xref: /openbmc/qemu/include/hw/riscv/sifive_cpu.h (revision 2b74dd91)
1 /*
2  * SiFive CPU types
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef HW_SIFIVE_CPU_H
21 #define HW_SIFIVE_CPU_H
22 
23 #if defined(TARGET_RISCV32)
24 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
25 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
26 #elif defined(TARGET_RISCV64)
27 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
28 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
29 #endif
30 
31 #endif /* HW_SIFIVE_CPU_H */
32