1*20f41c86SBin Meng /* 2*20f41c86SBin Meng * SiFive CPU types 3*20f41c86SBin Meng * 4*20f41c86SBin Meng * Copyright (c) 2017 SiFive, Inc. 5*20f41c86SBin Meng * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 6*20f41c86SBin Meng * 7*20f41c86SBin Meng * This program is free software; you can redistribute it and/or modify it 8*20f41c86SBin Meng * under the terms and conditions of the GNU General Public License, 9*20f41c86SBin Meng * version 2 or later, as published by the Free Software Foundation. 10*20f41c86SBin Meng * 11*20f41c86SBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 12*20f41c86SBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13*20f41c86SBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14*20f41c86SBin Meng * more details. 15*20f41c86SBin Meng * 16*20f41c86SBin Meng * You should have received a copy of the GNU General Public License along with 17*20f41c86SBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 18*20f41c86SBin Meng */ 19*20f41c86SBin Meng 20*20f41c86SBin Meng #ifndef HW_SIFIVE_CPU_H 21*20f41c86SBin Meng #define HW_SIFIVE_CPU_H 22*20f41c86SBin Meng 23*20f41c86SBin Meng #if defined(TARGET_RISCV32) 24*20f41c86SBin Meng #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 25*20f41c86SBin Meng #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 26*20f41c86SBin Meng #elif defined(TARGET_RISCV64) 27*20f41c86SBin Meng #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 28*20f41c86SBin Meng #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 29*20f41c86SBin Meng #endif 30*20f41c86SBin Meng 31*20f41c86SBin Meng #endif /* HW_SIFIVE_CPU_H */ 32