1 /* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_OPENTITAN_H 20 #define HW_OPENTITAN_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/intc/sifive_plic.h" 24 #include "hw/char/ibex_uart.h" 25 #include "hw/timer/ibex_timer.h" 26 #include "hw/ssi/ibex_spi_host.h" 27 #include "qom/object.h" 28 29 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" 30 OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC) 31 32 enum { 33 OPENTITAN_SPI_HOST0, 34 OPENTITAN_SPI_HOST1, 35 OPENTITAN_NUM_SPI_HOSTS, 36 }; 37 38 struct LowRISCIbexSoCState { 39 /*< private >*/ 40 SysBusDevice parent_obj; 41 42 /*< public >*/ 43 RISCVHartArrayState cpus; 44 SiFivePLICState plic; 45 IbexUartState uart; 46 IbexTimerState timer; 47 IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS]; 48 49 MemoryRegion flash_mem; 50 MemoryRegion rom; 51 MemoryRegion flash_alias; 52 }; 53 54 typedef struct OpenTitanState { 55 /*< private >*/ 56 SysBusDevice parent_obj; 57 58 /*< public >*/ 59 LowRISCIbexSoCState soc; 60 } OpenTitanState; 61 62 enum { 63 IBEX_DEV_ROM, 64 IBEX_DEV_RAM, 65 IBEX_DEV_FLASH, 66 IBEX_DEV_FLASH_VIRTUAL, 67 IBEX_DEV_UART, 68 IBEX_DEV_SPI_DEVICE, 69 IBEX_DEV_SPI_HOST0, 70 IBEX_DEV_SPI_HOST1, 71 IBEX_DEV_GPIO, 72 IBEX_DEV_I2C, 73 IBEX_DEV_PATTGEN, 74 IBEX_DEV_TIMER, 75 IBEX_DEV_SENSOR_CTRL, 76 IBEX_DEV_OTP_CTRL, 77 IBEX_DEV_PWRMGR, 78 IBEX_DEV_RSTMGR, 79 IBEX_DEV_CLKMGR, 80 IBEX_DEV_PINMUX, 81 IBEX_DEV_PADCTRL, 82 IBEX_DEV_USBDEV, 83 IBEX_DEV_FLASH_CTRL, 84 IBEX_DEV_PLIC, 85 IBEX_DEV_AES, 86 IBEX_DEV_HMAC, 87 IBEX_DEV_KMAC, 88 IBEX_DEV_KEYMGR, 89 IBEX_DEV_CSRNG, 90 IBEX_DEV_ENTROPY, 91 IBEX_DEV_EDNO, 92 IBEX_DEV_EDN1, 93 IBEX_DEV_ALERT_HANDLER, 94 IBEX_DEV_NMI_GEN, 95 IBEX_DEV_OTBN, 96 IBEX_DEV_PERI, 97 }; 98 99 enum { 100 IBEX_UART0_TX_WATERMARK_IRQ = 1, 101 IBEX_UART0_RX_WATERMARK_IRQ = 2, 102 IBEX_UART0_TX_EMPTY_IRQ = 3, 103 IBEX_UART0_RX_OVERFLOW_IRQ = 4, 104 IBEX_UART0_RX_FRAME_ERR_IRQ = 5, 105 IBEX_UART0_RX_BREAK_ERR_IRQ = 6, 106 IBEX_UART0_RX_TIMEOUT_IRQ = 7, 107 IBEX_UART0_RX_PARITY_ERR_IRQ = 8, 108 IBEX_TIMER_TIMEREXPIRED0_0 = 126, 109 IBEX_SPI_HOST0_ERR_IRQ = 150, 110 IBEX_SPI_HOST0_SPI_EVENT_IRQ = 151, 111 IBEX_SPI_HOST1_ERR_IRQ = 152, 112 IBEX_SPI_HOST1_SPI_EVENT_IRQ = 153, 113 }; 114 115 #endif 116