1 /* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_OPENTITAN_H 20 #define HW_OPENTITAN_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/intc/ibex_plic.h" 24 #include "hw/char/ibex_uart.h" 25 26 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" 27 #define RISCV_IBEX_SOC(obj) \ 28 OBJECT_CHECK(LowRISCIbexSoCState, (obj), TYPE_RISCV_IBEX_SOC) 29 30 typedef struct LowRISCIbexSoCState { 31 /*< private >*/ 32 SysBusDevice parent_obj; 33 34 /*< public >*/ 35 RISCVHartArrayState cpus; 36 IbexPlicState plic; 37 IbexUartState uart; 38 39 MemoryRegion flash_mem; 40 MemoryRegion rom; 41 } LowRISCIbexSoCState; 42 43 typedef struct OpenTitanState { 44 /*< private >*/ 45 SysBusDevice parent_obj; 46 47 /*< public >*/ 48 LowRISCIbexSoCState soc; 49 } OpenTitanState; 50 51 enum { 52 IBEX_ROM, 53 IBEX_RAM, 54 IBEX_FLASH, 55 IBEX_UART, 56 IBEX_GPIO, 57 IBEX_SPI, 58 IBEX_FLASH_CTRL, 59 IBEX_RV_TIMER, 60 IBEX_AES, 61 IBEX_HMAC, 62 IBEX_PLIC, 63 IBEX_PWRMGR, 64 IBEX_RSTMGR, 65 IBEX_CLKMGR, 66 IBEX_PINMUX, 67 IBEX_ALERT_HANDLER, 68 IBEX_NMI_GEN, 69 IBEX_USBDEV, 70 IBEX_PADCTRL, 71 }; 72 73 enum { 74 IBEX_UART_RX_PARITY_ERR_IRQ = 0x28, 75 IBEX_UART_RX_TIMEOUT_IRQ = 0x27, 76 IBEX_UART_RX_BREAK_ERR_IRQ = 0x26, 77 IBEX_UART_RX_FRAME_ERR_IRQ = 0x25, 78 IBEX_UART_RX_OVERFLOW_IRQ = 0x24, 79 IBEX_UART_TX_EMPTY_IRQ = 0x23, 80 IBEX_UART_RX_WATERMARK_IRQ = 0x22, 81 IBEX_UART_TX_WATERMARK_IRQ = 0x21, 82 }; 83 84 #endif 85