1 /* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_OPENTITAN_H 20 #define HW_OPENTITAN_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/intc/sifive_plic.h" 24 #include "hw/char/ibex_uart.h" 25 #include "hw/timer/ibex_timer.h" 26 #include "qom/object.h" 27 28 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" 29 OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC) 30 31 struct LowRISCIbexSoCState { 32 /*< private >*/ 33 SysBusDevice parent_obj; 34 35 /*< public >*/ 36 RISCVHartArrayState cpus; 37 SiFivePLICState plic; 38 IbexUartState uart; 39 IbexTimerState timer; 40 41 MemoryRegion flash_mem; 42 MemoryRegion rom; 43 MemoryRegion flash_alias; 44 }; 45 46 typedef struct OpenTitanState { 47 /*< private >*/ 48 SysBusDevice parent_obj; 49 50 /*< public >*/ 51 LowRISCIbexSoCState soc; 52 } OpenTitanState; 53 54 enum { 55 IBEX_DEV_ROM, 56 IBEX_DEV_RAM, 57 IBEX_DEV_FLASH, 58 IBEX_DEV_FLASH_VIRTUAL, 59 IBEX_DEV_UART, 60 IBEX_DEV_GPIO, 61 IBEX_DEV_SPI, 62 IBEX_DEV_I2C, 63 IBEX_DEV_PATTGEN, 64 IBEX_DEV_TIMER, 65 IBEX_DEV_SENSOR_CTRL, 66 IBEX_DEV_OTP_CTRL, 67 IBEX_DEV_PWRMGR, 68 IBEX_DEV_RSTMGR, 69 IBEX_DEV_CLKMGR, 70 IBEX_DEV_PINMUX, 71 IBEX_DEV_PADCTRL, 72 IBEX_DEV_USBDEV, 73 IBEX_DEV_FLASH_CTRL, 74 IBEX_DEV_PLIC, 75 IBEX_DEV_AES, 76 IBEX_DEV_HMAC, 77 IBEX_DEV_KMAC, 78 IBEX_DEV_KEYMGR, 79 IBEX_DEV_CSRNG, 80 IBEX_DEV_ENTROPY, 81 IBEX_DEV_EDNO, 82 IBEX_DEV_EDN1, 83 IBEX_DEV_ALERT_HANDLER, 84 IBEX_DEV_NMI_GEN, 85 IBEX_DEV_OTBN, 86 IBEX_DEV_PERI, 87 }; 88 89 enum { 90 IBEX_TIMER_TIMEREXPIRED0_0 = 126, 91 IBEX_UART0_RX_PARITY_ERR_IRQ = 8, 92 IBEX_UART0_RX_TIMEOUT_IRQ = 7, 93 IBEX_UART0_RX_BREAK_ERR_IRQ = 6, 94 IBEX_UART0_RX_FRAME_ERR_IRQ = 5, 95 IBEX_UART0_RX_OVERFLOW_IRQ = 4, 96 IBEX_UART0_TX_EMPTY_IRQ = 3, 97 IBEX_UART0_RX_WATERMARK_IRQ = 2, 98 IBEX_UART0_TX_WATERMARK_IRQ = 1, 99 }; 100 101 #endif 102