1 /* 2 * QEMU RISC-V NUMA Helper 3 * 4 * Copyright (c) 2020 Western Digital Corporation or its affiliates. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RISCV_NUMA_H 20 #define RISCV_NUMA_H 21 22 #include "hw/boards.h" 23 #include "hw/sysbus.h" 24 #include "sysemu/numa.h" 25 26 /** 27 * riscv_socket_count: 28 * @ms: pointer to machine state 29 * 30 * Returns: number of sockets for a numa system and 1 for a non-numa system 31 */ 32 int riscv_socket_count(const MachineState *ms); 33 34 /** 35 * riscv_socket_first_hartid: 36 * @ms: pointer to machine state 37 * @socket_id: socket index 38 * 39 * Returns: first hartid for a valid socket and -1 for an invalid socket 40 */ 41 int riscv_socket_first_hartid(const MachineState *ms, int socket_id); 42 43 /** 44 * riscv_socket_last_hartid: 45 * @ms: pointer to machine state 46 * @socket_id: socket index 47 * 48 * Returns: last hartid for a valid socket and -1 for an invalid socket 49 */ 50 int riscv_socket_last_hartid(const MachineState *ms, int socket_id); 51 52 /** 53 * riscv_socket_hart_count: 54 * @ms: pointer to machine state 55 * @socket_id: socket index 56 * 57 * Returns: number of harts for a valid socket and -1 for an invalid socket 58 */ 59 int riscv_socket_hart_count(const MachineState *ms, int socket_id); 60 61 /** 62 * riscv_socket_mem_offset: 63 * @ms: pointer to machine state 64 * @socket_id: socket index 65 * 66 * Returns: offset of ram belonging to given socket 67 */ 68 uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id); 69 70 /** 71 * riscv_socket_mem_size: 72 * @ms: pointer to machine state 73 * @socket_id: socket index 74 * 75 * Returns: size of ram belonging to given socket 76 */ 77 uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id); 78 79 /** 80 * riscv_socket_check_hartids: 81 * @ms: pointer to machine state 82 * @socket_id: socket index 83 * 84 * Returns: true if hardids belonging to given socket are contiguous else false 85 */ 86 bool riscv_socket_check_hartids(const MachineState *ms, int socket_id); 87 88 /** 89 * riscv_socket_fdt_write_id: 90 * @ms: pointer to machine state 91 * @socket_id: socket index 92 * 93 * Write NUMA node-id FDT property in MachineState->fdt 94 */ 95 void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, 96 int socket_id); 97 98 /** 99 * riscv_socket_fdt_write_distance_matrix: 100 * @ms: pointer to machine state 101 * @socket_id: socket index 102 * 103 * Write NUMA distance matrix in MachineState->fdt 104 */ 105 void riscv_socket_fdt_write_distance_matrix(const MachineState *ms); 106 107 CpuInstanceProperties 108 riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); 109 110 int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx); 111 112 const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms); 113 114 #endif /* RISCV_NUMA_H */ 115