1 /*
2  * Microchip PolarFire SoC machine interface
3  *
4  * Copyright (c) 2020 Wind River Systems, Inc.
5  *
6  * Author:
7  *   Bin Meng <bin.meng@windriver.com>
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms and conditions of the GNU General Public License,
11  * version 2 or later, as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program.  If not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #ifndef HW_MICROCHIP_PFSOC_H
23 #define HW_MICROCHIP_PFSOC_H
24 
25 #include "hw/char/mchp_pfsoc_mmuart.h"
26 #include "hw/dma/sifive_pdma.h"
27 #include "hw/net/cadence_gem.h"
28 #include "hw/sd/cadence_sdhci.h"
29 
30 typedef struct MicrochipPFSoCState {
31     /*< private >*/
32     DeviceState parent_obj;
33 
34     /*< public >*/
35     CPUClusterState e_cluster;
36     CPUClusterState u_cluster;
37     RISCVHartArrayState e_cpus;
38     RISCVHartArrayState u_cpus;
39     DeviceState *plic;
40     MchpPfSoCMMUartState *serial0;
41     MchpPfSoCMMUartState *serial1;
42     MchpPfSoCMMUartState *serial2;
43     MchpPfSoCMMUartState *serial3;
44     MchpPfSoCMMUartState *serial4;
45     SiFivePDMAState dma;
46     CadenceGEMState gem0;
47     CadenceGEMState gem1;
48     CadenceSDHCIState sdhci;
49 } MicrochipPFSoCState;
50 
51 #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
52 #define MICROCHIP_PFSOC(obj) \
53     OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
54 
55 typedef struct MicrochipIcicleKitState {
56     /*< private >*/
57     MachineState parent_obj;
58 
59     /*< public >*/
60     MicrochipPFSoCState soc;
61 } MicrochipIcicleKitState;
62 
63 #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
64     MACHINE_TYPE_NAME("microchip-icicle-kit")
65 #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
66     OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
67                  TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
68 
69 enum {
70     MICROCHIP_PFSOC_DEBUG,
71     MICROCHIP_PFSOC_E51_DTIM,
72     MICROCHIP_PFSOC_BUSERR_UNIT0,
73     MICROCHIP_PFSOC_BUSERR_UNIT1,
74     MICROCHIP_PFSOC_BUSERR_UNIT2,
75     MICROCHIP_PFSOC_BUSERR_UNIT3,
76     MICROCHIP_PFSOC_BUSERR_UNIT4,
77     MICROCHIP_PFSOC_CLINT,
78     MICROCHIP_PFSOC_L2CC,
79     MICROCHIP_PFSOC_DMA,
80     MICROCHIP_PFSOC_L2LIM,
81     MICROCHIP_PFSOC_PLIC,
82     MICROCHIP_PFSOC_MMUART0,
83     MICROCHIP_PFSOC_SYSREG,
84     MICROCHIP_PFSOC_MPUCFG,
85     MICROCHIP_PFSOC_EMMC_SD,
86     MICROCHIP_PFSOC_MMUART1,
87     MICROCHIP_PFSOC_MMUART2,
88     MICROCHIP_PFSOC_MMUART3,
89     MICROCHIP_PFSOC_MMUART4,
90     MICROCHIP_PFSOC_GEM0,
91     MICROCHIP_PFSOC_GEM1,
92     MICROCHIP_PFSOC_GPIO0,
93     MICROCHIP_PFSOC_GPIO1,
94     MICROCHIP_PFSOC_GPIO2,
95     MICROCHIP_PFSOC_ENVM_CFG,
96     MICROCHIP_PFSOC_ENVM_DATA,
97     MICROCHIP_PFSOC_IOSCB_CFG,
98     MICROCHIP_PFSOC_DRAM,
99 };
100 
101 enum {
102     MICROCHIP_PFSOC_DMA_IRQ0 = 5,
103     MICROCHIP_PFSOC_DMA_IRQ1 = 6,
104     MICROCHIP_PFSOC_DMA_IRQ2 = 7,
105     MICROCHIP_PFSOC_DMA_IRQ3 = 8,
106     MICROCHIP_PFSOC_DMA_IRQ4 = 9,
107     MICROCHIP_PFSOC_DMA_IRQ5 = 10,
108     MICROCHIP_PFSOC_DMA_IRQ6 = 11,
109     MICROCHIP_PFSOC_DMA_IRQ7 = 12,
110     MICROCHIP_PFSOC_GEM0_IRQ = 64,
111     MICROCHIP_PFSOC_GEM1_IRQ = 70,
112     MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
113     MICROCHIP_PFSOC_MMUART0_IRQ = 90,
114     MICROCHIP_PFSOC_MMUART1_IRQ = 91,
115     MICROCHIP_PFSOC_MMUART2_IRQ = 92,
116     MICROCHIP_PFSOC_MMUART3_IRQ = 93,
117     MICROCHIP_PFSOC_MMUART4_IRQ = 94,
118 };
119 
120 #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
121 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
122 
123 #define MICROCHIP_PFSOC_PLIC_HART_CONFIG        "MS"
124 #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
125 #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
126 #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
127 #define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
128 #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
129 #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
130 #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE       0x200000
131 #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE     0x1000
132 
133 #endif /* HW_MICROCHIP_PFSOC_H */
134