156f6e31eSBin Meng /* 256f6e31eSBin Meng * Microchip PolarFire SoC machine interface 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 1056f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 1156f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 1256f6e31eSBin Meng * 1356f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 1456f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1556f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1656f6e31eSBin Meng * more details. 1756f6e31eSBin Meng * 1856f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 1956f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 2056f6e31eSBin Meng */ 2156f6e31eSBin Meng 2256f6e31eSBin Meng #ifndef HW_MICROCHIP_PFSOC_H 2356f6e31eSBin Meng #define HW_MICROCHIP_PFSOC_H 2456f6e31eSBin Meng 258f2ac39dSBin Meng #include "hw/char/mchp_pfsoc_mmuart.h" 267124e27bSBin Meng #include "hw/dma/sifive_pdma.h" 27933f73f1SBin Meng #include "hw/misc/mchp_pfsoc_dmc.h" 28e35d6179SBin Meng #include "hw/misc/mchp_pfsoc_ioscb.h" 29*cdd58c70SBin Meng #include "hw/misc/mchp_pfsoc_sysreg.h" 3047374b07SBin Meng #include "hw/net/cadence_gem.h" 31898dc008SBin Meng #include "hw/sd/cadence_sdhci.h" 328f2ac39dSBin Meng 3356f6e31eSBin Meng typedef struct MicrochipPFSoCState { 3456f6e31eSBin Meng /*< private >*/ 3556f6e31eSBin Meng DeviceState parent_obj; 3656f6e31eSBin Meng 3756f6e31eSBin Meng /*< public >*/ 3856f6e31eSBin Meng CPUClusterState e_cluster; 3956f6e31eSBin Meng CPUClusterState u_cluster; 4056f6e31eSBin Meng RISCVHartArrayState e_cpus; 4156f6e31eSBin Meng RISCVHartArrayState u_cpus; 4256f6e31eSBin Meng DeviceState *plic; 43933f73f1SBin Meng MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; 44933f73f1SBin Meng MchpPfSoCDdrCfgState ddr_cfg; 45e35d6179SBin Meng MchpPfSoCIoscbState ioscb; 468f2ac39dSBin Meng MchpPfSoCMMUartState *serial0; 478f2ac39dSBin Meng MchpPfSoCMMUartState *serial1; 488f2ac39dSBin Meng MchpPfSoCMMUartState *serial2; 498f2ac39dSBin Meng MchpPfSoCMMUartState *serial3; 508f2ac39dSBin Meng MchpPfSoCMMUartState *serial4; 51*cdd58c70SBin Meng MchpPfSoCSysregState sysreg; 527124e27bSBin Meng SiFivePDMAState dma; 5347374b07SBin Meng CadenceGEMState gem0; 5447374b07SBin Meng CadenceGEMState gem1; 55898dc008SBin Meng CadenceSDHCIState sdhci; 5656f6e31eSBin Meng } MicrochipPFSoCState; 5756f6e31eSBin Meng 5856f6e31eSBin Meng #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" 5956f6e31eSBin Meng #define MICROCHIP_PFSOC(obj) \ 6056f6e31eSBin Meng OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) 6156f6e31eSBin Meng 6256f6e31eSBin Meng typedef struct MicrochipIcicleKitState { 6356f6e31eSBin Meng /*< private >*/ 6456f6e31eSBin Meng MachineState parent_obj; 6556f6e31eSBin Meng 6656f6e31eSBin Meng /*< public >*/ 6756f6e31eSBin Meng MicrochipPFSoCState soc; 6856f6e31eSBin Meng } MicrochipIcicleKitState; 6956f6e31eSBin Meng 7056f6e31eSBin Meng #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ 7156f6e31eSBin Meng MACHINE_TYPE_NAME("microchip-icicle-kit") 7256f6e31eSBin Meng #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ 7356f6e31eSBin Meng OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ 7456f6e31eSBin Meng TYPE_MICROCHIP_ICICLE_KIT_MACHINE) 7556f6e31eSBin Meng 7656f6e31eSBin Meng enum { 7756f6e31eSBin Meng MICROCHIP_PFSOC_DEBUG, 7856f6e31eSBin Meng MICROCHIP_PFSOC_E51_DTIM, 7956f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT0, 8056f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT1, 8156f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT2, 8256f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT3, 8356f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT4, 8456f6e31eSBin Meng MICROCHIP_PFSOC_CLINT, 8556f6e31eSBin Meng MICROCHIP_PFSOC_L2CC, 867124e27bSBin Meng MICROCHIP_PFSOC_DMA, 8756f6e31eSBin Meng MICROCHIP_PFSOC_L2LIM, 8856f6e31eSBin Meng MICROCHIP_PFSOC_PLIC, 898f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0, 9056f6e31eSBin Meng MICROCHIP_PFSOC_SYSREG, 9156f6e31eSBin Meng MICROCHIP_PFSOC_MPUCFG, 92933f73f1SBin Meng MICROCHIP_PFSOC_DDR_SGMII_PHY, 93898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD, 94933f73f1SBin Meng MICROCHIP_PFSOC_DDR_CFG, 958f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1, 968f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2, 978f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3, 988f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4, 9947374b07SBin Meng MICROCHIP_PFSOC_GEM0, 10047374b07SBin Meng MICROCHIP_PFSOC_GEM1, 101ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO0, 102ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO1, 103ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO2, 10456f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_CFG, 10556f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_DATA, 106e35d6179SBin Meng MICROCHIP_PFSOC_IOSCB, 10756f6e31eSBin Meng MICROCHIP_PFSOC_DRAM, 10856f6e31eSBin Meng }; 10956f6e31eSBin Meng 1108f2ac39dSBin Meng enum { 1117124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 = 5, 1127124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ1 = 6, 1137124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ2 = 7, 1147124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ3 = 8, 1157124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ4 = 9, 1167124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ5 = 10, 1177124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ6 = 11, 1187124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ7 = 12, 11947374b07SBin Meng MICROCHIP_PFSOC_GEM0_IRQ = 64, 12047374b07SBin Meng MICROCHIP_PFSOC_GEM1_IRQ = 70, 121898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, 1228f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0_IRQ = 90, 1238f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1_IRQ = 91, 1248f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2_IRQ = 92, 1258f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3_IRQ = 93, 1268f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4_IRQ = 94, 1278f2ac39dSBin Meng }; 1288f2ac39dSBin Meng 12956f6e31eSBin Meng #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 13056f6e31eSBin Meng #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 13156f6e31eSBin Meng 13256f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS" 13356f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 13456f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 13556f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 13656f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 13756f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 13856f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 13956f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 14056f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 14156f6e31eSBin Meng 14256f6e31eSBin Meng #endif /* HW_MICROCHIP_PFSOC_H */ 143