156f6e31eSBin Meng /* 256f6e31eSBin Meng * Microchip PolarFire SoC machine interface 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 1056f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 1156f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 1256f6e31eSBin Meng * 1356f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 1456f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1556f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1656f6e31eSBin Meng * more details. 1756f6e31eSBin Meng * 1856f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 1956f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 2056f6e31eSBin Meng */ 2156f6e31eSBin Meng 2256f6e31eSBin Meng #ifndef HW_MICROCHIP_PFSOC_H 2356f6e31eSBin Meng #define HW_MICROCHIP_PFSOC_H 2456f6e31eSBin Meng 258f2ac39dSBin Meng #include "hw/char/mchp_pfsoc_mmuart.h" 267124e27bSBin Meng #include "hw/dma/sifive_pdma.h" 27*933f73f1SBin Meng #include "hw/misc/mchp_pfsoc_dmc.h" 2847374b07SBin Meng #include "hw/net/cadence_gem.h" 29898dc008SBin Meng #include "hw/sd/cadence_sdhci.h" 308f2ac39dSBin Meng 3156f6e31eSBin Meng typedef struct MicrochipPFSoCState { 3256f6e31eSBin Meng /*< private >*/ 3356f6e31eSBin Meng DeviceState parent_obj; 3456f6e31eSBin Meng 3556f6e31eSBin Meng /*< public >*/ 3656f6e31eSBin Meng CPUClusterState e_cluster; 3756f6e31eSBin Meng CPUClusterState u_cluster; 3856f6e31eSBin Meng RISCVHartArrayState e_cpus; 3956f6e31eSBin Meng RISCVHartArrayState u_cpus; 4056f6e31eSBin Meng DeviceState *plic; 41*933f73f1SBin Meng MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; 42*933f73f1SBin Meng MchpPfSoCDdrCfgState ddr_cfg; 438f2ac39dSBin Meng MchpPfSoCMMUartState *serial0; 448f2ac39dSBin Meng MchpPfSoCMMUartState *serial1; 458f2ac39dSBin Meng MchpPfSoCMMUartState *serial2; 468f2ac39dSBin Meng MchpPfSoCMMUartState *serial3; 478f2ac39dSBin Meng MchpPfSoCMMUartState *serial4; 487124e27bSBin Meng SiFivePDMAState dma; 4947374b07SBin Meng CadenceGEMState gem0; 5047374b07SBin Meng CadenceGEMState gem1; 51898dc008SBin Meng CadenceSDHCIState sdhci; 5256f6e31eSBin Meng } MicrochipPFSoCState; 5356f6e31eSBin Meng 5456f6e31eSBin Meng #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" 5556f6e31eSBin Meng #define MICROCHIP_PFSOC(obj) \ 5656f6e31eSBin Meng OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) 5756f6e31eSBin Meng 5856f6e31eSBin Meng typedef struct MicrochipIcicleKitState { 5956f6e31eSBin Meng /*< private >*/ 6056f6e31eSBin Meng MachineState parent_obj; 6156f6e31eSBin Meng 6256f6e31eSBin Meng /*< public >*/ 6356f6e31eSBin Meng MicrochipPFSoCState soc; 6456f6e31eSBin Meng } MicrochipIcicleKitState; 6556f6e31eSBin Meng 6656f6e31eSBin Meng #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ 6756f6e31eSBin Meng MACHINE_TYPE_NAME("microchip-icicle-kit") 6856f6e31eSBin Meng #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ 6956f6e31eSBin Meng OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ 7056f6e31eSBin Meng TYPE_MICROCHIP_ICICLE_KIT_MACHINE) 7156f6e31eSBin Meng 7256f6e31eSBin Meng enum { 7356f6e31eSBin Meng MICROCHIP_PFSOC_DEBUG, 7456f6e31eSBin Meng MICROCHIP_PFSOC_E51_DTIM, 7556f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT0, 7656f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT1, 7756f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT2, 7856f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT3, 7956f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT4, 8056f6e31eSBin Meng MICROCHIP_PFSOC_CLINT, 8156f6e31eSBin Meng MICROCHIP_PFSOC_L2CC, 827124e27bSBin Meng MICROCHIP_PFSOC_DMA, 8356f6e31eSBin Meng MICROCHIP_PFSOC_L2LIM, 8456f6e31eSBin Meng MICROCHIP_PFSOC_PLIC, 858f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0, 8656f6e31eSBin Meng MICROCHIP_PFSOC_SYSREG, 8756f6e31eSBin Meng MICROCHIP_PFSOC_MPUCFG, 88*933f73f1SBin Meng MICROCHIP_PFSOC_DDR_SGMII_PHY, 89898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD, 90*933f73f1SBin Meng MICROCHIP_PFSOC_DDR_CFG, 918f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1, 928f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2, 938f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3, 948f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4, 9547374b07SBin Meng MICROCHIP_PFSOC_GEM0, 9647374b07SBin Meng MICROCHIP_PFSOC_GEM1, 97ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO0, 98ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO1, 99ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO2, 10056f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_CFG, 10156f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_DATA, 10256f6e31eSBin Meng MICROCHIP_PFSOC_IOSCB_CFG, 10356f6e31eSBin Meng MICROCHIP_PFSOC_DRAM, 10456f6e31eSBin Meng }; 10556f6e31eSBin Meng 1068f2ac39dSBin Meng enum { 1077124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 = 5, 1087124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ1 = 6, 1097124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ2 = 7, 1107124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ3 = 8, 1117124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ4 = 9, 1127124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ5 = 10, 1137124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ6 = 11, 1147124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ7 = 12, 11547374b07SBin Meng MICROCHIP_PFSOC_GEM0_IRQ = 64, 11647374b07SBin Meng MICROCHIP_PFSOC_GEM1_IRQ = 70, 117898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, 1188f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0_IRQ = 90, 1198f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1_IRQ = 91, 1208f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2_IRQ = 92, 1218f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3_IRQ = 93, 1228f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4_IRQ = 94, 1238f2ac39dSBin Meng }; 1248f2ac39dSBin Meng 12556f6e31eSBin Meng #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 12656f6e31eSBin Meng #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 12756f6e31eSBin Meng 12856f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS" 12956f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 13056f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 13156f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 13256f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 13356f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 13456f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 13556f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 13656f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 13756f6e31eSBin Meng 13856f6e31eSBin Meng #endif /* HW_MICROCHIP_PFSOC_H */ 139