156f6e31eSBin Meng /* 256f6e31eSBin Meng * Microchip PolarFire SoC machine interface 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 1056f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 1156f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 1256f6e31eSBin Meng * 1356f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 1456f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1556f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1656f6e31eSBin Meng * more details. 1756f6e31eSBin Meng * 1856f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 1956f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 2056f6e31eSBin Meng */ 2156f6e31eSBin Meng 2256f6e31eSBin Meng #ifndef HW_MICROCHIP_PFSOC_H 2356f6e31eSBin Meng #define HW_MICROCHIP_PFSOC_H 2456f6e31eSBin Meng 25*7a5951f6SMarkus Armbruster #include "hw/boards.h" 268f2ac39dSBin Meng #include "hw/char/mchp_pfsoc_mmuart.h" 27*7a5951f6SMarkus Armbruster #include "hw/cpu/cluster.h" 287124e27bSBin Meng #include "hw/dma/sifive_pdma.h" 29933f73f1SBin Meng #include "hw/misc/mchp_pfsoc_dmc.h" 30e35d6179SBin Meng #include "hw/misc/mchp_pfsoc_ioscb.h" 31cdd58c70SBin Meng #include "hw/misc/mchp_pfsoc_sysreg.h" 3247374b07SBin Meng #include "hw/net/cadence_gem.h" 33898dc008SBin Meng #include "hw/sd/cadence_sdhci.h" 34*7a5951f6SMarkus Armbruster #include "hw/riscv/riscv_hart.h" 358f2ac39dSBin Meng 3656f6e31eSBin Meng typedef struct MicrochipPFSoCState { 3756f6e31eSBin Meng /*< private >*/ 3856f6e31eSBin Meng DeviceState parent_obj; 3956f6e31eSBin Meng 4056f6e31eSBin Meng /*< public >*/ 4156f6e31eSBin Meng CPUClusterState e_cluster; 4256f6e31eSBin Meng CPUClusterState u_cluster; 4356f6e31eSBin Meng RISCVHartArrayState e_cpus; 4456f6e31eSBin Meng RISCVHartArrayState u_cpus; 4556f6e31eSBin Meng DeviceState *plic; 46933f73f1SBin Meng MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; 47933f73f1SBin Meng MchpPfSoCDdrCfgState ddr_cfg; 48e35d6179SBin Meng MchpPfSoCIoscbState ioscb; 498f2ac39dSBin Meng MchpPfSoCMMUartState *serial0; 508f2ac39dSBin Meng MchpPfSoCMMUartState *serial1; 518f2ac39dSBin Meng MchpPfSoCMMUartState *serial2; 528f2ac39dSBin Meng MchpPfSoCMMUartState *serial3; 538f2ac39dSBin Meng MchpPfSoCMMUartState *serial4; 54cdd58c70SBin Meng MchpPfSoCSysregState sysreg; 557124e27bSBin Meng SiFivePDMAState dma; 5647374b07SBin Meng CadenceGEMState gem0; 5747374b07SBin Meng CadenceGEMState gem1; 58898dc008SBin Meng CadenceSDHCIState sdhci; 5956f6e31eSBin Meng } MicrochipPFSoCState; 6056f6e31eSBin Meng 6156f6e31eSBin Meng #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" 6256f6e31eSBin Meng #define MICROCHIP_PFSOC(obj) \ 6356f6e31eSBin Meng OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) 6456f6e31eSBin Meng 6556f6e31eSBin Meng typedef struct MicrochipIcicleKitState { 6656f6e31eSBin Meng /*< private >*/ 6756f6e31eSBin Meng MachineState parent_obj; 6856f6e31eSBin Meng 6956f6e31eSBin Meng /*< public >*/ 7056f6e31eSBin Meng MicrochipPFSoCState soc; 7156f6e31eSBin Meng } MicrochipIcicleKitState; 7256f6e31eSBin Meng 7356f6e31eSBin Meng #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ 7456f6e31eSBin Meng MACHINE_TYPE_NAME("microchip-icicle-kit") 7556f6e31eSBin Meng #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ 7656f6e31eSBin Meng OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ 7756f6e31eSBin Meng TYPE_MICROCHIP_ICICLE_KIT_MACHINE) 7856f6e31eSBin Meng 7956f6e31eSBin Meng enum { 8027c22b2dSBin Meng MICROCHIP_PFSOC_RSVD0, 8156f6e31eSBin Meng MICROCHIP_PFSOC_DEBUG, 8256f6e31eSBin Meng MICROCHIP_PFSOC_E51_DTIM, 8356f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT0, 8456f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT1, 8556f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT2, 8656f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT3, 8756f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT4, 8856f6e31eSBin Meng MICROCHIP_PFSOC_CLINT, 8956f6e31eSBin Meng MICROCHIP_PFSOC_L2CC, 907124e27bSBin Meng MICROCHIP_PFSOC_DMA, 9156f6e31eSBin Meng MICROCHIP_PFSOC_L2LIM, 9256f6e31eSBin Meng MICROCHIP_PFSOC_PLIC, 938f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0, 9425da6e31SConor Dooley MICROCHIP_PFSOC_WDOG0, 9556f6e31eSBin Meng MICROCHIP_PFSOC_SYSREG, 9625da6e31SConor Dooley MICROCHIP_PFSOC_AXISW, 9756f6e31eSBin Meng MICROCHIP_PFSOC_MPUCFG, 9825da6e31SConor Dooley MICROCHIP_PFSOC_FMETER, 99933f73f1SBin Meng MICROCHIP_PFSOC_DDR_SGMII_PHY, 100898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD, 101933f73f1SBin Meng MICROCHIP_PFSOC_DDR_CFG, 1028f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1, 1038f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2, 1048f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3, 1058f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4, 10625da6e31SConor Dooley MICROCHIP_PFSOC_WDOG1, 10725da6e31SConor Dooley MICROCHIP_PFSOC_WDOG2, 10825da6e31SConor Dooley MICROCHIP_PFSOC_WDOG3, 10925da6e31SConor Dooley MICROCHIP_PFSOC_WDOG4, 110dfc973ecSVitaly Wool MICROCHIP_PFSOC_SPI0, 111dfc973ecSVitaly Wool MICROCHIP_PFSOC_SPI1, 11225da6e31SConor Dooley MICROCHIP_PFSOC_I2C0, 11390742c54SBin Meng MICROCHIP_PFSOC_I2C1, 11425da6e31SConor Dooley MICROCHIP_PFSOC_CAN0, 11525da6e31SConor Dooley MICROCHIP_PFSOC_CAN1, 11647374b07SBin Meng MICROCHIP_PFSOC_GEM0, 11747374b07SBin Meng MICROCHIP_PFSOC_GEM1, 118ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO0, 119ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO1, 120ce908a2fSBin Meng MICROCHIP_PFSOC_GPIO2, 12125da6e31SConor Dooley MICROCHIP_PFSOC_RTC, 12256f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_CFG, 12356f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_DATA, 12425da6e31SConor Dooley MICROCHIP_PFSOC_USB, 125dfc973ecSVitaly Wool MICROCHIP_PFSOC_QSPI_XIP, 126e35d6179SBin Meng MICROCHIP_PFSOC_IOSCB, 1278d32e374SConor Dooley MICROCHIP_PFSOC_FABRIC_FIC0, 1288d32e374SConor Dooley MICROCHIP_PFSOC_FABRIC_FIC1, 12925da6e31SConor Dooley MICROCHIP_PFSOC_FABRIC_FIC3, 130f03100d7SBin Meng MICROCHIP_PFSOC_DRAM_LO, 131f03100d7SBin Meng MICROCHIP_PFSOC_DRAM_LO_ALIAS, 132f03100d7SBin Meng MICROCHIP_PFSOC_DRAM_HI, 133f03100d7SBin Meng MICROCHIP_PFSOC_DRAM_HI_ALIAS 13456f6e31eSBin Meng }; 13556f6e31eSBin Meng 1368f2ac39dSBin Meng enum { 1377124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 = 5, 1387124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ1 = 6, 1397124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ2 = 7, 1407124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ3 = 8, 1417124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ4 = 9, 1427124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ5 = 10, 1437124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ6 = 11, 1447124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ7 = 12, 14547374b07SBin Meng MICROCHIP_PFSOC_GEM0_IRQ = 64, 14647374b07SBin Meng MICROCHIP_PFSOC_GEM1_IRQ = 70, 147898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, 1488f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0_IRQ = 90, 1498f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1_IRQ = 91, 1508f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2_IRQ = 92, 1518f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3_IRQ = 93, 1528f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4_IRQ = 94, 153592f0a94SConor Dooley MICROCHIP_PFSOC_MAILBOX_IRQ = 96, 1548f2ac39dSBin Meng }; 1558f2ac39dSBin Meng 15656f6e31eSBin Meng #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 15756f6e31eSBin Meng #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 15856f6e31eSBin Meng 1591257418bSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 16056f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 1615decd2c5SBin Meng #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00 16256f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 16356f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 16456f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 16556f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 16656f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 16756f6e31eSBin Meng 16856f6e31eSBin Meng #endif /* HW_MICROCHIP_PFSOC_H */ 169