156f6e31eSBin Meng /* 256f6e31eSBin Meng * Microchip PolarFire SoC machine interface 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 1056f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 1156f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 1256f6e31eSBin Meng * 1356f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 1456f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1556f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1656f6e31eSBin Meng * more details. 1756f6e31eSBin Meng * 1856f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 1956f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 2056f6e31eSBin Meng */ 2156f6e31eSBin Meng 2256f6e31eSBin Meng #ifndef HW_MICROCHIP_PFSOC_H 2356f6e31eSBin Meng #define HW_MICROCHIP_PFSOC_H 2456f6e31eSBin Meng 258f2ac39dSBin Meng #include "hw/char/mchp_pfsoc_mmuart.h" 26*7124e27bSBin Meng #include "hw/dma/sifive_pdma.h" 27898dc008SBin Meng #include "hw/sd/cadence_sdhci.h" 288f2ac39dSBin Meng 2956f6e31eSBin Meng typedef struct MicrochipPFSoCState { 3056f6e31eSBin Meng /*< private >*/ 3156f6e31eSBin Meng DeviceState parent_obj; 3256f6e31eSBin Meng 3356f6e31eSBin Meng /*< public >*/ 3456f6e31eSBin Meng CPUClusterState e_cluster; 3556f6e31eSBin Meng CPUClusterState u_cluster; 3656f6e31eSBin Meng RISCVHartArrayState e_cpus; 3756f6e31eSBin Meng RISCVHartArrayState u_cpus; 3856f6e31eSBin Meng DeviceState *plic; 398f2ac39dSBin Meng MchpPfSoCMMUartState *serial0; 408f2ac39dSBin Meng MchpPfSoCMMUartState *serial1; 418f2ac39dSBin Meng MchpPfSoCMMUartState *serial2; 428f2ac39dSBin Meng MchpPfSoCMMUartState *serial3; 438f2ac39dSBin Meng MchpPfSoCMMUartState *serial4; 44*7124e27bSBin Meng SiFivePDMAState dma; 45898dc008SBin Meng CadenceSDHCIState sdhci; 4656f6e31eSBin Meng } MicrochipPFSoCState; 4756f6e31eSBin Meng 4856f6e31eSBin Meng #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" 4956f6e31eSBin Meng #define MICROCHIP_PFSOC(obj) \ 5056f6e31eSBin Meng OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) 5156f6e31eSBin Meng 5256f6e31eSBin Meng typedef struct MicrochipIcicleKitState { 5356f6e31eSBin Meng /*< private >*/ 5456f6e31eSBin Meng MachineState parent_obj; 5556f6e31eSBin Meng 5656f6e31eSBin Meng /*< public >*/ 5756f6e31eSBin Meng MicrochipPFSoCState soc; 5856f6e31eSBin Meng } MicrochipIcicleKitState; 5956f6e31eSBin Meng 6056f6e31eSBin Meng #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ 6156f6e31eSBin Meng MACHINE_TYPE_NAME("microchip-icicle-kit") 6256f6e31eSBin Meng #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ 6356f6e31eSBin Meng OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ 6456f6e31eSBin Meng TYPE_MICROCHIP_ICICLE_KIT_MACHINE) 6556f6e31eSBin Meng 6656f6e31eSBin Meng enum { 6756f6e31eSBin Meng MICROCHIP_PFSOC_DEBUG, 6856f6e31eSBin Meng MICROCHIP_PFSOC_E51_DTIM, 6956f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT0, 7056f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT1, 7156f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT2, 7256f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT3, 7356f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT4, 7456f6e31eSBin Meng MICROCHIP_PFSOC_CLINT, 7556f6e31eSBin Meng MICROCHIP_PFSOC_L2CC, 76*7124e27bSBin Meng MICROCHIP_PFSOC_DMA, 7756f6e31eSBin Meng MICROCHIP_PFSOC_L2LIM, 7856f6e31eSBin Meng MICROCHIP_PFSOC_PLIC, 798f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0, 8056f6e31eSBin Meng MICROCHIP_PFSOC_SYSREG, 8156f6e31eSBin Meng MICROCHIP_PFSOC_MPUCFG, 82898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD, 838f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1, 848f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2, 858f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3, 868f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4, 8756f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_CFG, 8856f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_DATA, 8956f6e31eSBin Meng MICROCHIP_PFSOC_IOSCB_CFG, 9056f6e31eSBin Meng MICROCHIP_PFSOC_DRAM, 9156f6e31eSBin Meng }; 9256f6e31eSBin Meng 938f2ac39dSBin Meng enum { 94*7124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 = 5, 95*7124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ1 = 6, 96*7124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ2 = 7, 97*7124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ3 = 8, 98*7124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ4 = 9, 99*7124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ5 = 10, 100*7124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ6 = 11, 101*7124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ7 = 12, 102898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, 1038f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0_IRQ = 90, 1048f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1_IRQ = 91, 1058f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2_IRQ = 92, 1068f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3_IRQ = 93, 1078f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4_IRQ = 94, 1088f2ac39dSBin Meng }; 1098f2ac39dSBin Meng 11056f6e31eSBin Meng #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 11156f6e31eSBin Meng #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 11256f6e31eSBin Meng 11356f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS" 11456f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 11556f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 11656f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 11756f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 11856f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 11956f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 12056f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 12156f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 12256f6e31eSBin Meng 12356f6e31eSBin Meng #endif /* HW_MICROCHIP_PFSOC_H */ 124