1*56f6e31eSBin Meng /* 2*56f6e31eSBin Meng * Microchip PolarFire SoC machine interface 3*56f6e31eSBin Meng * 4*56f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 5*56f6e31eSBin Meng * 6*56f6e31eSBin Meng * Author: 7*56f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 8*56f6e31eSBin Meng * 9*56f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 10*56f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 11*56f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 12*56f6e31eSBin Meng * 13*56f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 14*56f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15*56f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16*56f6e31eSBin Meng * more details. 17*56f6e31eSBin Meng * 18*56f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 19*56f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 20*56f6e31eSBin Meng */ 21*56f6e31eSBin Meng 22*56f6e31eSBin Meng #ifndef HW_MICROCHIP_PFSOC_H 23*56f6e31eSBin Meng #define HW_MICROCHIP_PFSOC_H 24*56f6e31eSBin Meng 25*56f6e31eSBin Meng typedef struct MicrochipPFSoCState { 26*56f6e31eSBin Meng /*< private >*/ 27*56f6e31eSBin Meng DeviceState parent_obj; 28*56f6e31eSBin Meng 29*56f6e31eSBin Meng /*< public >*/ 30*56f6e31eSBin Meng CPUClusterState e_cluster; 31*56f6e31eSBin Meng CPUClusterState u_cluster; 32*56f6e31eSBin Meng RISCVHartArrayState e_cpus; 33*56f6e31eSBin Meng RISCVHartArrayState u_cpus; 34*56f6e31eSBin Meng DeviceState *plic; 35*56f6e31eSBin Meng } MicrochipPFSoCState; 36*56f6e31eSBin Meng 37*56f6e31eSBin Meng #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" 38*56f6e31eSBin Meng #define MICROCHIP_PFSOC(obj) \ 39*56f6e31eSBin Meng OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) 40*56f6e31eSBin Meng 41*56f6e31eSBin Meng typedef struct MicrochipIcicleKitState { 42*56f6e31eSBin Meng /*< private >*/ 43*56f6e31eSBin Meng MachineState parent_obj; 44*56f6e31eSBin Meng 45*56f6e31eSBin Meng /*< public >*/ 46*56f6e31eSBin Meng MicrochipPFSoCState soc; 47*56f6e31eSBin Meng } MicrochipIcicleKitState; 48*56f6e31eSBin Meng 49*56f6e31eSBin Meng #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ 50*56f6e31eSBin Meng MACHINE_TYPE_NAME("microchip-icicle-kit") 51*56f6e31eSBin Meng #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ 52*56f6e31eSBin Meng OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ 53*56f6e31eSBin Meng TYPE_MICROCHIP_ICICLE_KIT_MACHINE) 54*56f6e31eSBin Meng 55*56f6e31eSBin Meng enum { 56*56f6e31eSBin Meng MICROCHIP_PFSOC_DEBUG, 57*56f6e31eSBin Meng MICROCHIP_PFSOC_E51_DTIM, 58*56f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT0, 59*56f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT1, 60*56f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT2, 61*56f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT3, 62*56f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT4, 63*56f6e31eSBin Meng MICROCHIP_PFSOC_CLINT, 64*56f6e31eSBin Meng MICROCHIP_PFSOC_L2CC, 65*56f6e31eSBin Meng MICROCHIP_PFSOC_L2LIM, 66*56f6e31eSBin Meng MICROCHIP_PFSOC_PLIC, 67*56f6e31eSBin Meng MICROCHIP_PFSOC_SYSREG, 68*56f6e31eSBin Meng MICROCHIP_PFSOC_MPUCFG, 69*56f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_CFG, 70*56f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_DATA, 71*56f6e31eSBin Meng MICROCHIP_PFSOC_IOSCB_CFG, 72*56f6e31eSBin Meng MICROCHIP_PFSOC_DRAM, 73*56f6e31eSBin Meng }; 74*56f6e31eSBin Meng 75*56f6e31eSBin Meng #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 76*56f6e31eSBin Meng #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 77*56f6e31eSBin Meng 78*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS" 79*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 80*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 81*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 82*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 83*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 84*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 85*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 86*56f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 87*56f6e31eSBin Meng 88*56f6e31eSBin Meng #endif /* HW_MICROCHIP_PFSOC_H */ 89