156f6e31eSBin Meng /* 256f6e31eSBin Meng * Microchip PolarFire SoC machine interface 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 1056f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 1156f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 1256f6e31eSBin Meng * 1356f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 1456f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1556f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1656f6e31eSBin Meng * more details. 1756f6e31eSBin Meng * 1856f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 1956f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 2056f6e31eSBin Meng */ 2156f6e31eSBin Meng 2256f6e31eSBin Meng #ifndef HW_MICROCHIP_PFSOC_H 2356f6e31eSBin Meng #define HW_MICROCHIP_PFSOC_H 2456f6e31eSBin Meng 258f2ac39dSBin Meng #include "hw/char/mchp_pfsoc_mmuart.h" 267124e27bSBin Meng #include "hw/dma/sifive_pdma.h" 27*47374b07SBin Meng #include "hw/net/cadence_gem.h" 28898dc008SBin Meng #include "hw/sd/cadence_sdhci.h" 298f2ac39dSBin Meng 3056f6e31eSBin Meng typedef struct MicrochipPFSoCState { 3156f6e31eSBin Meng /*< private >*/ 3256f6e31eSBin Meng DeviceState parent_obj; 3356f6e31eSBin Meng 3456f6e31eSBin Meng /*< public >*/ 3556f6e31eSBin Meng CPUClusterState e_cluster; 3656f6e31eSBin Meng CPUClusterState u_cluster; 3756f6e31eSBin Meng RISCVHartArrayState e_cpus; 3856f6e31eSBin Meng RISCVHartArrayState u_cpus; 3956f6e31eSBin Meng DeviceState *plic; 408f2ac39dSBin Meng MchpPfSoCMMUartState *serial0; 418f2ac39dSBin Meng MchpPfSoCMMUartState *serial1; 428f2ac39dSBin Meng MchpPfSoCMMUartState *serial2; 438f2ac39dSBin Meng MchpPfSoCMMUartState *serial3; 448f2ac39dSBin Meng MchpPfSoCMMUartState *serial4; 457124e27bSBin Meng SiFivePDMAState dma; 46*47374b07SBin Meng CadenceGEMState gem0; 47*47374b07SBin Meng CadenceGEMState gem1; 48898dc008SBin Meng CadenceSDHCIState sdhci; 4956f6e31eSBin Meng } MicrochipPFSoCState; 5056f6e31eSBin Meng 5156f6e31eSBin Meng #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" 5256f6e31eSBin Meng #define MICROCHIP_PFSOC(obj) \ 5356f6e31eSBin Meng OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) 5456f6e31eSBin Meng 5556f6e31eSBin Meng typedef struct MicrochipIcicleKitState { 5656f6e31eSBin Meng /*< private >*/ 5756f6e31eSBin Meng MachineState parent_obj; 5856f6e31eSBin Meng 5956f6e31eSBin Meng /*< public >*/ 6056f6e31eSBin Meng MicrochipPFSoCState soc; 6156f6e31eSBin Meng } MicrochipIcicleKitState; 6256f6e31eSBin Meng 6356f6e31eSBin Meng #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ 6456f6e31eSBin Meng MACHINE_TYPE_NAME("microchip-icicle-kit") 6556f6e31eSBin Meng #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ 6656f6e31eSBin Meng OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ 6756f6e31eSBin Meng TYPE_MICROCHIP_ICICLE_KIT_MACHINE) 6856f6e31eSBin Meng 6956f6e31eSBin Meng enum { 7056f6e31eSBin Meng MICROCHIP_PFSOC_DEBUG, 7156f6e31eSBin Meng MICROCHIP_PFSOC_E51_DTIM, 7256f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT0, 7356f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT1, 7456f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT2, 7556f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT3, 7656f6e31eSBin Meng MICROCHIP_PFSOC_BUSERR_UNIT4, 7756f6e31eSBin Meng MICROCHIP_PFSOC_CLINT, 7856f6e31eSBin Meng MICROCHIP_PFSOC_L2CC, 797124e27bSBin Meng MICROCHIP_PFSOC_DMA, 8056f6e31eSBin Meng MICROCHIP_PFSOC_L2LIM, 8156f6e31eSBin Meng MICROCHIP_PFSOC_PLIC, 828f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0, 8356f6e31eSBin Meng MICROCHIP_PFSOC_SYSREG, 8456f6e31eSBin Meng MICROCHIP_PFSOC_MPUCFG, 85898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD, 868f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1, 878f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2, 888f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3, 898f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4, 90*47374b07SBin Meng MICROCHIP_PFSOC_GEM0, 91*47374b07SBin Meng MICROCHIP_PFSOC_GEM1, 9256f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_CFG, 9356f6e31eSBin Meng MICROCHIP_PFSOC_ENVM_DATA, 9456f6e31eSBin Meng MICROCHIP_PFSOC_IOSCB_CFG, 9556f6e31eSBin Meng MICROCHIP_PFSOC_DRAM, 9656f6e31eSBin Meng }; 9756f6e31eSBin Meng 988f2ac39dSBin Meng enum { 997124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 = 5, 1007124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ1 = 6, 1017124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ2 = 7, 1027124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ3 = 8, 1037124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ4 = 9, 1047124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ5 = 10, 1057124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ6 = 11, 1067124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ7 = 12, 107*47374b07SBin Meng MICROCHIP_PFSOC_GEM0_IRQ = 64, 108*47374b07SBin Meng MICROCHIP_PFSOC_GEM1_IRQ = 70, 109898dc008SBin Meng MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, 1108f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART0_IRQ = 90, 1118f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART1_IRQ = 91, 1128f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART2_IRQ = 92, 1138f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART3_IRQ = 93, 1148f2ac39dSBin Meng MICROCHIP_PFSOC_MMUART4_IRQ = 94, 1158f2ac39dSBin Meng }; 1168f2ac39dSBin Meng 11756f6e31eSBin Meng #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 11856f6e31eSBin Meng #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 11956f6e31eSBin Meng 12056f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS" 12156f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 12256f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 12356f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 12456f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 12556f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 12656f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 12756f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 12856f6e31eSBin Meng #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 12956f6e31eSBin Meng 13056f6e31eSBin Meng #endif /* HW_MICROCHIP_PFSOC_H */ 131