xref: /openbmc/qemu/include/hw/riscv/boot.h (revision 5b6c291b)
1 /*
2  * QEMU RISC-V Boot Helper
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef RISCV_BOOT_H
21 #define RISCV_BOOT_H
22 
23 #include "exec/cpu-defs.h"
24 #include "hw/loader.h"
25 
26 bool riscv_is_32_bit(MachineState *machine);
27 
28 target_ulong riscv_calc_kernel_start_addr(MachineState *machine,
29                                           target_ulong firmware_end_addr);
30 target_ulong riscv_find_and_load_firmware(MachineState *machine,
31                                           const char *default_machine_firmware,
32                                           hwaddr firmware_load_addr,
33                                           symbol_fn_t sym_cb);
34 char *riscv_find_firmware(const char *firmware_filename);
35 target_ulong riscv_load_firmware(const char *firmware_filename,
36                                  hwaddr firmware_load_addr,
37                                  symbol_fn_t sym_cb);
38 target_ulong riscv_load_kernel(const char *kernel_filename,
39                                target_ulong firmware_end_addr,
40                                symbol_fn_t sym_cb);
41 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
42                          uint64_t kernel_entry, hwaddr *start);
43 uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
44 void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr,
45                                hwaddr rom_base, hwaddr rom_size,
46                                uint64_t kernel_entry,
47                                uint32_t fdt_load_addr, void *fdt);
48 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
49                                   hwaddr rom_size,
50                                   uint32_t reset_vec_size,
51                                   uint64_t kernel_entry);
52 
53 #endif /* RISCV_BOOT_H */
54