1 /* 2 * QEMU PowerPC XIVE internal structure definitions 3 * 4 * 5 * The XIVE structures are accessed by the HW and their format is 6 * architected to be big-endian. Some macros are provided to ease 7 * access to the different fields. 8 * 9 * 10 * Copyright (c) 2016-2018, IBM Corporation. 11 * 12 * This code is licensed under the GPL version 2 or later. See the 13 * COPYING file in the top-level directory. 14 */ 15 16 #ifndef PPC_XIVE_REGS_H 17 #define PPC_XIVE_REGS_H 18 19 #include "qemu/bswap.h" 20 #include "qemu/host-utils.h" 21 22 /* 23 * Interrupt source number encoding on PowerBUS 24 */ 25 /* 26 * Trigger data definition 27 * 28 * The trigger definition is used for triggers both for HW source 29 * interrupts (PHB, PSI), as well as for rerouting interrupts between 30 * Interrupt Controller. 31 * 32 * HW source controllers set bit0 of word0 to ‘0’ as they provide EAS 33 * information (EAS block + EAS index) in the 8 byte data and not END 34 * information, which is use for rerouting interrupts. 35 * 36 * bit1 of word0 to ‘1’ signals that the state bit check has been 37 * performed. 38 */ 39 #define XIVE_TRIGGER_END PPC_BIT(0) 40 #define XIVE_TRIGGER_PQ PPC_BIT(1) 41 42 /* 43 * QEMU macros to manipulate the trigger payload in native endian 44 */ 45 #define XIVE_EAS_BLOCK(n) (((n) >> 28) & 0xf) 46 #define XIVE_EAS_INDEX(n) ((n) & 0x0fffffff) 47 #define XIVE_EAS(blk, idx) ((uint32_t)(blk) << 28 | (idx)) 48 49 #define TM_SHIFT 16 50 51 /* 52 * TIMA addresses are 12-bits (4k page). 53 * The MSB indicates a special op with side effect, which can be 54 * refined with bit 10 (see below). 55 * The registers, logically grouped in 4 rings (a quad-word each), are 56 * defined on the 6 LSBs (offset below 0x40) 57 * In between, we can add a cache line index from 0...3 (ie, 0, 0x80, 58 * 0x100, 0x180) to select a specific snooper. Those 'snoop port 59 * address' bits should be dropped when processing the operations as 60 * they are all equivalent. 61 */ 62 #define TM_ADDRESS_MASK 0xC3F 63 #define TM_SPECIAL_OP 0x800 64 #define TM_RING_OFFSET 0x30 65 #define TM_REG_OFFSET 0x3F 66 67 /* TM register offsets */ 68 #define TM_QW0_USER 0x000 /* All rings */ 69 #define TM_QW1_OS 0x010 /* Ring 0..2 */ 70 #define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ 71 #define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ 72 73 /* Byte offsets inside a QW QW0 QW1 QW2 QW3 */ 74 #define TM_NSR 0x0 /* + + - + */ 75 #define TM_CPPR 0x1 /* - + - + */ 76 #define TM_IPB 0x2 /* - + + + */ 77 #define TM_LSMFB 0x3 /* - + + + */ 78 #define TM_ACK_CNT 0x4 /* - + - - */ 79 #define TM_INC 0x5 /* - + - + */ 80 #define TM_LGS 0x5 /* + + + + */ /* Rename P10 */ 81 #define TM_AGE 0x6 /* - + - + */ 82 #define TM_T 0x6 /* - + - + */ /* Rename P10 */ 83 #define TM_PIPR 0x7 /* - + - + */ 84 #define TM_OGEN 0xF /* - + - - */ /* P10 only */ 85 86 #define TM_WORD0 0x0 87 #define TM_WORD1 0x4 88 89 /* 90 * QW word 2 contains the valid bit at the top and other fields 91 * depending on the QW. 92 */ 93 #define TM_WORD2 0x8 94 #define TM_QW0W2_VU PPC_BIT32(0) 95 #define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */ 96 #define TM_QW1W2_VO PPC_BIT32(0) 97 #define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31) 98 #define TM_QW2W2_VP PPC_BIT32(0) 99 #define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31) 100 #define TM_QW3W2_VT PPC_BIT32(0) 101 #define TM_QW3W2_LP PPC_BIT32(6) 102 #define TM_QW3W2_LE PPC_BIT32(7) 103 #define TM_QW3W2_T PPC_BIT32(31) 104 #define TM_QW3B8_VT PPC_BIT8(0) 105 106 /* 107 * In addition to normal loads to "peek" and writes (only when invalid) 108 * using 4 and 8 bytes accesses, the above registers support these 109 * "special" byte operations: 110 * 111 * - Byte load from QW0[NSR] - User level NSR (EBB) 112 * - Byte store to QW0[NSR] - User level NSR (EBB) 113 * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access 114 * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0 115 * otherwise VT||0000000 116 * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present) 117 * 118 * Then we have all these "special" CI ops at these offset that trigger 119 * all sorts of side effects: 120 */ 121 #define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg */ 122 #define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ 123 #define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */ 124 #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */ 125 /* context */ 126 #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ 127 #define TM_SPC_PULL_OS_CTX_G2 0x810 /* Load32/Load64 Pull/Invalidate OS */ 128 /* context to reg */ 129 #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */ 130 /* context to reg */ 131 #define TM_SPC_PULL_POOL_CTX_G2 0x820 /* Load32/Load64 Pull/Invalidate Pool */ 132 /* context to reg */ 133 #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */ 134 /* context to reg */ 135 #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ 136 #define TM_SPC_PULL_PHYS_CTX_G2 0x830 /* Load32 Pull phys ctx to reg */ 137 #define TM_SPC_PULL_PHYS_CTX 0x838 /* Load8 Pull phys ctx to reg */ 138 #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ 139 /* line */ 140 #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ 141 #define TM_SPC_PULL_OS_CTX_OL 0xc18 /* Pull/Invalidate OS context to */ 142 /* odd Thread reporting line */ 143 #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even */ 144 /* line */ 145 #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ 146 #define TM_SPC_PULL_PHYS_CTX_OL 0xc38 /* Pull phys ctx to odd cache line */ 147 /* XXX more... */ 148 149 /* NSR fields for the various QW ack types */ 150 #define TM_QW0_NSR_EB PPC_BIT8(0) 151 #define TM_QW1_NSR_EO PPC_BIT8(0) 152 #define TM_QW3_NSR_HE PPC_BITMASK8(0, 1) 153 #define TM_QW3_NSR_HE_NONE 0 154 #define TM_QW3_NSR_HE_POOL 1 155 #define TM_QW3_NSR_HE_PHYS 2 156 #define TM_QW3_NSR_HE_LSI 3 157 #define TM_QW3_NSR_I PPC_BIT8(2) 158 #define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7) 159 160 /* 161 * EAS (Event Assignment Structure) 162 * 163 * One per interrupt source. Targets an interrupt to a given Event 164 * Notification Descriptor (END) and provides the corresponding 165 * logical interrupt number (END data) 166 */ 167 typedef struct XiveEAS { 168 /* 169 * Use a single 64-bit definition to make it easier to perform 170 * atomic updates 171 */ 172 uint64_t w; 173 #define EAS_VALID PPC_BIT(0) 174 #define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */ 175 #define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */ 176 #define EAS_MASKED PPC_BIT(32) /* Masked */ 177 #define EAS_END_DATA PPC_BITMASK(33, 63) /* Data written to the END */ 178 } XiveEAS; 179 180 #define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID) 181 #define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED) 182 183 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf); 184 185 static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word) 186 { 187 return (be64_to_cpu(word) & mask) >> ctz64(mask); 188 } 189 190 static inline uint64_t xive_set_field64(uint64_t mask, uint64_t word, 191 uint64_t value) 192 { 193 uint64_t tmp = 194 (be64_to_cpu(word) & ~mask) | ((value << ctz64(mask)) & mask); 195 return cpu_to_be64(tmp); 196 } 197 198 static inline uint32_t xive_get_field32(uint32_t mask, uint32_t word) 199 { 200 return (be32_to_cpu(word) & mask) >> ctz32(mask); 201 } 202 203 static inline uint32_t xive_set_field32(uint32_t mask, uint32_t word, 204 uint32_t value) 205 { 206 uint32_t tmp = 207 (be32_to_cpu(word) & ~mask) | ((value << ctz32(mask)) & mask); 208 return cpu_to_be32(tmp); 209 } 210 211 /* Event Notification Descriptor (END) */ 212 typedef struct XiveEND { 213 uint32_t w0; 214 #define END_W0_VALID PPC_BIT32(0) /* "v" bit */ 215 #define END_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */ 216 #define END_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */ 217 #define END_W0_BACKLOG PPC_BIT32(3) /* "b" bit */ 218 #define END_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */ 219 #define END_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */ 220 #define END_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */ 221 #define END_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */ 222 #define END_W0_QSIZE PPC_BITMASK32(12, 15) 223 #define END_W0_SW0 PPC_BIT32(16) 224 #define END_W0_FIRMWARE END_W0_SW0 /* Owned by FW */ 225 #define END_QSIZE_4K 0 226 #define END_QSIZE_64K 4 227 #define END_W0_HWDEP PPC_BITMASK32(24, 31) 228 uint32_t w1; 229 #define END_W1_ESn PPC_BITMASK32(0, 1) 230 #define END_W1_ESn_P PPC_BIT32(0) 231 #define END_W1_ESn_Q PPC_BIT32(1) 232 #define END_W1_ESe PPC_BITMASK32(2, 3) 233 #define END_W1_ESe_P PPC_BIT32(2) 234 #define END_W1_ESe_Q PPC_BIT32(3) 235 #define END_W1_GENERATION PPC_BIT32(9) 236 #define END_W1_PAGE_OFF PPC_BITMASK32(10, 31) 237 uint32_t w2; 238 #define END_W2_MIGRATION_REG PPC_BITMASK32(0, 3) 239 #define END_W2_OP_DESC_HI PPC_BITMASK32(4, 31) 240 uint32_t w3; 241 #define END_W3_OP_DESC_LO PPC_BITMASK32(0, 31) 242 uint32_t w4; 243 #define END_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) 244 #define END_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) 245 uint32_t w5; 246 #define END_W5_ESC_END_DATA PPC_BITMASK32(1, 31) 247 uint32_t w6; 248 #define END_W6_FORMAT_BIT PPC_BIT32(8) 249 #define END_W6_NVT_BLOCK PPC_BITMASK32(9, 12) 250 #define END_W6_NVT_INDEX PPC_BITMASK32(13, 31) 251 uint32_t w7; 252 #define END_W7_F0_IGNORE PPC_BIT32(0) 253 #define END_W7_F0_BLK_GROUPING PPC_BIT32(1) 254 #define END_W7_F0_PRIORITY PPC_BITMASK32(8, 15) 255 #define END_W7_F1_WAKEZ PPC_BIT32(0) 256 #define END_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1, 31) 257 } XiveEND; 258 259 #define xive_end_is_valid(end) (be32_to_cpu((end)->w0) & END_W0_VALID) 260 #define xive_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END_W0_ENQUEUE) 261 #define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY) 262 #define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG) 263 #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL) 264 #define xive_end_is_uncond_escalation(end) \ 265 (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE) 266 #define xive_end_is_silent_escalation(end) \ 267 (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE) 268 #define xive_end_is_firmware(end) \ 269 (be32_to_cpu((end)->w0) & END_W0_FIRMWARE) 270 271 static inline uint64_t xive_end_qaddr(XiveEND *end) 272 { 273 return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 | 274 be32_to_cpu(end->w3); 275 } 276 277 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf); 278 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf); 279 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf); 280 281 /* Notification Virtual Target (NVT) */ 282 typedef struct XiveNVT { 283 uint32_t w0; 284 #define NVT_W0_VALID PPC_BIT32(0) 285 uint32_t w1; 286 #define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3) 287 #define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31) 288 uint32_t w2; 289 uint32_t w3; 290 uint32_t w4; 291 #define NVT_W4_IPB PPC_BITMASK32(16, 23) 292 uint32_t w5; 293 uint32_t w6; 294 uint32_t w7; 295 uint32_t w8; 296 #define NVT_W8_GRP_VALID PPC_BIT32(0) 297 uint32_t w9; 298 uint32_t wa; 299 uint32_t wb; 300 uint32_t wc; 301 uint32_t wd; 302 uint32_t we; 303 uint32_t wf; 304 } XiveNVT; 305 306 #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID) 307 308 /* 309 * The VP number space in a block is defined by the END_W6_NVT_INDEX 310 * field of the XIVE END 311 */ 312 #define XIVE_NVT_SHIFT 19 313 #define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT) 314 315 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) 316 { 317 return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx; 318 } 319 320 static inline uint32_t xive_nvt_idx(uint32_t cam_line) 321 { 322 return cam_line & ((1 << XIVE_NVT_SHIFT) - 1); 323 } 324 325 static inline uint32_t xive_nvt_blk(uint32_t cam_line) 326 { 327 return (cam_line >> XIVE_NVT_SHIFT) & 0xf; 328 } 329 330 #endif /* PPC_XIVE_REGS_H */ 331