1 /* 2 * QEMU PowerPC XIVE internal structure definitions 3 * 4 * 5 * The XIVE structures are accessed by the HW and their format is 6 * architected to be big-endian. Some macros are provided to ease 7 * access to the different fields. 8 * 9 * 10 * Copyright (c) 2016-2018, IBM Corporation. 11 * 12 * This code is licensed under the GPL version 2 or later. See the 13 * COPYING file in the top-level directory. 14 */ 15 16 #ifndef PPC_XIVE_REGS_H 17 #define PPC_XIVE_REGS_H 18 19 #include "qemu/bswap.h" 20 #include "qemu/host-utils.h" 21 22 /* 23 * Interrupt source number encoding on PowerBUS 24 */ 25 /* 26 * Trigger data definition 27 * 28 * The trigger definition is used for triggers both for HW source 29 * interrupts (PHB, PSI), as well as for rerouting interrupts between 30 * Interrupt Controller. 31 * 32 * HW source controllers set bit0 of word0 to ‘0’ as they provide EAS 33 * information (EAS block + EAS index) in the 8 byte data and not END 34 * information, which is use for rerouting interrupts. 35 * 36 * bit1 of word0 to ‘1’ signals that the state bit check has been 37 * performed. 38 */ 39 #define XIVE_TRIGGER_END PPC_BIT(0) 40 #define XIVE_TRIGGER_PQ PPC_BIT(1) 41 42 /* 43 * QEMU macros to manipulate the trigger payload in native endian 44 */ 45 #define XIVE_EAS_BLOCK(n) (((n) >> 28) & 0xf) 46 #define XIVE_EAS_INDEX(n) ((n) & 0x0fffffff) 47 #define XIVE_EAS(blk, idx) ((uint32_t)(blk) << 28 | (idx)) 48 49 #define TM_SHIFT 16 50 51 /* 52 * TIMA addresses are 12-bits (4k page). 53 * The MSB indicates a special op with side effect, which can be 54 * refined with bit 10 (see below). 55 * The registers, logically grouped in 4 rings (a quad-word each), are 56 * defined on the 6 LSBs (offset below 0x40) 57 * In between, we can add a cache line index from 0...3 (ie, 0, 0x80, 58 * 0x100, 0x180) to select a specific snooper. Those 'snoop port 59 * address' bits should be dropped when processing the operations as 60 * they are all equivalent. 61 */ 62 #define TM_ADDRESS_MASK 0xC3F 63 #define TM_SPECIAL_OP 0x800 64 #define TM_RING_OFFSET 0x30 65 #define TM_REG_OFFSET 0x3F 66 67 /* TM register offsets */ 68 #define TM_QW0_USER 0x000 /* All rings */ 69 #define TM_QW1_OS 0x010 /* Ring 0..2 */ 70 #define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ 71 #define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ 72 73 /* Byte offsets inside a QW QW0 QW1 QW2 QW3 */ 74 #define TM_NSR 0x0 /* + + - + */ 75 #define TM_CPPR 0x1 /* - + - + */ 76 #define TM_IPB 0x2 /* - + + + */ 77 #define TM_LSMFB 0x3 /* - + + + */ 78 #define TM_ACK_CNT 0x4 /* - + - - */ 79 #define TM_INC 0x5 /* - + - + */ 80 #define TM_AGE 0x6 /* - + - + */ 81 #define TM_PIPR 0x7 /* - + - + */ 82 83 #define TM_WORD0 0x0 84 #define TM_WORD1 0x4 85 86 /* 87 * QW word 2 contains the valid bit at the top and other fields 88 * depending on the QW. 89 */ 90 #define TM_WORD2 0x8 91 #define TM_QW0W2_VU PPC_BIT32(0) 92 #define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */ 93 #define TM_QW1W2_VO PPC_BIT32(0) 94 #define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31) 95 #define TM_QW2W2_VP PPC_BIT32(0) 96 #define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31) 97 #define TM_QW3W2_VT PPC_BIT32(0) 98 #define TM_QW3W2_LP PPC_BIT32(6) 99 #define TM_QW3W2_LE PPC_BIT32(7) 100 #define TM_QW3W2_T PPC_BIT32(31) 101 102 /* 103 * In addition to normal loads to "peek" and writes (only when invalid) 104 * using 4 and 8 bytes accesses, the above registers support these 105 * "special" byte operations: 106 * 107 * - Byte load from QW0[NSR] - User level NSR (EBB) 108 * - Byte store to QW0[NSR] - User level NSR (EBB) 109 * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access 110 * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0 111 * otherwise VT||0000000 112 * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present) 113 * 114 * Then we have all these "special" CI ops at these offset that trigger 115 * all sorts of side effects: 116 */ 117 #define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ 118 #define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ 119 #define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */ 120 #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user 121 * context */ 122 #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ 123 #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS 124 * context to reg */ 125 #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool 126 * context to reg*/ 127 #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ 128 #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd 129 * line */ 130 #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ 131 #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even 132 * line */ 133 #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ 134 /* XXX more... */ 135 136 /* NSR fields for the various QW ack types */ 137 #define TM_QW0_NSR_EB PPC_BIT8(0) 138 #define TM_QW1_NSR_EO PPC_BIT8(0) 139 #define TM_QW3_NSR_HE PPC_BITMASK8(0, 1) 140 #define TM_QW3_NSR_HE_NONE 0 141 #define TM_QW3_NSR_HE_POOL 1 142 #define TM_QW3_NSR_HE_PHYS 2 143 #define TM_QW3_NSR_HE_LSI 3 144 #define TM_QW3_NSR_I PPC_BIT8(2) 145 #define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7) 146 147 /* 148 * EAS (Event Assignment Structure) 149 * 150 * One per interrupt source. Targets an interrupt to a given Event 151 * Notification Descriptor (END) and provides the corresponding 152 * logical interrupt number (END data) 153 */ 154 typedef struct XiveEAS { 155 /* 156 * Use a single 64-bit definition to make it easier to perform 157 * atomic updates 158 */ 159 uint64_t w; 160 #define EAS_VALID PPC_BIT(0) 161 #define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */ 162 #define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */ 163 #define EAS_MASKED PPC_BIT(32) /* Masked */ 164 #define EAS_END_DATA PPC_BITMASK(33, 63) /* Data written to the END */ 165 } XiveEAS; 166 167 #define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID) 168 #define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED) 169 170 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf); 171 172 static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word) 173 { 174 return (be64_to_cpu(word) & mask) >> ctz64(mask); 175 } 176 177 static inline uint64_t xive_set_field64(uint64_t mask, uint64_t word, 178 uint64_t value) 179 { 180 uint64_t tmp = 181 (be64_to_cpu(word) & ~mask) | ((value << ctz64(mask)) & mask); 182 return cpu_to_be64(tmp); 183 } 184 185 static inline uint32_t xive_get_field32(uint32_t mask, uint32_t word) 186 { 187 return (be32_to_cpu(word) & mask) >> ctz32(mask); 188 } 189 190 static inline uint32_t xive_set_field32(uint32_t mask, uint32_t word, 191 uint32_t value) 192 { 193 uint32_t tmp = 194 (be32_to_cpu(word) & ~mask) | ((value << ctz32(mask)) & mask); 195 return cpu_to_be32(tmp); 196 } 197 198 /* Event Notification Descriptor (END) */ 199 typedef struct XiveEND { 200 uint32_t w0; 201 #define END_W0_VALID PPC_BIT32(0) /* "v" bit */ 202 #define END_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */ 203 #define END_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */ 204 #define END_W0_BACKLOG PPC_BIT32(3) /* "b" bit */ 205 #define END_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */ 206 #define END_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */ 207 #define END_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */ 208 #define END_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */ 209 #define END_W0_QSIZE PPC_BITMASK32(12, 15) 210 #define END_W0_SW0 PPC_BIT32(16) 211 #define END_W0_FIRMWARE END_W0_SW0 /* Owned by FW */ 212 #define END_QSIZE_4K 0 213 #define END_QSIZE_64K 4 214 #define END_W0_HWDEP PPC_BITMASK32(24, 31) 215 uint32_t w1; 216 #define END_W1_ESn PPC_BITMASK32(0, 1) 217 #define END_W1_ESn_P PPC_BIT32(0) 218 #define END_W1_ESn_Q PPC_BIT32(1) 219 #define END_W1_ESe PPC_BITMASK32(2, 3) 220 #define END_W1_ESe_P PPC_BIT32(2) 221 #define END_W1_ESe_Q PPC_BIT32(3) 222 #define END_W1_GENERATION PPC_BIT32(9) 223 #define END_W1_PAGE_OFF PPC_BITMASK32(10, 31) 224 uint32_t w2; 225 #define END_W2_MIGRATION_REG PPC_BITMASK32(0, 3) 226 #define END_W2_OP_DESC_HI PPC_BITMASK32(4, 31) 227 uint32_t w3; 228 #define END_W3_OP_DESC_LO PPC_BITMASK32(0, 31) 229 uint32_t w4; 230 #define END_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) 231 #define END_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) 232 uint32_t w5; 233 #define END_W5_ESC_END_DATA PPC_BITMASK32(1, 31) 234 uint32_t w6; 235 #define END_W6_FORMAT_BIT PPC_BIT32(8) 236 #define END_W6_NVT_BLOCK PPC_BITMASK32(9, 12) 237 #define END_W6_NVT_INDEX PPC_BITMASK32(13, 31) 238 uint32_t w7; 239 #define END_W7_F0_IGNORE PPC_BIT32(0) 240 #define END_W7_F0_BLK_GROUPING PPC_BIT32(1) 241 #define END_W7_F0_PRIORITY PPC_BITMASK32(8, 15) 242 #define END_W7_F1_WAKEZ PPC_BIT32(0) 243 #define END_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1, 31) 244 } XiveEND; 245 246 #define xive_end_is_valid(end) (be32_to_cpu((end)->w0) & END_W0_VALID) 247 #define xive_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END_W0_ENQUEUE) 248 #define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY) 249 #define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG) 250 #define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL) 251 #define xive_end_is_uncond_escalation(end) \ 252 (be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE) 253 #define xive_end_is_silent_escalation(end) \ 254 (be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE) 255 #define xive_end_is_firmware(end) \ 256 (be32_to_cpu((end)->w0) & END_W0_FIRMWARE) 257 258 static inline uint64_t xive_end_qaddr(XiveEND *end) 259 { 260 return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 | 261 be32_to_cpu(end->w3); 262 } 263 264 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf); 265 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf); 266 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf); 267 268 /* Notification Virtual Target (NVT) */ 269 typedef struct XiveNVT { 270 uint32_t w0; 271 #define NVT_W0_VALID PPC_BIT32(0) 272 uint32_t w1; 273 #define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3) 274 #define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31) 275 uint32_t w2; 276 uint32_t w3; 277 uint32_t w4; 278 #define NVT_W4_IPB PPC_BITMASK32(16, 23) 279 uint32_t w5; 280 uint32_t w6; 281 uint32_t w7; 282 uint32_t w8; 283 #define NVT_W8_GRP_VALID PPC_BIT32(0) 284 uint32_t w9; 285 uint32_t wa; 286 uint32_t wb; 287 uint32_t wc; 288 uint32_t wd; 289 uint32_t we; 290 uint32_t wf; 291 } XiveNVT; 292 293 #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID) 294 295 /* 296 * The VP number space in a block is defined by the END_W6_NVT_INDEX 297 * field of the XIVE END 298 */ 299 #define XIVE_NVT_SHIFT 19 300 #define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT) 301 302 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) 303 { 304 return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx; 305 } 306 307 static inline uint32_t xive_nvt_idx(uint32_t cam_line) 308 { 309 return cam_line & ((1 << XIVE_NVT_SHIFT) - 1); 310 } 311 312 static inline uint32_t xive_nvt_blk(uint32_t cam_line) 313 { 314 return (cam_line >> XIVE_NVT_SHIFT) & 0xf; 315 } 316 317 #endif /* PPC_XIVE_REGS_H */ 318