1 /* 2 * QEMU PowerPC XIVE2 internal structure definitions (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PPC_XIVE2_REGS_H 11 #define PPC_XIVE2_REGS_H 12 13 /* 14 * Thread Interrupt Management Area (TIMA) 15 * 16 * In Gen1 mode (P9 compat mode) word 2 is the same. However in Gen2 17 * mode (P10), the CAM line is slightly different as the VP space was 18 * increased. 19 */ 20 #define TM2_QW0W2_VU PPC_BIT32(0) 21 #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31) 22 #define TM2_QW1W2_VO PPC_BIT32(0) 23 #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31) 24 #define TM2_QW2W2_VP PPC_BIT32(0) 25 #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31) 26 #define TM2_QW3W2_VT PPC_BIT32(0) 27 #define TM2_QW3W2_LP PPC_BIT32(6) 28 #define TM2_QW3W2_LE PPC_BIT32(7) 29 30 /* 31 * Event Assignment Structure (EAS) 32 */ 33 34 typedef struct Xive2Eas { 35 uint64_t w; 36 #define EAS2_VALID PPC_BIT(0) 37 #define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */ 38 #define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */ 39 #define EAS2_MASKED PPC_BIT(32) /* Masked */ 40 #define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */ 41 } Xive2Eas; 42 43 #define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID) 44 #define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED) 45 46 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon); 47 48 /* 49 * Event Notifification Descriptor (END) 50 */ 51 52 typedef struct Xive2End { 53 uint32_t w0; 54 #define END2_W0_VALID PPC_BIT32(0) /* "v" bit */ 55 #define END2_W0_ENQUEUE PPC_BIT32(5) /* "q" bit */ 56 #define END2_W0_UCOND_NOTIFY PPC_BIT32(6) /* "n" bit */ 57 #define END2_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */ 58 #define END2_W0_BACKLOG PPC_BIT32(8) /* "b" bit */ 59 #define END2_W0_PRECL_ESC_CTL PPC_BIT32(9) /* "p" bit */ 60 #define END2_W0_UNCOND_ESCALATE PPC_BIT32(10) /* "u" bit */ 61 #define END2_W0_ESCALATE_CTL PPC_BIT32(11) /* "e" bit */ 62 #define END2_W0_ADAPTIVE_ESC PPC_BIT32(12) /* "a" bit */ 63 #define END2_W0_ESCALATE_END PPC_BIT32(13) /* "N" bit */ 64 #define END2_W0_FIRMWARE1 PPC_BIT32(16) /* Owned by FW */ 65 #define END2_W0_FIRMWARE2 PPC_BIT32(17) /* Owned by FW */ 66 #define END2_W0_AEC_SIZE PPC_BITMASK32(18, 19) 67 #define END2_W0_AEG_SIZE PPC_BITMASK32(20, 23) 68 #define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */ 69 uint32_t w1; 70 #define END2_W1_ESn PPC_BITMASK32(0, 1) 71 #define END2_W1_ESn_P PPC_BIT32(0) 72 #define END2_W1_ESn_Q PPC_BIT32(1) 73 #define END2_W1_ESe PPC_BITMASK32(2, 3) 74 #define END2_W1_ESe_P PPC_BIT32(2) 75 #define END2_W1_ESe_Q PPC_BIT32(3) 76 #define END2_W1_GEN_FLIPPED PPC_BIT32(8) 77 #define END2_W1_GENERATION PPC_BIT32(9) 78 #define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31) 79 uint32_t w2; 80 #define END2_W2_RESERVED PPC_BITMASK32(4, 7) 81 #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31) 82 uint32_t w3; 83 #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24) 84 #define END2_W3_QSIZE PPC_BITMASK32(28, 31) 85 uint32_t w4; 86 #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7) 87 #define END2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) 88 #define END2_W4_ESB_BLOCK PPC_BITMASK32(0, 3) 89 #define END2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) 90 uint32_t w5; 91 #define END2_W5_ESC_END_DATA PPC_BITMASK32(1, 31) 92 uint32_t w6; 93 #define END2_W6_FORMAT_BIT PPC_BIT32(0) 94 #define END2_W6_IGNORE PPC_BIT32(1) 95 #define END2_W6_VP_BLOCK PPC_BITMASK32(4, 7) 96 #define END2_W6_VP_OFFSET PPC_BITMASK32(8, 31) 97 #define END2_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13, 31) 98 uint32_t w7; 99 #define END2_W7_TOPO PPC_BITMASK32(0, 3) /* Owned by HW */ 100 #define END2_W7_F0_PRIORITY PPC_BITMASK32(8, 15) 101 #define END2_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4, 31) 102 } Xive2End; 103 104 #define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID) 105 #define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE) 106 #define xive2_end_is_notify(end) \ 107 (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY) 108 #define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG) 109 #define xive2_end_is_escalate(end) \ 110 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL) 111 #define xive2_end_is_uncond_escalation(end) \ 112 (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE) 113 #define xive2_end_is_silent_escalation(end) \ 114 (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE) 115 #define xive2_end_is_escalate_end(end) \ 116 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END) 117 #define xive2_end_is_firmware1(end) \ 118 (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1) 119 #define xive2_end_is_firmware2(end) \ 120 (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2) 121 122 static inline uint64_t xive2_end_qaddr(Xive2End *end) 123 { 124 return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 | 125 (be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO); 126 } 127 128 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon); 129 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, 130 Monitor *mon); 131 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 132 Monitor *mon); 133 134 /* 135 * Notification Virtual Processor (NVP) 136 */ 137 typedef struct Xive2Nvp { 138 uint32_t w0; 139 #define NVP2_W0_VALID PPC_BIT32(0) 140 #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */ 141 uint32_t w1; 142 uint32_t w2; 143 #define NVP2_W2_IPB PPC_BITMASK32(8, 15) 144 uint32_t w3; 145 uint32_t w4; 146 #define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */ 147 #define NVP2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */ 148 #define NVP2_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */ 149 #define NVP2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */ 150 uint32_t w5; 151 #define NVP2_W5_PSIZE PPC_BITMASK32(0, 1) 152 #define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7) 153 #define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31) 154 uint32_t w6; 155 uint32_t w7; 156 } Xive2Nvp; 157 158 #define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID) 159 160 /* 161 * The VP number space in a block is defined by the END2_W6_VP_OFFSET 162 * field of the XIVE END. When running in Gen1 mode (P9 compat mode), 163 * the VP space is reduced to (1 << 19) VPs per block 164 */ 165 #define XIVE2_NVP_SHIFT 24 166 #define XIVE2_NVP_COUNT (1 << XIVE2_NVP_SHIFT) 167 168 static inline uint32_t xive2_nvp_cam_line(uint8_t nvp_blk, uint32_t nvp_idx) 169 { 170 return (nvp_blk << XIVE2_NVP_SHIFT) | nvp_idx; 171 } 172 173 static inline uint32_t xive2_nvp_idx(uint32_t cam_line) 174 { 175 return cam_line & ((1 << XIVE2_NVP_SHIFT) - 1); 176 } 177 178 static inline uint32_t xive2_nvp_blk(uint32_t cam_line) 179 { 180 return (cam_line >> XIVE2_NVP_SHIFT) & 0xf; 181 } 182 183 /* 184 * Notification Virtual Group or Crowd (NVG/NVC) 185 */ 186 typedef struct Xive2Nvgc { 187 uint32_t w0; 188 #define NVGC2_W0_VALID PPC_BIT32(0) 189 uint32_t w1; 190 uint32_t w2; 191 uint32_t w3; 192 uint32_t w4; 193 uint32_t w5; 194 uint32_t w6; 195 uint32_t w7; 196 } Xive2Nvgc; 197 198 #endif /* PPC_XIVE2_REGS_H */ 199