xref: /openbmc/qemu/include/hw/ppc/xive2.h (revision 700784bf)
1 /*
2  * QEMU PowerPC XIVE2 interrupt controller model  (POWER10)
3  *
4  * Copyright (c) 2019-2022, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  *
9  */
10 
11 #ifndef PPC_XIVE2_H
12 #define PPC_XIVE2_H
13 
14 #include "hw/ppc/xive.h"
15 #include "hw/ppc/xive2_regs.h"
16 #include "hw/sysbus.h"
17 
18 /*
19  * XIVE2 Router (POWER10)
20  */
21 typedef struct Xive2Router {
22     SysBusDevice    parent;
23 
24     XiveFabric *xfb;
25 } Xive2Router;
26 
27 #define TYPE_XIVE2_ROUTER "xive2-router"
28 OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);
29 
30 /*
31  * Configuration flags
32  */
33 
34 #define XIVE2_GEN1_TIMA_OS      0x00000001
35 #define XIVE2_VP_SAVE_RESTORE   0x00000002
36 #define XIVE2_THREADID_8BITS    0x00000004
37 
38 typedef struct Xive2RouterClass {
39     SysBusDeviceClass parent;
40 
41     /* XIVE table accessors */
42     int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
43                    Xive2Eas *eas);
44     int (*get_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
45                   uint8_t *pq);
46     int (*set_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
47                   uint8_t *pq);
48     int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
49                    Xive2End *end);
50     int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
51                      Xive2End *end, uint8_t word_number);
52     int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
53                    Xive2Nvp *nvp);
54     int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
55                      Xive2Nvp *nvp, uint8_t word_number);
56     int (*get_nvgc)(Xive2Router *xrtr, bool crowd,
57                     uint8_t nvgc_blk, uint32_t nvgc_idx,
58                     Xive2Nvgc *nvgc);
59     int (*write_nvgc)(Xive2Router *xrtr, bool crowd,
60                       uint8_t nvgc_blk, uint32_t nvgc_idx,
61                       Xive2Nvgc *nvgc);
62     uint8_t (*get_block_id)(Xive2Router *xrtr);
63     uint32_t (*get_config)(Xive2Router *xrtr);
64 } Xive2RouterClass;
65 
66 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
67                         Xive2Eas *eas);
68 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
69                         Xive2End *end);
70 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
71                           Xive2End *end, uint8_t word_number);
72 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
73                         Xive2Nvp *nvp);
74 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
75                           Xive2Nvp *nvp, uint8_t word_number);
76 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd,
77                           uint8_t nvgc_blk, uint32_t nvgc_idx,
78                           Xive2Nvgc *nvgc);
79 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd,
80                             uint8_t nvgc_blk, uint32_t nvgc_idx,
81                             Xive2Nvgc *nvgc);
82 uint32_t xive2_router_get_config(Xive2Router *xrtr);
83 
84 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
85 
86 /*
87  * XIVE2 Presenter (POWER10)
88  */
89 
90 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
91                                uint8_t format,
92                                uint8_t nvt_blk, uint32_t nvt_idx,
93                                bool cam_ignore, uint32_t logic_serv);
94 
95 /*
96  * XIVE2 END ESBs  (POWER10)
97  */
98 
99 #define TYPE_XIVE2_END_SOURCE "xive2-end-source"
100 OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE)
101 
102 typedef struct Xive2EndSource {
103     DeviceState parent;
104 
105     uint32_t        nr_ends;
106 
107     /* ESB memory region */
108     uint32_t        esb_shift;
109     MemoryRegion    esb_mmio;
110 
111     Xive2Router     *xrtr;
112 } Xive2EndSource;
113 
114 /*
115  * XIVE2 Thread Interrupt Management Area (POWER10)
116  */
117 
118 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
119                            uint64_t value, unsigned size);
120 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
121                                hwaddr offset, unsigned size);
122 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
123                              hwaddr offset, uint64_t value, unsigned size);
124 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
125                             hwaddr offset, uint64_t value, unsigned size);
126 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
127                                hwaddr offset, uint64_t value, unsigned size);
128 
129 #endif /* PPC_XIVE2_H */
130