1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 * 9 */ 10 11 #ifndef PPC_XIVE2_H 12 #define PPC_XIVE2_H 13 14 #include "hw/ppc/xive2_regs.h" 15 16 /* 17 * XIVE2 Router (POWER10) 18 */ 19 typedef struct Xive2Router { 20 SysBusDevice parent; 21 22 XiveFabric *xfb; 23 } Xive2Router; 24 25 #define TYPE_XIVE2_ROUTER "xive2-router" 26 OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER); 27 28 /* 29 * Configuration flags 30 */ 31 32 #define XIVE2_GEN1_TIMA_OS 0x00000001 33 #define XIVE2_VP_SAVE_RESTORE 0x00000002 34 #define XIVE2_THREADID_8BITS 0x00000004 35 36 typedef struct Xive2RouterClass { 37 SysBusDeviceClass parent; 38 39 /* XIVE table accessors */ 40 int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 41 Xive2Eas *eas); 42 int (*get_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 43 uint8_t *pq); 44 int (*set_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 45 uint8_t *pq); 46 int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 47 Xive2End *end); 48 int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 49 Xive2End *end, uint8_t word_number); 50 int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 51 Xive2Nvp *nvp); 52 int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 53 Xive2Nvp *nvp, uint8_t word_number); 54 uint8_t (*get_block_id)(Xive2Router *xrtr); 55 uint32_t (*get_config)(Xive2Router *xrtr); 56 } Xive2RouterClass; 57 58 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 59 Xive2Eas *eas); 60 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 61 Xive2End *end); 62 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 63 Xive2End *end, uint8_t word_number); 64 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 65 Xive2Nvp *nvp); 66 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 67 Xive2Nvp *nvp, uint8_t word_number); 68 uint32_t xive2_router_get_config(Xive2Router *xrtr); 69 70 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked); 71 72 /* 73 * XIVE2 Presenter (POWER10) 74 */ 75 76 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 77 uint8_t format, 78 uint8_t nvt_blk, uint32_t nvt_idx, 79 bool cam_ignore, uint32_t logic_serv); 80 81 /* 82 * XIVE2 END ESBs (POWER10) 83 */ 84 85 #define TYPE_XIVE2_END_SOURCE "xive2-end-source" 86 OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE) 87 88 typedef struct Xive2EndSource { 89 DeviceState parent; 90 91 uint32_t nr_ends; 92 93 /* ESB memory region */ 94 uint32_t esb_shift; 95 MemoryRegion esb_mmio; 96 97 Xive2Router *xrtr; 98 } Xive2EndSource; 99 100 /* 101 * XIVE2 Thread Interrupt Management Area (POWER10) 102 */ 103 104 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 105 uint64_t value, unsigned size); 106 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 107 hwaddr offset, unsigned size); 108 109 #endif /* PPC_XIVE2_H */ 110