1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * 5 * The POWER9 processor comes with a new interrupt controller, called 6 * XIVE as "eXternal Interrupt Virtualization Engine". 7 * 8 * = Overall architecture 9 * 10 * 11 * XIVE Interrupt Controller 12 * +------------------------------------+ IPIs 13 * | +---------+ +---------+ +--------+ | +-------+ 14 * | |VC | |CQ | |PC |----> | CORES | 15 * | | esb | | | | |----> | | 16 * | | eas | | Bridge | | tctx |----> | | 17 * | |SC end | | | | nvt | | | | 18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+ 19 * | RAM | +------------------|-----------------+ | | | 20 * | | | | | | 21 * | | | | | | 22 * | | +--------------------v------------------------v-v-v--+ other 23 * | <--+ Power Bus +--> chips 24 * | esb | +---------+-----------------------+------------------+ 25 * | eas | | | 26 * | end | +--|------+ | 27 * | nvt | +----+----+ | +----+----+ 28 * +------+ |SC | | |SC | 29 * | | | | | 30 * | PQ-bits | | | PQ-bits | 31 * | local |-+ | in VC | 32 * +---------+ +---------+ 33 * PCIe NX,NPU,CAPI 34 * 35 * SC: Source Controller (aka. IVSE) 36 * VC: Virtualization Controller (aka. IVRE) 37 * PC: Presentation Controller (aka. IVPE) 38 * CQ: Common Queue (Bridge) 39 * 40 * PQ-bits: 2 bits source state machine (P:pending Q:queued) 41 * esb: Event State Buffer (Array of PQ bits in an IVSE) 42 * eas: Event Assignment Structure 43 * end: Event Notification Descriptor 44 * nvt: Notification Virtual Target 45 * tctx: Thread interrupt Context 46 * 47 * 48 * The XIVE IC is composed of three sub-engines : 49 * 50 * - Interrupt Virtualization Source Engine (IVSE), or Source 51 * Controller (SC). These are found in PCI PHBs, in the PSI host 52 * bridge controller, but also inside the main controller for the 53 * core IPIs and other sub-chips (NX, CAP, NPU) of the 54 * chip/processor. They are configured to feed the IVRE with events. 55 * 56 * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization 57 * Controller (VC). Its job is to match an event source with an 58 * Event Notification Descriptor (END). 59 * 60 * - Interrupt Virtualization Presentation Engine (IVPE) or 61 * Presentation Controller (PC). It maintains the interrupt context 62 * state of each thread and handles the delivery of the external 63 * exception to the thread. 64 * 65 * In XIVE 1.0, the sub-engines used to be referred as: 66 * 67 * SC Source Controller 68 * VC Virtualization Controller 69 * PC Presentation Controller 70 * CQ Common Queue (PowerBUS Bridge) 71 * 72 * 73 * = XIVE internal tables 74 * 75 * Each of the sub-engines uses a set of tables to redirect exceptions 76 * from event sources to CPU threads. 77 * 78 * +-------+ 79 * User or OS | EQ | 80 * or +------>|entries| 81 * Hypervisor | | .. | 82 * Memory | +-------+ 83 * | ^ 84 * | | 85 * +-------------------------------------------------+ 86 * | | 87 * Hypervisor +------+ +---+--+ +---+--+ +------+ 88 * Memory | ESB | | EAT | | ENDT | | NVTT | 89 * (skiboot) +----+-+ +----+-+ +----+-+ +------+ 90 * ^ | ^ | ^ | ^ 91 * | | | | | | | 92 * +-------------------------------------------------+ 93 * | | | | | | | 94 * | | | | | | | 95 * +----|--|--------|--|--------|--|-+ +-|-----+ +------+ 96 * | | | | | | | | | | tctx| |Thread| 97 * IPI or --> | + v + v + v |---| + .. |-----> | 98 * HW events --> | | | | | | 99 * IVSE | IVRE | | IVPE | +------+ 100 * +---------------------------------+ +-------+ 101 * 102 * 103 * 104 * The IVSE have a 2-bits state machine, P for pending and Q for queued, 105 * for each source that allows events to be triggered. They are stored in 106 * an Event State Buffer (ESB) array and can be controlled by MMIOs. 107 * 108 * If the event is let through, the IVRE looks up in the Event Assignment 109 * Structure (EAS) table for an Event Notification Descriptor (END) 110 * configured for the source. Each Event Notification Descriptor defines 111 * a notification path to a CPU and an in-memory Event Queue, in which 112 * will be enqueued an EQ data for the OS to pull. 113 * 114 * The IVPE determines if a Notification Virtual Target (NVT) can 115 * handle the event by scanning the thread contexts of the VCPUs 116 * dispatched on the processor HW threads. It maintains the state of 117 * the thread interrupt context (TCTX) of each thread in a NVT table. 118 * 119 * = Acronyms 120 * 121 * Description In XIVE 1.0, used to be referred as 122 * 123 * EAS Event Assignment Structure IVE Interrupt Virt. Entry 124 * EAT Event Assignment Table IVT Interrupt Virt. Table 125 * ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table 126 * EQ Event Queue same 127 * ESB Event State Buffer SBE State Bit Entry 128 * NVT Notif. Virtual Target VPD Virtual Processor Desc. 129 * NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table 130 * TCTX Thread interrupt Context 131 * 132 * 133 * Copyright (c) 2017-2018, IBM Corporation. 134 * 135 * This code is licensed under the GPL version 2 or later. See the 136 * COPYING file in the top-level directory. 137 * 138 */ 139 140 #ifndef PPC_XIVE_H 141 #define PPC_XIVE_H 142 143 #include "sysemu/kvm.h" 144 #include "hw/sysbus.h" 145 #include "hw/ppc/xive_regs.h" 146 #include "qom/object.h" 147 148 /* 149 * XIVE Notifier (Interface between Source and Router) 150 */ 151 152 typedef struct XiveNotifier XiveNotifier; 153 154 #define TYPE_XIVE_NOTIFIER "xive-notifier" 155 #define XIVE_NOTIFIER(obj) \ 156 INTERFACE_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER) 157 typedef struct XiveNotifierClass XiveNotifierClass; 158 DECLARE_CLASS_CHECKERS(XiveNotifierClass, XIVE_NOTIFIER, 159 TYPE_XIVE_NOTIFIER) 160 161 struct XiveNotifierClass { 162 InterfaceClass parent; 163 void (*notify)(XiveNotifier *xn, uint32_t lisn, bool pq_checked); 164 }; 165 166 /* 167 * XIVE Interrupt Source 168 */ 169 170 #define TYPE_XIVE_SOURCE "xive-source" 171 OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE) 172 173 /* 174 * XIVE Interrupt Source characteristics, which define how the ESB are 175 * controlled. 176 */ 177 #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */ 178 #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */ 179 #define XIVE_SRC_PQ_DISABLE 0x4 /* Disable check on the PQ state bits */ 180 181 struct XiveSource { 182 DeviceState parent; 183 184 /* IRQs */ 185 uint32_t nr_irqs; 186 unsigned long *lsi_map; 187 188 /* PQ bits and LSI assertion bit */ 189 uint8_t *status; 190 191 /* ESB memory region */ 192 uint64_t esb_flags; 193 uint32_t esb_shift; 194 MemoryRegion esb_mmio; 195 MemoryRegion esb_mmio_emulated; 196 197 /* KVM support */ 198 void *esb_mmap; 199 MemoryRegion esb_mmio_kvm; 200 201 XiveNotifier *xive; 202 }; 203 204 /* 205 * ESB MMIO setting. Can be one page, for both source triggering and 206 * source management, or two different pages. See below for magic 207 * values. 208 */ 209 #define XIVE_ESB_4K 12 /* PSI HB only */ 210 #define XIVE_ESB_4K_2PAGE 13 211 #define XIVE_ESB_64K 16 212 #define XIVE_ESB_64K_2PAGE 17 213 214 static inline bool xive_source_esb_has_2page(XiveSource *xsrc) 215 { 216 return xsrc->esb_shift == XIVE_ESB_64K_2PAGE || 217 xsrc->esb_shift == XIVE_ESB_4K_2PAGE; 218 } 219 220 static inline size_t xive_source_esb_len(XiveSource *xsrc) 221 { 222 return (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 223 } 224 225 /* The trigger page is always the first/even page */ 226 static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno) 227 { 228 assert(srcno < xsrc->nr_irqs); 229 return (1ull << xsrc->esb_shift) * srcno; 230 } 231 232 /* In a two pages ESB MMIO setting, the odd page is for management */ 233 static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno) 234 { 235 hwaddr addr = xive_source_esb_page(xsrc, srcno); 236 237 if (xive_source_esb_has_2page(xsrc)) { 238 addr += (1 << (xsrc->esb_shift - 1)); 239 } 240 241 return addr; 242 } 243 244 /* 245 * Each interrupt source has a 2-bit state machine which can be 246 * controlled by MMIO. P indicates that an interrupt is pending (has 247 * been sent to a queue and is waiting for an EOI). Q indicates that 248 * the interrupt has been triggered while pending. 249 * 250 * This acts as a coalescing mechanism in order to guarantee that a 251 * given interrupt only occurs at most once in a queue. 252 * 253 * When doing an EOI, the Q bit will indicate if the interrupt 254 * needs to be re-triggered. 255 */ 256 #define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */ 257 #define XIVE_ESB_VAL_P 0x2 258 #define XIVE_ESB_VAL_Q 0x1 259 260 #define XIVE_ESB_RESET 0x0 261 #define XIVE_ESB_PENDING XIVE_ESB_VAL_P 262 #define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q) 263 #define XIVE_ESB_OFF XIVE_ESB_VAL_Q 264 265 bool xive_esb_trigger(uint8_t *pq); 266 bool xive_esb_eoi(uint8_t *pq); 267 uint8_t xive_esb_set(uint8_t *pq, uint8_t value); 268 269 /* 270 * "magic" Event State Buffer (ESB) MMIO offsets. 271 * 272 * The following offsets into the ESB MMIO allow to read or manipulate 273 * the PQ bits. They must be used with an 8-byte load instruction. 274 * They all return the previous state of the interrupt (atomically). 275 * 276 * Additionally, some ESB pages support doing an EOI via a store and 277 * some ESBs support doing a trigger via a separate trigger page. 278 */ 279 #define XIVE_ESB_STORE_EOI 0x400 /* Store */ 280 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */ 281 #define XIVE_ESB_GET 0x800 /* Load */ 282 #define XIVE_ESB_INJECT 0x800 /* Store */ 283 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ 284 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ 285 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ 286 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ 287 288 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno); 289 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq); 290 291 /* 292 * Source status helpers 293 */ 294 static inline void xive_source_set_status(XiveSource *xsrc, uint32_t srcno, 295 uint8_t status, bool enable) 296 { 297 if (enable) { 298 xsrc->status[srcno] |= status; 299 } else { 300 xsrc->status[srcno] &= ~status; 301 } 302 } 303 304 static inline void xive_source_set_asserted(XiveSource *xsrc, uint32_t srcno, 305 bool enable) 306 { 307 xive_source_set_status(xsrc, srcno, XIVE_STATUS_ASSERTED, enable); 308 } 309 310 static inline bool xive_source_is_asserted(XiveSource *xsrc, uint32_t srcno) 311 { 312 return xsrc->status[srcno] & XIVE_STATUS_ASSERTED; 313 } 314 315 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, 316 Monitor *mon); 317 318 static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno) 319 { 320 assert(srcno < xsrc->nr_irqs); 321 return test_bit(srcno, xsrc->lsi_map); 322 } 323 324 static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno) 325 { 326 assert(srcno < xsrc->nr_irqs); 327 bitmap_set(xsrc->lsi_map, srcno, 1); 328 } 329 330 void xive_source_set_irq(void *opaque, int srcno, int val); 331 332 /* 333 * XIVE Thread interrupt Management (TM) context 334 */ 335 336 #define TYPE_XIVE_TCTX "xive-tctx" 337 OBJECT_DECLARE_SIMPLE_TYPE(XiveTCTX, XIVE_TCTX) 338 339 /* 340 * XIVE Thread interrupt Management register rings : 341 * 342 * QW-0 User event-based exception state 343 * QW-1 O/S OS context for priority management, interrupt acks 344 * QW-2 Pool hypervisor pool context for virtual processors dispatched 345 * QW-3 Physical physical thread context and security context 346 */ 347 #define XIVE_TM_RING_COUNT 4 348 #define XIVE_TM_RING_SIZE 0x10 349 350 typedef struct XivePresenter XivePresenter; 351 352 struct XiveTCTX { 353 DeviceState parent_obj; 354 355 CPUState *cs; 356 qemu_irq hv_output; 357 qemu_irq os_output; 358 359 uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; 360 361 XivePresenter *xptr; 362 }; 363 364 static inline uint32_t xive_tctx_word2(uint8_t *ring) 365 { 366 return *((uint32_t *) &ring[TM_WORD2]); 367 } 368 369 /* 370 * XIVE Router 371 */ 372 typedef struct XiveFabric XiveFabric; 373 374 struct XiveRouter { 375 SysBusDevice parent; 376 377 XiveFabric *xfb; 378 }; 379 380 #define TYPE_XIVE_ROUTER "xive-router" 381 OBJECT_DECLARE_TYPE(XiveRouter, XiveRouterClass, 382 XIVE_ROUTER) 383 384 struct XiveRouterClass { 385 SysBusDeviceClass parent; 386 387 /* XIVE table accessors */ 388 int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 389 XiveEAS *eas); 390 int (*get_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 391 uint8_t *pq); 392 int (*set_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 393 uint8_t *pq); 394 int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 395 XiveEND *end); 396 int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 397 XiveEND *end, uint8_t word_number); 398 int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 399 XiveNVT *nvt); 400 int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 401 XiveNVT *nvt, uint8_t word_number); 402 uint8_t (*get_block_id)(XiveRouter *xrtr); 403 }; 404 405 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 406 XiveEAS *eas); 407 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 408 XiveEND *end); 409 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 410 XiveEND *end, uint8_t word_number); 411 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 412 XiveNVT *nvt); 413 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 414 XiveNVT *nvt, uint8_t word_number); 415 void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked); 416 417 /* 418 * XIVE Presenter 419 */ 420 421 typedef struct XiveTCTXMatch { 422 XiveTCTX *tctx; 423 uint8_t ring; 424 } XiveTCTXMatch; 425 426 #define TYPE_XIVE_PRESENTER "xive-presenter" 427 #define XIVE_PRESENTER(obj) \ 428 INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER) 429 typedef struct XivePresenterClass XivePresenterClass; 430 DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESENTER, 431 TYPE_XIVE_PRESENTER) 432 433 struct XivePresenterClass { 434 InterfaceClass parent; 435 int (*match_nvt)(XivePresenter *xptr, uint8_t format, 436 uint8_t nvt_blk, uint32_t nvt_idx, 437 bool cam_ignore, uint8_t priority, 438 uint32_t logic_serv, XiveTCTXMatch *match); 439 bool (*in_kernel)(const XivePresenter *xptr); 440 }; 441 442 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 443 uint8_t format, 444 uint8_t nvt_blk, uint32_t nvt_idx, 445 bool cam_ignore, uint32_t logic_serv); 446 bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, 447 uint8_t nvt_blk, uint32_t nvt_idx, 448 bool cam_ignore, uint8_t priority, 449 uint32_t logic_serv); 450 451 /* 452 * XIVE Fabric (Interface between Interrupt Controller and Machine) 453 */ 454 455 #define TYPE_XIVE_FABRIC "xive-fabric" 456 #define XIVE_FABRIC(obj) \ 457 INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC) 458 typedef struct XiveFabricClass XiveFabricClass; 459 DECLARE_CLASS_CHECKERS(XiveFabricClass, XIVE_FABRIC, 460 TYPE_XIVE_FABRIC) 461 462 struct XiveFabricClass { 463 InterfaceClass parent; 464 int (*match_nvt)(XiveFabric *xfb, uint8_t format, 465 uint8_t nvt_blk, uint32_t nvt_idx, 466 bool cam_ignore, uint8_t priority, 467 uint32_t logic_serv, XiveTCTXMatch *match); 468 }; 469 470 /* 471 * XIVE END ESBs 472 */ 473 474 #define TYPE_XIVE_END_SOURCE "xive-end-source" 475 OBJECT_DECLARE_SIMPLE_TYPE(XiveENDSource, XIVE_END_SOURCE) 476 477 struct XiveENDSource { 478 DeviceState parent; 479 480 uint32_t nr_ends; 481 482 /* ESB memory region */ 483 uint32_t esb_shift; 484 MemoryRegion esb_mmio; 485 486 XiveRouter *xrtr; 487 }; 488 489 /* 490 * For legacy compatibility, the exceptions define up to 256 different 491 * priorities. P9 implements only 9 levels : 8 active levels [0 - 7] 492 * and the least favored level 0xFF. 493 */ 494 #define XIVE_PRIORITY_MAX 7 495 496 /* 497 * Convert a priority number to an Interrupt Pending Buffer (IPB) 498 * register, which indicates a pending interrupt at the priority 499 * corresponding to the bit number 500 */ 501 static inline uint8_t xive_priority_to_ipb(uint8_t priority) 502 { 503 return priority > XIVE_PRIORITY_MAX ? 504 0 : 1 << (XIVE_PRIORITY_MAX - priority); 505 } 506 507 /* 508 * XIVE Thread Interrupt Management Aera (TIMA) 509 * 510 * This region gives access to the registers of the thread interrupt 511 * management context. It is four page wide, each page providing a 512 * different view of the registers. The page with the lower offset is 513 * the most privileged and gives access to the entire context. 514 */ 515 #define XIVE_TM_HW_PAGE 0x0 516 #define XIVE_TM_HV_PAGE 0x1 517 #define XIVE_TM_OS_PAGE 0x2 518 #define XIVE_TM_USER_PAGE 0x3 519 520 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 521 uint64_t value, unsigned size); 522 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, 523 unsigned size); 524 525 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); 526 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp); 527 void xive_tctx_reset(XiveTCTX *tctx); 528 void xive_tctx_destroy(XiveTCTX *tctx); 529 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); 530 531 /* 532 * KVM XIVE device helpers 533 */ 534 535 int kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp); 536 void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val); 537 int kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp); 538 int kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp); 539 int kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp); 540 int kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp); 541 542 #endif /* PPC_XIVE_H */ 543