1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * 5 * The POWER9 processor comes with a new interrupt controller, called 6 * XIVE as "eXternal Interrupt Virtualization Engine". 7 * 8 * = Overall architecture 9 * 10 * 11 * XIVE Interrupt Controller 12 * +------------------------------------+ IPIs 13 * | +---------+ +---------+ +--------+ | +-------+ 14 * | |VC | |CQ | |PC |----> | CORES | 15 * | | esb | | | | |----> | | 16 * | | eas | | Bridge | | tctx |----> | | 17 * | |SC end | | | | nvt | | | | 18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+ 19 * | RAM | +------------------|-----------------+ | | | 20 * | | | | | | 21 * | | | | | | 22 * | | +--------------------v------------------------v-v-v--+ other 23 * | <--+ Power Bus +--> chips 24 * | esb | +---------+-----------------------+------------------+ 25 * | eas | | | 26 * | end | +--|------+ | 27 * | nvt | +----+----+ | +----+----+ 28 * +------+ |SC | | |SC | 29 * | | | | | 30 * | PQ-bits | | | PQ-bits | 31 * | local |-+ | in VC | 32 * +---------+ +---------+ 33 * PCIe NX,NPU,CAPI 34 * 35 * SC: Source Controller (aka. IVSE) 36 * VC: Virtualization Controller (aka. IVRE) 37 * PC: Presentation Controller (aka. IVPE) 38 * CQ: Common Queue (Bridge) 39 * 40 * PQ-bits: 2 bits source state machine (P:pending Q:queued) 41 * esb: Event State Buffer (Array of PQ bits in an IVSE) 42 * eas: Event Assignment Structure 43 * end: Event Notification Descriptor 44 * nvt: Notification Virtual Target 45 * tctx: Thread interrupt Context 46 * 47 * 48 * The XIVE IC is composed of three sub-engines : 49 * 50 * - Interrupt Virtualization Source Engine (IVSE), or Source 51 * Controller (SC). These are found in PCI PHBs, in the PSI host 52 * bridge controller, but also inside the main controller for the 53 * core IPIs and other sub-chips (NX, CAP, NPU) of the 54 * chip/processor. They are configured to feed the IVRE with events. 55 * 56 * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization 57 * Controller (VC). Its job is to match an event source with an 58 * Event Notification Descriptor (END). 59 * 60 * - Interrupt Virtualization Presentation Engine (IVPE) or 61 * Presentation Controller (PC). It maintains the interrupt context 62 * state of each thread and handles the delivery of the external 63 * exception to the thread. 64 * 65 * In XIVE 1.0, the sub-engines used to be referred as: 66 * 67 * SC Source Controller 68 * VC Virtualization Controller 69 * PC Presentation Controller 70 * CQ Common Queue (PowerBUS Bridge) 71 * 72 * 73 * = XIVE internal tables 74 * 75 * Each of the sub-engines uses a set of tables to redirect exceptions 76 * from event sources to CPU threads. 77 * 78 * +-------+ 79 * User or OS | EQ | 80 * or +------>|entries| 81 * Hypervisor | | .. | 82 * Memory | +-------+ 83 * | ^ 84 * | | 85 * +-------------------------------------------------+ 86 * | | 87 * Hypervisor +------+ +---+--+ +---+--+ +------+ 88 * Memory | ESB | | EAT | | ENDT | | NVTT | 89 * (skiboot) +----+-+ +----+-+ +----+-+ +------+ 90 * ^ | ^ | ^ | ^ 91 * | | | | | | | 92 * +-------------------------------------------------+ 93 * | | | | | | | 94 * | | | | | | | 95 * +----|--|--------|--|--------|--|-+ +-|-----+ +------+ 96 * | | | | | | | | | | tctx| |Thread| 97 * IPI or --> | + v + v + v |---| + .. |-----> | 98 * HW events --> | | | | | | 99 * IVSE | IVRE | | IVPE | +------+ 100 * +---------------------------------+ +-------+ 101 * 102 * 103 * 104 * The IVSE have a 2-bits state machine, P for pending and Q for queued, 105 * for each source that allows events to be triggered. They are stored in 106 * an Event State Buffer (ESB) array and can be controlled by MMIOs. 107 * 108 * If the event is let through, the IVRE looks up in the Event Assignment 109 * Structure (EAS) table for an Event Notification Descriptor (END) 110 * configured for the source. Each Event Notification Descriptor defines 111 * a notification path to a CPU and an in-memory Event Queue, in which 112 * will be enqueued an EQ data for the OS to pull. 113 * 114 * The IVPE determines if a Notification Virtual Target (NVT) can 115 * handle the event by scanning the thread contexts of the VCPUs 116 * dispatched on the processor HW threads. It maintains the state of 117 * the thread interrupt context (TCTX) of each thread in a NVT table. 118 * 119 * = Acronyms 120 * 121 * Description In XIVE 1.0, used to be referred as 122 * 123 * EAS Event Assignment Structure IVE Interrupt Virt. Entry 124 * EAT Event Assignment Table IVT Interrupt Virt. Table 125 * ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table 126 * EQ Event Queue same 127 * ESB Event State Buffer SBE State Bit Entry 128 * NVT Notif. Virtual Target VPD Virtual Processor Desc. 129 * NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table 130 * TCTX Thread interrupt Context 131 * 132 * 133 * Copyright (c) 2017-2018, IBM Corporation. 134 * 135 * This code is licensed under the GPL version 2 or later. See the 136 * COPYING file in the top-level directory. 137 * 138 */ 139 140 #ifndef PPC_XIVE_H 141 #define PPC_XIVE_H 142 143 #include "sysemu/kvm.h" 144 #include "hw/sysbus.h" 145 #include "hw/ppc/xive_regs.h" 146 147 /* 148 * XIVE Notifier (Interface between Source and Router) 149 */ 150 151 typedef struct XiveNotifier XiveNotifier; 152 153 #define TYPE_XIVE_NOTIFIER "xive-notifier" 154 #define XIVE_NOTIFIER(obj) \ 155 INTERFACE_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER) 156 #define XIVE_NOTIFIER_CLASS(klass) \ 157 OBJECT_CLASS_CHECK(XiveNotifierClass, (klass), TYPE_XIVE_NOTIFIER) 158 #define XIVE_NOTIFIER_GET_CLASS(obj) \ 159 OBJECT_GET_CLASS(XiveNotifierClass, (obj), TYPE_XIVE_NOTIFIER) 160 161 typedef struct XiveNotifierClass { 162 InterfaceClass parent; 163 void (*notify)(XiveNotifier *xn, uint32_t lisn); 164 } XiveNotifierClass; 165 166 /* 167 * XIVE Interrupt Source 168 */ 169 170 #define TYPE_XIVE_SOURCE "xive-source" 171 #define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE) 172 173 /* 174 * XIVE Interrupt Source characteristics, which define how the ESB are 175 * controlled. 176 */ 177 #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */ 178 #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */ 179 180 typedef struct XiveSource { 181 DeviceState parent; 182 183 /* IRQs */ 184 uint32_t nr_irqs; 185 unsigned long *lsi_map; 186 187 /* PQ bits and LSI assertion bit */ 188 uint8_t *status; 189 190 /* ESB memory region */ 191 uint64_t esb_flags; 192 uint32_t esb_shift; 193 MemoryRegion esb_mmio; 194 195 /* KVM support */ 196 void *esb_mmap; 197 MemoryRegion esb_mmio_kvm; 198 199 XiveNotifier *xive; 200 } XiveSource; 201 202 /* 203 * ESB MMIO setting. Can be one page, for both source triggering and 204 * source management, or two different pages. See below for magic 205 * values. 206 */ 207 #define XIVE_ESB_4K 12 /* PSI HB only */ 208 #define XIVE_ESB_4K_2PAGE 13 209 #define XIVE_ESB_64K 16 210 #define XIVE_ESB_64K_2PAGE 17 211 212 static inline bool xive_source_esb_has_2page(XiveSource *xsrc) 213 { 214 return xsrc->esb_shift == XIVE_ESB_64K_2PAGE || 215 xsrc->esb_shift == XIVE_ESB_4K_2PAGE; 216 } 217 218 /* The trigger page is always the first/even page */ 219 static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno) 220 { 221 assert(srcno < xsrc->nr_irqs); 222 return (1ull << xsrc->esb_shift) * srcno; 223 } 224 225 /* In a two pages ESB MMIO setting, the odd page is for management */ 226 static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno) 227 { 228 hwaddr addr = xive_source_esb_page(xsrc, srcno); 229 230 if (xive_source_esb_has_2page(xsrc)) { 231 addr += (1 << (xsrc->esb_shift - 1)); 232 } 233 234 return addr; 235 } 236 237 /* 238 * Each interrupt source has a 2-bit state machine which can be 239 * controlled by MMIO. P indicates that an interrupt is pending (has 240 * been sent to a queue and is waiting for an EOI). Q indicates that 241 * the interrupt has been triggered while pending. 242 * 243 * This acts as a coalescing mechanism in order to guarantee that a 244 * given interrupt only occurs at most once in a queue. 245 * 246 * When doing an EOI, the Q bit will indicate if the interrupt 247 * needs to be re-triggered. 248 */ 249 #define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */ 250 #define XIVE_ESB_VAL_P 0x2 251 #define XIVE_ESB_VAL_Q 0x1 252 253 #define XIVE_ESB_RESET 0x0 254 #define XIVE_ESB_PENDING XIVE_ESB_VAL_P 255 #define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q) 256 #define XIVE_ESB_OFF XIVE_ESB_VAL_Q 257 258 /* 259 * "magic" Event State Buffer (ESB) MMIO offsets. 260 * 261 * The following offsets into the ESB MMIO allow to read or manipulate 262 * the PQ bits. They must be used with an 8-byte load instruction. 263 * They all return the previous state of the interrupt (atomically). 264 * 265 * Additionally, some ESB pages support doing an EOI via a store and 266 * some ESBs support doing a trigger via a separate trigger page. 267 */ 268 #define XIVE_ESB_STORE_EOI 0x400 /* Store */ 269 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */ 270 #define XIVE_ESB_GET 0x800 /* Load */ 271 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ 272 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ 273 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ 274 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ 275 276 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno); 277 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq); 278 279 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, 280 Monitor *mon); 281 282 static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno) 283 { 284 assert(srcno < xsrc->nr_irqs); 285 return test_bit(srcno, xsrc->lsi_map); 286 } 287 288 static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno) 289 { 290 assert(srcno < xsrc->nr_irqs); 291 bitmap_set(xsrc->lsi_map, srcno, 1); 292 } 293 294 void xive_source_set_irq(void *opaque, int srcno, int val); 295 296 /* 297 * XIVE Thread interrupt Management (TM) context 298 */ 299 300 #define TYPE_XIVE_TCTX "xive-tctx" 301 #define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX) 302 303 /* 304 * XIVE Thread interrupt Management register rings : 305 * 306 * QW-0 User event-based exception state 307 * QW-1 O/S OS context for priority management, interrupt acks 308 * QW-2 Pool hypervisor pool context for virtual processors dispatched 309 * QW-3 Physical physical thread context and security context 310 */ 311 #define XIVE_TM_RING_COUNT 4 312 #define XIVE_TM_RING_SIZE 0x10 313 314 typedef struct XiveTCTX { 315 DeviceState parent_obj; 316 317 CPUState *cs; 318 qemu_irq hv_output; 319 qemu_irq os_output; 320 321 uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; 322 } XiveTCTX; 323 324 /* 325 * XIVE Router 326 */ 327 328 typedef struct XiveRouter { 329 SysBusDevice parent; 330 } XiveRouter; 331 332 #define TYPE_XIVE_ROUTER "xive-router" 333 #define XIVE_ROUTER(obj) \ 334 OBJECT_CHECK(XiveRouter, (obj), TYPE_XIVE_ROUTER) 335 #define XIVE_ROUTER_CLASS(klass) \ 336 OBJECT_CLASS_CHECK(XiveRouterClass, (klass), TYPE_XIVE_ROUTER) 337 #define XIVE_ROUTER_GET_CLASS(obj) \ 338 OBJECT_GET_CLASS(XiveRouterClass, (obj), TYPE_XIVE_ROUTER) 339 340 typedef struct XiveRouterClass { 341 SysBusDeviceClass parent; 342 343 /* XIVE table accessors */ 344 int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 345 XiveEAS *eas); 346 int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 347 XiveEND *end); 348 int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 349 XiveEND *end, uint8_t word_number); 350 int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 351 XiveNVT *nvt); 352 int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 353 XiveNVT *nvt, uint8_t word_number); 354 XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); 355 } XiveRouterClass; 356 357 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 358 XiveEAS *eas); 359 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 360 XiveEND *end); 361 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 362 XiveEND *end, uint8_t word_number); 363 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 364 XiveNVT *nvt); 365 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 366 XiveNVT *nvt, uint8_t word_number); 367 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); 368 void xive_router_notify(XiveNotifier *xn, uint32_t lisn); 369 370 /* 371 * XIVE END ESBs 372 */ 373 374 #define TYPE_XIVE_END_SOURCE "xive-end-source" 375 #define XIVE_END_SOURCE(obj) \ 376 OBJECT_CHECK(XiveENDSource, (obj), TYPE_XIVE_END_SOURCE) 377 378 typedef struct XiveENDSource { 379 DeviceState parent; 380 381 uint32_t nr_ends; 382 uint8_t block_id; 383 384 /* ESB memory region */ 385 uint32_t esb_shift; 386 MemoryRegion esb_mmio; 387 388 XiveRouter *xrtr; 389 } XiveENDSource; 390 391 /* 392 * For legacy compatibility, the exceptions define up to 256 different 393 * priorities. P9 implements only 9 levels : 8 active levels [0 - 7] 394 * and the least favored level 0xFF. 395 */ 396 #define XIVE_PRIORITY_MAX 7 397 398 /* 399 * XIVE Thread Interrupt Management Aera (TIMA) 400 * 401 * This region gives access to the registers of the thread interrupt 402 * management context. It is four page wide, each page providing a 403 * different view of the registers. The page with the lower offset is 404 * the most privileged and gives access to the entire context. 405 */ 406 #define XIVE_TM_HW_PAGE 0x0 407 #define XIVE_TM_HV_PAGE 0x1 408 #define XIVE_TM_OS_PAGE 0x2 409 #define XIVE_TM_USER_PAGE 0x3 410 411 extern const MemoryRegionOps xive_tm_ops; 412 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 413 unsigned size); 414 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size); 415 416 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); 417 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); 418 419 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) 420 { 421 return (nvt_blk << 19) | nvt_idx; 422 } 423 424 /* 425 * KVM XIVE device helpers 426 */ 427 428 int kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp); 429 void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val); 430 void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp); 431 void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp); 432 void kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp); 433 void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp); 434 435 #endif /* PPC_XIVE_H */ 436