1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * 5 * The POWER9 processor comes with a new interrupt controller, called 6 * XIVE as "eXternal Interrupt Virtualization Engine". 7 * 8 * = Overall architecture 9 * 10 * 11 * XIVE Interrupt Controller 12 * +------------------------------------+ IPIs 13 * | +---------+ +---------+ +--------+ | +-------+ 14 * | |VC | |CQ | |PC |----> | CORES | 15 * | | esb | | | | |----> | | 16 * | | eas | | Bridge | | tctx |----> | | 17 * | |SC end | | | | nvt | | | | 18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+ 19 * | RAM | +------------------|-----------------+ | | | 20 * | | | | | | 21 * | | | | | | 22 * | | +--------------------v------------------------v-v-v--+ other 23 * | <--+ Power Bus +--> chips 24 * | esb | +---------+-----------------------+------------------+ 25 * | eas | | | 26 * | end | +--|------+ | 27 * | nvt | +----+----+ | +----+----+ 28 * +------+ |SC | | |SC | 29 * | | | | | 30 * | PQ-bits | | | PQ-bits | 31 * | local |-+ | in VC | 32 * +---------+ +---------+ 33 * PCIe NX,NPU,CAPI 34 * 35 * SC: Source Controller (aka. IVSE) 36 * VC: Virtualization Controller (aka. IVRE) 37 * PC: Presentation Controller (aka. IVPE) 38 * CQ: Common Queue (Bridge) 39 * 40 * PQ-bits: 2 bits source state machine (P:pending Q:queued) 41 * esb: Event State Buffer (Array of PQ bits in an IVSE) 42 * eas: Event Assignment Structure 43 * end: Event Notification Descriptor 44 * nvt: Notification Virtual Target 45 * tctx: Thread interrupt Context 46 * 47 * 48 * The XIVE IC is composed of three sub-engines : 49 * 50 * - Interrupt Virtualization Source Engine (IVSE), or Source 51 * Controller (SC). These are found in PCI PHBs, in the PSI host 52 * bridge controller, but also inside the main controller for the 53 * core IPIs and other sub-chips (NX, CAP, NPU) of the 54 * chip/processor. They are configured to feed the IVRE with events. 55 * 56 * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization 57 * Controller (VC). Its job is to match an event source with an 58 * Event Notification Descriptor (END). 59 * 60 * - Interrupt Virtualization Presentation Engine (IVPE) or 61 * Presentation Controller (PC). It maintains the interrupt context 62 * state of each thread and handles the delivery of the external 63 * exception to the thread. 64 * 65 * In XIVE 1.0, the sub-engines used to be referred as: 66 * 67 * SC Source Controller 68 * VC Virtualization Controller 69 * PC Presentation Controller 70 * CQ Common Queue (PowerBUS Bridge) 71 * 72 * 73 * = XIVE internal tables 74 * 75 * Each of the sub-engines uses a set of tables to redirect exceptions 76 * from event sources to CPU threads. 77 * 78 * +-------+ 79 * User or OS | EQ | 80 * or +------>|entries| 81 * Hypervisor | | .. | 82 * Memory | +-------+ 83 * | ^ 84 * | | 85 * +-------------------------------------------------+ 86 * | | 87 * Hypervisor +------+ +---+--+ +---+--+ +------+ 88 * Memory | ESB | | EAT | | ENDT | | NVTT | 89 * (skiboot) +----+-+ +----+-+ +----+-+ +------+ 90 * ^ | ^ | ^ | ^ 91 * | | | | | | | 92 * +-------------------------------------------------+ 93 * | | | | | | | 94 * | | | | | | | 95 * +----|--|--------|--|--------|--|-+ +-|-----+ +------+ 96 * | | | | | | | | | | tctx| |Thread| 97 * IPI or --> | + v + v + v |---| + .. |-----> | 98 * HW events --> | | | | | | 99 * IVSE | IVRE | | IVPE | +------+ 100 * +---------------------------------+ +-------+ 101 * 102 * 103 * 104 * The IVSE have a 2-bits state machine, P for pending and Q for queued, 105 * for each source that allows events to be triggered. They are stored in 106 * an Event State Buffer (ESB) array and can be controlled by MMIOs. 107 * 108 * If the event is let through, the IVRE looks up in the Event Assignment 109 * Structure (EAS) table for an Event Notification Descriptor (END) 110 * configured for the source. Each Event Notification Descriptor defines 111 * a notification path to a CPU and an in-memory Event Queue, in which 112 * will be enqueued an EQ data for the OS to pull. 113 * 114 * The IVPE determines if a Notification Virtual Target (NVT) can 115 * handle the event by scanning the thread contexts of the VCPUs 116 * dispatched on the processor HW threads. It maintains the state of 117 * the thread interrupt context (TCTX) of each thread in a NVT table. 118 * 119 * = Acronyms 120 * 121 * Description In XIVE 1.0, used to be referred as 122 * 123 * EAS Event Assignment Structure IVE Interrupt Virt. Entry 124 * EAT Event Assignment Table IVT Interrupt Virt. Table 125 * ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table 126 * EQ Event Queue same 127 * ESB Event State Buffer SBE State Bit Entry 128 * NVT Notif. Virtual Target VPD Virtual Processor Desc. 129 * NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table 130 * TCTX Thread interrupt Context 131 * 132 * 133 * Copyright (c) 2017-2018, IBM Corporation. 134 * 135 * This code is licensed under the GPL version 2 or later. See the 136 * COPYING file in the top-level directory. 137 * 138 */ 139 140 #ifndef PPC_XIVE_H 141 #define PPC_XIVE_H 142 143 #include "sysemu/kvm.h" 144 #include "hw/qdev-core.h" 145 #include "hw/sysbus.h" 146 #include "hw/ppc/xive_regs.h" 147 148 /* 149 * XIVE Notifier (Interface between Source and Router) 150 */ 151 152 typedef struct XiveNotifier { 153 Object parent; 154 } XiveNotifier; 155 156 #define TYPE_XIVE_NOTIFIER "xive-notifier" 157 #define XIVE_NOTIFIER(obj) \ 158 OBJECT_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER) 159 #define XIVE_NOTIFIER_CLASS(klass) \ 160 OBJECT_CLASS_CHECK(XiveNotifierClass, (klass), TYPE_XIVE_NOTIFIER) 161 #define XIVE_NOTIFIER_GET_CLASS(obj) \ 162 OBJECT_GET_CLASS(XiveNotifierClass, (obj), TYPE_XIVE_NOTIFIER) 163 164 typedef struct XiveNotifierClass { 165 InterfaceClass parent; 166 void (*notify)(XiveNotifier *xn, uint32_t lisn); 167 } XiveNotifierClass; 168 169 /* 170 * XIVE Interrupt Source 171 */ 172 173 #define TYPE_XIVE_SOURCE "xive-source" 174 #define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE) 175 176 /* 177 * XIVE Interrupt Source characteristics, which define how the ESB are 178 * controlled. 179 */ 180 #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */ 181 #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */ 182 183 typedef struct XiveSource { 184 DeviceState parent; 185 186 /* IRQs */ 187 uint32_t nr_irqs; 188 unsigned long *lsi_map; 189 190 /* PQ bits and LSI assertion bit */ 191 uint8_t *status; 192 193 /* ESB memory region */ 194 uint64_t esb_flags; 195 uint32_t esb_shift; 196 MemoryRegion esb_mmio; 197 198 /* KVM support */ 199 void *esb_mmap; 200 201 XiveNotifier *xive; 202 } XiveSource; 203 204 /* 205 * ESB MMIO setting. Can be one page, for both source triggering and 206 * source management, or two different pages. See below for magic 207 * values. 208 */ 209 #define XIVE_ESB_4K 12 /* PSI HB only */ 210 #define XIVE_ESB_4K_2PAGE 13 211 #define XIVE_ESB_64K 16 212 #define XIVE_ESB_64K_2PAGE 17 213 214 static inline bool xive_source_esb_has_2page(XiveSource *xsrc) 215 { 216 return xsrc->esb_shift == XIVE_ESB_64K_2PAGE || 217 xsrc->esb_shift == XIVE_ESB_4K_2PAGE; 218 } 219 220 /* The trigger page is always the first/even page */ 221 static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno) 222 { 223 assert(srcno < xsrc->nr_irqs); 224 return (1ull << xsrc->esb_shift) * srcno; 225 } 226 227 /* In a two pages ESB MMIO setting, the odd page is for management */ 228 static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno) 229 { 230 hwaddr addr = xive_source_esb_page(xsrc, srcno); 231 232 if (xive_source_esb_has_2page(xsrc)) { 233 addr += (1 << (xsrc->esb_shift - 1)); 234 } 235 236 return addr; 237 } 238 239 /* 240 * Each interrupt source has a 2-bit state machine which can be 241 * controlled by MMIO. P indicates that an interrupt is pending (has 242 * been sent to a queue and is waiting for an EOI). Q indicates that 243 * the interrupt has been triggered while pending. 244 * 245 * This acts as a coalescing mechanism in order to guarantee that a 246 * given interrupt only occurs at most once in a queue. 247 * 248 * When doing an EOI, the Q bit will indicate if the interrupt 249 * needs to be re-triggered. 250 */ 251 #define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */ 252 #define XIVE_ESB_VAL_P 0x2 253 #define XIVE_ESB_VAL_Q 0x1 254 255 #define XIVE_ESB_RESET 0x0 256 #define XIVE_ESB_PENDING XIVE_ESB_VAL_P 257 #define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q) 258 #define XIVE_ESB_OFF XIVE_ESB_VAL_Q 259 260 /* 261 * "magic" Event State Buffer (ESB) MMIO offsets. 262 * 263 * The following offsets into the ESB MMIO allow to read or manipulate 264 * the PQ bits. They must be used with an 8-byte load instruction. 265 * They all return the previous state of the interrupt (atomically). 266 * 267 * Additionally, some ESB pages support doing an EOI via a store and 268 * some ESBs support doing a trigger via a separate trigger page. 269 */ 270 #define XIVE_ESB_STORE_EOI 0x400 /* Store */ 271 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */ 272 #define XIVE_ESB_GET 0x800 /* Load */ 273 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ 274 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ 275 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ 276 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ 277 278 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno); 279 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq); 280 281 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, 282 Monitor *mon); 283 284 static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno) 285 { 286 assert(srcno < xsrc->nr_irqs); 287 return test_bit(srcno, xsrc->lsi_map); 288 } 289 290 static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno) 291 { 292 assert(srcno < xsrc->nr_irqs); 293 bitmap_set(xsrc->lsi_map, srcno, 1); 294 } 295 296 void xive_source_set_irq(void *opaque, int srcno, int val); 297 298 /* 299 * XIVE Thread interrupt Management (TM) context 300 */ 301 302 #define TYPE_XIVE_TCTX "xive-tctx" 303 #define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX) 304 305 /* 306 * XIVE Thread interrupt Management register rings : 307 * 308 * QW-0 User event-based exception state 309 * QW-1 O/S OS context for priority management, interrupt acks 310 * QW-2 Pool hypervisor pool context for virtual processors dispatched 311 * QW-3 Physical physical thread context and security context 312 */ 313 #define XIVE_TM_RING_COUNT 4 314 #define XIVE_TM_RING_SIZE 0x10 315 316 typedef struct XiveTCTX { 317 DeviceState parent_obj; 318 319 CPUState *cs; 320 qemu_irq output; 321 322 uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; 323 } XiveTCTX; 324 325 /* 326 * XIVE Router 327 */ 328 329 typedef struct XiveRouter { 330 SysBusDevice parent; 331 } XiveRouter; 332 333 #define TYPE_XIVE_ROUTER "xive-router" 334 #define XIVE_ROUTER(obj) \ 335 OBJECT_CHECK(XiveRouter, (obj), TYPE_XIVE_ROUTER) 336 #define XIVE_ROUTER_CLASS(klass) \ 337 OBJECT_CLASS_CHECK(XiveRouterClass, (klass), TYPE_XIVE_ROUTER) 338 #define XIVE_ROUTER_GET_CLASS(obj) \ 339 OBJECT_GET_CLASS(XiveRouterClass, (obj), TYPE_XIVE_ROUTER) 340 341 typedef struct XiveRouterClass { 342 SysBusDeviceClass parent; 343 344 /* XIVE table accessors */ 345 int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 346 XiveEAS *eas); 347 int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 348 XiveEND *end); 349 int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 350 XiveEND *end, uint8_t word_number); 351 int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 352 XiveNVT *nvt); 353 int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 354 XiveNVT *nvt, uint8_t word_number); 355 XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); 356 } XiveRouterClass; 357 358 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon); 359 360 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, 361 XiveEAS *eas); 362 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 363 XiveEND *end); 364 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, 365 XiveEND *end, uint8_t word_number); 366 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 367 XiveNVT *nvt); 368 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, 369 XiveNVT *nvt, uint8_t word_number); 370 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); 371 void xive_router_notify(XiveNotifier *xn, uint32_t lisn); 372 373 /* 374 * XIVE END ESBs 375 */ 376 377 #define TYPE_XIVE_END_SOURCE "xive-end-source" 378 #define XIVE_END_SOURCE(obj) \ 379 OBJECT_CHECK(XiveENDSource, (obj), TYPE_XIVE_END_SOURCE) 380 381 typedef struct XiveENDSource { 382 DeviceState parent; 383 384 uint32_t nr_ends; 385 uint8_t block_id; 386 387 /* ESB memory region */ 388 uint32_t esb_shift; 389 MemoryRegion esb_mmio; 390 391 XiveRouter *xrtr; 392 } XiveENDSource; 393 394 /* 395 * For legacy compatibility, the exceptions define up to 256 different 396 * priorities. P9 implements only 9 levels : 8 active levels [0 - 7] 397 * and the least favored level 0xFF. 398 */ 399 #define XIVE_PRIORITY_MAX 7 400 401 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon); 402 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon); 403 404 /* 405 * XIVE Thread Interrupt Management Aera (TIMA) 406 * 407 * This region gives access to the registers of the thread interrupt 408 * management context. It is four page wide, each page providing a 409 * different view of the registers. The page with the lower offset is 410 * the most privileged and gives access to the entire context. 411 */ 412 #define XIVE_TM_HW_PAGE 0x0 413 #define XIVE_TM_HV_PAGE 0x1 414 #define XIVE_TM_OS_PAGE 0x2 415 #define XIVE_TM_USER_PAGE 0x3 416 417 extern const MemoryRegionOps xive_tm_ops; 418 void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, 419 unsigned size); 420 uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size); 421 422 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); 423 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); 424 425 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) 426 { 427 return (nvt_blk << 19) | nvt_idx; 428 } 429 430 /* 431 * KVM XIVE device helpers 432 */ 433 434 void kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp); 435 void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val); 436 void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp); 437 void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp); 438 void kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp); 439 440 #endif /* PPC_XIVE_H */ 441