xref: /openbmc/qemu/include/hw/ppc/xive.h (revision 0274bd7b)
1 /*
2  * QEMU PowerPC XIVE interrupt controller model
3  *
4  *
5  * The POWER9 processor comes with a new interrupt controller, called
6  * XIVE as "eXternal Interrupt Virtualization Engine".
7  *
8  * = Overall architecture
9  *
10  *
11  *              XIVE Interrupt Controller
12  *              +------------------------------------+      IPIs
13  *              | +---------+ +---------+ +--------+ |    +-------+
14  *              | |VC       | |CQ       | |PC      |----> | CORES |
15  *              | |     esb | |         | |        |----> |       |
16  *              | |     eas | |  Bridge | |   tctx |----> |       |
17  *              | |SC   end | |         | |    nvt | |    |       |
18  *  +------+    | +---------+ +----+----+ +--------+ |    +-+-+-+-+
19  *  | RAM  |    +------------------|-----------------+      | | |
20  *  |      |                       |                        | | |
21  *  |      |                       |                        | | |
22  *  |      |  +--------------------v------------------------v-v-v--+    other
23  *  |      <--+                     Power Bus                      +--> chips
24  *  |  esb |  +---------+-----------------------+------------------+
25  *  |  eas |            |                       |
26  *  |  end |         +--|------+                |
27  *  |  nvt |       +----+----+ |           +----+----+
28  *  +------+       |SC       | |           |SC       |
29  *                 |         | |           |         |
30  *                 | PQ-bits | |           | PQ-bits |
31  *                 | local   |-+           |  in VC  |
32  *                 +---------+             +---------+
33  *                    PCIe                 NX,NPU,CAPI
34  *
35  *                   SC: Source Controller (aka. IVSE)
36  *                   VC: Virtualization Controller (aka. IVRE)
37  *                   PC: Presentation Controller (aka. IVPE)
38  *                   CQ: Common Queue (Bridge)
39  *
40  *              PQ-bits: 2 bits source state machine (P:pending Q:queued)
41  *                  esb: Event State Buffer (Array of PQ bits in an IVSE)
42  *                  eas: Event Assignment Structure
43  *                  end: Event Notification Descriptor
44  *                  nvt: Notification Virtual Target
45  *                 tctx: Thread interrupt Context
46  *
47  *
48  * The XIVE IC is composed of three sub-engines :
49  *
50  * - Interrupt Virtualization Source Engine (IVSE), or Source
51  *   Controller (SC). These are found in PCI PHBs, in the PSI host
52  *   bridge controller, but also inside the main controller for the
53  *   core IPIs and other sub-chips (NX, CAP, NPU) of the
54  *   chip/processor. They are configured to feed the IVRE with events.
55  *
56  * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
57  *   Controller (VC). Its job is to match an event source with an
58  *   Event Notification Descriptor (END).
59  *
60  * - Interrupt Virtualization Presentation Engine (IVPE) or
61  *   Presentation Controller (PC). It maintains the interrupt context
62  *   state of each thread and handles the delivery of the external
63  *   exception to the thread.
64  *
65  * In XIVE 1.0, the sub-engines used to be referred as:
66  *
67  *   SC     Source Controller
68  *   VC     Virtualization Controller
69  *   PC     Presentation Controller
70  *   CQ     Common Queue (PowerBUS Bridge)
71  *
72  *
73  * = XIVE internal tables
74  *
75  * Each of the sub-engines uses a set of tables to redirect exceptions
76  * from event sources to CPU threads.
77  *
78  *                                           +-------+
79  *   User or OS                              |  EQ   |
80  *       or                          +------>|entries|
81  *   Hypervisor                      |       |  ..   |
82  *     Memory                        |       +-------+
83  *                                   |           ^
84  *                                   |           |
85  *              +-------------------------------------------------+
86  *                                   |           |
87  *   Hypervisor      +------+    +---+--+    +---+--+   +------+
88  *     Memory        | ESB  |    | EAT  |    | ENDT |   | NVTT |
89  *    (skiboot)      +----+-+    +----+-+    +----+-+   +------+
90  *                     ^  |        ^  |        ^  |       ^
91  *                     |  |        |  |        |  |       |
92  *              +-------------------------------------------------+
93  *                     |  |        |  |        |  |       |
94  *                     |  |        |  |        |  |       |
95  *                +----|--|--------|--|--------|--|-+   +-|-----+    +------+
96  *                |    |  |        |  |        |  | |   | | tctx|    |Thread|
97  *   IPI or   --> |    +  v        +  v        +  v |---| +  .. |----->     |
98  *  HW events --> |                                 |   |       |    |      |
99  *    IVSE        |             IVRE                |   | IVPE  |    +------+
100  *                +---------------------------------+   +-------+
101  *
102  *
103  *
104  * The IVSE have a 2-bits state machine, P for pending and Q for queued,
105  * for each source that allows events to be triggered. They are stored in
106  * an Event State Buffer (ESB) array and can be controlled by MMIOs.
107  *
108  * If the event is let through, the IVRE looks up in the Event Assignment
109  * Structure (EAS) table for an Event Notification Descriptor (END)
110  * configured for the source. Each Event Notification Descriptor defines
111  * a notification path to a CPU and an in-memory Event Queue, in which
112  * will be enqueued an EQ data for the OS to pull.
113  *
114  * The IVPE determines if a Notification Virtual Target (NVT) can
115  * handle the event by scanning the thread contexts of the VCPUs
116  * dispatched on the processor HW threads. It maintains the state of
117  * the thread interrupt context (TCTX) of each thread in a NVT table.
118  *
119  * = Acronyms
120  *
121  *          Description                     In XIVE 1.0, used to be referred as
122  *
123  *   EAS    Event Assignment Structure      IVE   Interrupt Virt. Entry
124  *   EAT    Event Assignment Table          IVT   Interrupt Virt. Table
125  *   ENDT   Event Notif. Descriptor Table   EQDT  Event Queue Desc. Table
126  *   EQ     Event Queue                     same
127  *   ESB    Event State Buffer              SBE   State Bit Entry
128  *   NVT    Notif. Virtual Target           VPD   Virtual Processor Desc.
129  *   NVTT   Notif. Virtual Target Table     VPDT  Virtual Processor Desc. Table
130  *   TCTX   Thread interrupt Context
131  *
132  *
133  * Copyright (c) 2017-2018, IBM Corporation.
134  *
135  * This code is licensed under the GPL version 2 or later. See the
136  * COPYING file in the top-level directory.
137  *
138  */
139 
140 #ifndef PPC_XIVE_H
141 #define PPC_XIVE_H
142 
143 #include "sysemu/kvm.h"
144 #include "hw/sysbus.h"
145 #include "hw/ppc/xive_regs.h"
146 #include "qom/object.h"
147 
148 /*
149  * XIVE Notifier (Interface between Source and Router)
150  */
151 
152 typedef struct XiveNotifier XiveNotifier;
153 
154 #define TYPE_XIVE_NOTIFIER "xive-notifier"
155 #define XIVE_NOTIFIER(obj)                                     \
156     INTERFACE_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
157 typedef struct XiveNotifierClass XiveNotifierClass;
158 DECLARE_CLASS_CHECKERS(XiveNotifierClass, XIVE_NOTIFIER,
159                        TYPE_XIVE_NOTIFIER)
160 
161 struct XiveNotifierClass {
162     InterfaceClass parent;
163     void (*notify)(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
164 };
165 
166 /*
167  * XIVE Interrupt Source
168  */
169 
170 #define TYPE_XIVE_SOURCE "xive-source"
171 OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE)
172 
173 /*
174  * XIVE Interrupt Source characteristics, which define how the ESB are
175  * controlled.
176  */
177 #define XIVE_SRC_H_INT_ESB     0x1 /* ESB managed with hcall H_INT_ESB */
178 #define XIVE_SRC_STORE_EOI     0x2 /* Store EOI supported */
179 #define XIVE_SRC_PQ_DISABLE    0x4 /* Disable check on the PQ state bits */
180 
181 struct XiveSource {
182     DeviceState parent;
183 
184     /* IRQs */
185     uint32_t        nr_irqs;
186     unsigned long   *lsi_map;
187 
188     /* PQ bits and LSI assertion bit */
189     uint8_t         *status;
190     uint8_t         reset_pq; /* PQ state on reset */
191 
192     /* ESB memory region */
193     uint64_t        esb_flags;
194     uint32_t        esb_shift;
195     MemoryRegion    esb_mmio;
196     MemoryRegion    esb_mmio_emulated;
197 
198     /* KVM support */
199     void            *esb_mmap;
200     MemoryRegion    esb_mmio_kvm;
201 
202     XiveNotifier    *xive;
203 };
204 
205 /*
206  * ESB MMIO setting. Can be one page, for both source triggering and
207  * source management, or two different pages. See below for magic
208  * values.
209  */
210 #define XIVE_ESB_4K          12 /* PSI HB only */
211 #define XIVE_ESB_4K_2PAGE    13
212 #define XIVE_ESB_64K         16
213 #define XIVE_ESB_64K_2PAGE   17
214 
215 static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
216 {
217     return xsrc->esb_shift == XIVE_ESB_64K_2PAGE ||
218         xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
219 }
220 
221 static inline size_t xive_source_esb_len(XiveSource *xsrc)
222 {
223     return (1ull << xsrc->esb_shift) * xsrc->nr_irqs;
224 }
225 
226 /* The trigger page is always the first/even page */
227 static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno)
228 {
229     assert(srcno < xsrc->nr_irqs);
230     return (1ull << xsrc->esb_shift) * srcno;
231 }
232 
233 /* In a two pages ESB MMIO setting, the odd page is for management */
234 static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno)
235 {
236     hwaddr addr = xive_source_esb_page(xsrc, srcno);
237 
238     if (xive_source_esb_has_2page(xsrc)) {
239         addr += (1 << (xsrc->esb_shift - 1));
240     }
241 
242     return addr;
243 }
244 
245 /*
246  * Each interrupt source has a 2-bit state machine which can be
247  * controlled by MMIO. P indicates that an interrupt is pending (has
248  * been sent to a queue and is waiting for an EOI). Q indicates that
249  * the interrupt has been triggered while pending.
250  *
251  * This acts as a coalescing mechanism in order to guarantee that a
252  * given interrupt only occurs at most once in a queue.
253  *
254  * When doing an EOI, the Q bit will indicate if the interrupt
255  * needs to be re-triggered.
256  */
257 #define XIVE_STATUS_ASSERTED  0x4  /* Extra bit for LSI */
258 #define XIVE_ESB_VAL_P        0x2
259 #define XIVE_ESB_VAL_Q        0x1
260 
261 #define XIVE_ESB_RESET        0x0
262 #define XIVE_ESB_PENDING      XIVE_ESB_VAL_P
263 #define XIVE_ESB_QUEUED       (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
264 #define XIVE_ESB_OFF          XIVE_ESB_VAL_Q
265 
266 bool xive_esb_trigger(uint8_t *pq);
267 bool xive_esb_eoi(uint8_t *pq);
268 uint8_t xive_esb_set(uint8_t *pq, uint8_t value);
269 
270 /*
271  * "magic" Event State Buffer (ESB) MMIO offsets.
272  *
273  * The following offsets into the ESB MMIO allow to read or manipulate
274  * the PQ bits. They must be used with an 8-byte load instruction.
275  * They all return the previous state of the interrupt (atomically).
276  *
277  * Additionally, some ESB pages support doing an EOI via a store and
278  * some ESBs support doing a trigger via a separate trigger page.
279  */
280 #define XIVE_ESB_STORE_EOI      0x400 /* Store */
281 #define XIVE_ESB_LOAD_EOI       0x000 /* Load */
282 #define XIVE_ESB_GET            0x800 /* Load */
283 #define XIVE_ESB_INJECT         0x800 /* Store */
284 #define XIVE_ESB_SET_PQ_00      0xc00 /* Load */
285 #define XIVE_ESB_SET_PQ_01      0xd00 /* Load */
286 #define XIVE_ESB_SET_PQ_10      0xe00 /* Load */
287 #define XIVE_ESB_SET_PQ_11      0xf00 /* Load */
288 
289 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno);
290 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
291 
292 /*
293  * Source status helpers
294  */
295 static inline void xive_source_set_status(XiveSource *xsrc, uint32_t srcno,
296                                           uint8_t status, bool enable)
297 {
298     if (enable) {
299         xsrc->status[srcno] |= status;
300     } else {
301         xsrc->status[srcno] &= ~status;
302     }
303 }
304 
305 static inline void xive_source_set_asserted(XiveSource *xsrc, uint32_t srcno,
306                                             bool enable)
307 {
308     xive_source_set_status(xsrc, srcno, XIVE_STATUS_ASSERTED, enable);
309 }
310 
311 static inline bool xive_source_is_asserted(XiveSource *xsrc, uint32_t srcno)
312 {
313     return xsrc->status[srcno] & XIVE_STATUS_ASSERTED;
314 }
315 
316 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
317                                 Monitor *mon);
318 
319 static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
320 {
321     assert(srcno < xsrc->nr_irqs);
322     return test_bit(srcno, xsrc->lsi_map);
323 }
324 
325 static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno)
326 {
327     assert(srcno < xsrc->nr_irqs);
328     bitmap_set(xsrc->lsi_map, srcno, 1);
329 }
330 
331 void xive_source_set_irq(void *opaque, int srcno, int val);
332 
333 /*
334  * XIVE Thread interrupt Management (TM) context
335  */
336 
337 #define TYPE_XIVE_TCTX "xive-tctx"
338 OBJECT_DECLARE_SIMPLE_TYPE(XiveTCTX, XIVE_TCTX)
339 
340 /*
341  * XIVE Thread interrupt Management register rings :
342  *
343  *   QW-0  User       event-based exception state
344  *   QW-1  O/S        OS context for priority management, interrupt acks
345  *   QW-2  Pool       hypervisor pool context for virtual processors dispatched
346  *   QW-3  Physical   physical thread context and security context
347  */
348 #define XIVE_TM_RING_COUNT      4
349 #define XIVE_TM_RING_SIZE       0x10
350 
351 typedef struct XivePresenter XivePresenter;
352 
353 struct XiveTCTX {
354     DeviceState parent_obj;
355 
356     CPUState    *cs;
357     qemu_irq    hv_output;
358     qemu_irq    os_output;
359 
360     uint8_t     regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
361 
362     XivePresenter *xptr;
363 };
364 
365 static inline uint32_t xive_tctx_word2(uint8_t *ring)
366 {
367     return *((uint32_t *) &ring[TM_WORD2]);
368 }
369 
370 /*
371  * XIVE Router
372  */
373 typedef struct XiveFabric XiveFabric;
374 
375 struct XiveRouter {
376     SysBusDevice    parent;
377 
378     XiveFabric *xfb;
379 };
380 
381 #define TYPE_XIVE_ROUTER "xive-router"
382 OBJECT_DECLARE_TYPE(XiveRouter, XiveRouterClass,
383                     XIVE_ROUTER)
384 
385 struct XiveRouterClass {
386     SysBusDeviceClass parent;
387 
388     /* XIVE table accessors */
389     int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
390                    XiveEAS *eas);
391     int (*get_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
392                   uint8_t *pq);
393     int (*set_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
394                   uint8_t *pq);
395     int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
396                    XiveEND *end);
397     int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
398                      XiveEND *end, uint8_t word_number);
399     int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
400                    XiveNVT *nvt);
401     int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
402                      XiveNVT *nvt, uint8_t word_number);
403     uint8_t (*get_block_id)(XiveRouter *xrtr);
404     void (*end_notify)(XiveRouter *xrtr, XiveEAS *eas);
405 };
406 
407 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
408                         XiveEAS *eas);
409 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
410                         XiveEND *end);
411 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
412                           XiveEND *end, uint8_t word_number);
413 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
414                         XiveNVT *nvt);
415 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
416                           XiveNVT *nvt, uint8_t word_number);
417 void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
418 void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *eas);
419 
420 /*
421  * XIVE Presenter
422  */
423 
424 typedef struct XiveTCTXMatch {
425     XiveTCTX *tctx;
426     uint8_t ring;
427 } XiveTCTXMatch;
428 
429 #define TYPE_XIVE_PRESENTER "xive-presenter"
430 #define XIVE_PRESENTER(obj)                                     \
431     INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
432 typedef struct XivePresenterClass XivePresenterClass;
433 DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESENTER,
434                        TYPE_XIVE_PRESENTER)
435 
436 #define XIVE_PRESENTER_GEN1_TIMA_OS     0x1
437 
438 struct XivePresenterClass {
439     InterfaceClass parent;
440     int (*match_nvt)(XivePresenter *xptr, uint8_t format,
441                      uint8_t nvt_blk, uint32_t nvt_idx,
442                      bool cam_ignore, uint8_t priority,
443                      uint32_t logic_serv, XiveTCTXMatch *match);
444     bool (*in_kernel)(const XivePresenter *xptr);
445     uint32_t (*get_config)(XivePresenter *xptr);
446 };
447 
448 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
449                               uint8_t format,
450                               uint8_t nvt_blk, uint32_t nvt_idx,
451                               bool cam_ignore, uint32_t logic_serv);
452 bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
453                            uint8_t nvt_blk, uint32_t nvt_idx,
454                            bool cam_ignore, uint8_t priority,
455                            uint32_t logic_serv);
456 
457 /*
458  * XIVE Fabric (Interface between Interrupt Controller and Machine)
459  */
460 
461 #define TYPE_XIVE_FABRIC "xive-fabric"
462 #define XIVE_FABRIC(obj)                                     \
463     INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
464 typedef struct XiveFabricClass XiveFabricClass;
465 DECLARE_CLASS_CHECKERS(XiveFabricClass, XIVE_FABRIC,
466                        TYPE_XIVE_FABRIC)
467 
468 struct XiveFabricClass {
469     InterfaceClass parent;
470     int (*match_nvt)(XiveFabric *xfb, uint8_t format,
471                      uint8_t nvt_blk, uint32_t nvt_idx,
472                      bool cam_ignore, uint8_t priority,
473                      uint32_t logic_serv, XiveTCTXMatch *match);
474 };
475 
476 /*
477  * XIVE END ESBs
478  */
479 
480 #define TYPE_XIVE_END_SOURCE "xive-end-source"
481 OBJECT_DECLARE_SIMPLE_TYPE(XiveENDSource, XIVE_END_SOURCE)
482 
483 struct XiveENDSource {
484     DeviceState parent;
485 
486     uint32_t        nr_ends;
487 
488     /* ESB memory region */
489     uint32_t        esb_shift;
490     MemoryRegion    esb_mmio;
491 
492     XiveRouter      *xrtr;
493 };
494 
495 /*
496  * For legacy compatibility, the exceptions define up to 256 different
497  * priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
498  * and the least favored level 0xFF.
499  */
500 #define XIVE_PRIORITY_MAX  7
501 
502 /*
503  * Convert a priority number to an Interrupt Pending Buffer (IPB)
504  * register, which indicates a pending interrupt at the priority
505  * corresponding to the bit number
506  */
507 static inline uint8_t xive_priority_to_ipb(uint8_t priority)
508 {
509     return priority > XIVE_PRIORITY_MAX ?
510         0 : 1 << (XIVE_PRIORITY_MAX - priority);
511 }
512 
513 /*
514  * XIVE Thread Interrupt Management Aera (TIMA)
515  *
516  * This region gives access to the registers of the thread interrupt
517  * management context. It is four page wide, each page providing a
518  * different view of the registers. The page with the lower offset is
519  * the most privileged and gives access to the entire context.
520  */
521 #define XIVE_TM_HW_PAGE         0x0
522 #define XIVE_TM_HV_PAGE         0x1
523 #define XIVE_TM_OS_PAGE         0x2
524 #define XIVE_TM_USER_PAGE       0x3
525 
526 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
527                         uint64_t value, unsigned size);
528 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
529                            unsigned size);
530 
531 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
532 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
533 void xive_tctx_reset(XiveTCTX *tctx);
534 void xive_tctx_destroy(XiveTCTX *tctx);
535 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
536 void xive_tctx_reset_os_signal(XiveTCTX *tctx);
537 
538 /*
539  * KVM XIVE device helpers
540  */
541 
542 int kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp);
543 void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val);
544 int kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp);
545 int kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp);
546 int kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp);
547 int kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp);
548 
549 #endif /* PPC_XIVE_H */
550