1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #if !defined(__XICS_H__) 28 #define __XICS_H__ 29 30 #include "hw/sysbus.h" 31 32 #define TYPE_XICS "xics" 33 #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS) 34 35 #define XICS_IPI 0x2 36 #define XICS_BUID 0x1 37 #define XICS_IRQ_BASE (XICS_BUID << 12) 38 39 /* 40 * We currently only support one BUID which is our interrupt base 41 * (the kernel implementation supports more but we don't exploit 42 * that yet) 43 */ 44 typedef struct XICSState XICSState; 45 typedef struct ICPStateClass ICPStateClass; 46 typedef struct ICPState ICPState; 47 typedef struct ICSStateClass ICSStateClass; 48 typedef struct ICSState ICSState; 49 typedef struct ICSIRQState ICSIRQState; 50 51 struct XICSState { 52 /*< private >*/ 53 SysBusDevice parent_obj; 54 /*< public >*/ 55 uint32_t nr_servers; 56 uint32_t nr_irqs; 57 ICPState *ss; 58 ICSState *ics; 59 }; 60 61 #define TYPE_ICP "icp" 62 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) 63 64 #define ICP_CLASS(klass) \ 65 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) 66 #define ICP_GET_CLASS(obj) \ 67 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) 68 69 struct ICPStateClass { 70 DeviceClass parent_class; 71 72 void (*pre_save)(ICPState *s); 73 int (*post_load)(ICPState *s, int version_id); 74 }; 75 76 struct ICPState { 77 /*< private >*/ 78 DeviceState parent_obj; 79 /*< public >*/ 80 uint32_t xirr; 81 uint8_t pending_priority; 82 uint8_t mfrr; 83 qemu_irq output; 84 }; 85 86 #define TYPE_ICS "ics" 87 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) 88 89 #define ICS_CLASS(klass) \ 90 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS) 91 #define ICS_GET_CLASS(obj) \ 92 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS) 93 94 struct ICSStateClass { 95 DeviceClass parent_class; 96 97 void (*pre_save)(ICSState *s); 98 int (*post_load)(ICSState *s, int version_id); 99 }; 100 101 struct ICSState { 102 /*< private >*/ 103 DeviceState parent_obj; 104 /*< public >*/ 105 uint32_t nr_irqs; 106 uint32_t offset; 107 qemu_irq *qirqs; 108 bool *islsi; 109 ICSIRQState *irqs; 110 XICSState *icp; 111 }; 112 113 struct ICSIRQState { 114 uint32_t server; 115 uint8_t priority; 116 uint8_t saved_priority; 117 #define XICS_STATUS_ASSERTED 0x1 118 #define XICS_STATUS_SENT 0x2 119 #define XICS_STATUS_REJECTED 0x4 120 #define XICS_STATUS_MASKED_PENDING 0x8 121 uint8_t status; 122 }; 123 124 qemu_irq xics_get_qirq(XICSState *icp, int irq); 125 void xics_set_irq_type(XICSState *icp, int irq, bool lsi); 126 127 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); 128 129 #endif /* __XICS_H__ */ 130