1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #if !defined(__XICS_H__) 28 #define __XICS_H__ 29 30 #include "hw/sysbus.h" 31 32 #define TYPE_XICS_COMMON "xics-common" 33 #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON) 34 35 #define TYPE_XICS "xics" 36 #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS) 37 38 #define XICS_COMMON_CLASS(klass) \ 39 OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON) 40 #define XICS_CLASS(klass) \ 41 OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS) 42 #define XICS_COMMON_GET_CLASS(obj) \ 43 OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON) 44 #define XICS_GET_CLASS(obj) \ 45 OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS) 46 47 #define XICS_IPI 0x2 48 #define XICS_BUID 0x1 49 #define XICS_IRQ_BASE (XICS_BUID << 12) 50 51 /* 52 * We currently only support one BUID which is our interrupt base 53 * (the kernel implementation supports more but we don't exploit 54 * that yet) 55 */ 56 typedef struct XICSStateClass XICSStateClass; 57 typedef struct XICSState XICSState; 58 typedef struct ICPStateClass ICPStateClass; 59 typedef struct ICPState ICPState; 60 typedef struct ICSStateClass ICSStateClass; 61 typedef struct ICSState ICSState; 62 typedef struct ICSIRQState ICSIRQState; 63 64 struct XICSStateClass { 65 DeviceClass parent_class; 66 67 void (*set_nr_irqs)(XICSState *icp, uint32_t nr_irqs, Error **errp); 68 void (*set_nr_servers)(XICSState *icp, uint32_t nr_servers, Error **errp); 69 }; 70 71 struct XICSState { 72 /*< private >*/ 73 SysBusDevice parent_obj; 74 /*< public >*/ 75 uint32_t nr_servers; 76 uint32_t nr_irqs; 77 ICPState *ss; 78 ICSState *ics; 79 }; 80 81 #define TYPE_ICP "icp" 82 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) 83 84 #define ICP_CLASS(klass) \ 85 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) 86 #define ICP_GET_CLASS(obj) \ 87 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) 88 89 struct ICPStateClass { 90 DeviceClass parent_class; 91 92 void (*pre_save)(ICPState *s); 93 int (*post_load)(ICPState *s, int version_id); 94 }; 95 96 struct ICPState { 97 /*< private >*/ 98 DeviceState parent_obj; 99 /*< public >*/ 100 uint32_t xirr; 101 uint8_t pending_priority; 102 uint8_t mfrr; 103 qemu_irq output; 104 }; 105 106 #define TYPE_ICS "ics" 107 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) 108 109 #define ICS_CLASS(klass) \ 110 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS) 111 #define ICS_GET_CLASS(obj) \ 112 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS) 113 114 struct ICSStateClass { 115 DeviceClass parent_class; 116 117 void (*pre_save)(ICSState *s); 118 int (*post_load)(ICSState *s, int version_id); 119 }; 120 121 struct ICSState { 122 /*< private >*/ 123 DeviceState parent_obj; 124 /*< public >*/ 125 uint32_t nr_irqs; 126 uint32_t offset; 127 qemu_irq *qirqs; 128 bool *islsi; 129 ICSIRQState *irqs; 130 XICSState *icp; 131 }; 132 133 struct ICSIRQState { 134 uint32_t server; 135 uint8_t priority; 136 uint8_t saved_priority; 137 #define XICS_STATUS_ASSERTED 0x1 138 #define XICS_STATUS_SENT 0x2 139 #define XICS_STATUS_REJECTED 0x4 140 #define XICS_STATUS_MASKED_PENDING 0x8 141 uint8_t status; 142 }; 143 144 qemu_irq xics_get_qirq(XICSState *icp, int irq); 145 void xics_set_irq_type(XICSState *icp, int irq, bool lsi); 146 147 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); 148 149 #endif /* __XICS_H__ */ 150