1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #if !defined(__XICS_H__) 28 #define __XICS_H__ 29 30 #include "hw/sysbus.h" 31 32 #define TYPE_XICS "xics" 33 #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS) 34 35 #define XICS_IPI 0x2 36 #define XICS_BUID 0x1 37 #define XICS_IRQ_BASE (XICS_BUID << 12) 38 39 /* 40 * We currently only support one BUID which is our interrupt base 41 * (the kernel implementation supports more but we don't exploit 42 * that yet) 43 */ 44 typedef struct XICSState XICSState; 45 typedef struct ICPState ICPState; 46 typedef struct ICSState ICSState; 47 typedef struct ICSIRQState ICSIRQState; 48 49 struct XICSState { 50 /*< private >*/ 51 SysBusDevice parent_obj; 52 /*< public >*/ 53 uint32_t nr_servers; 54 uint32_t nr_irqs; 55 ICPState *ss; 56 ICSState *ics; 57 }; 58 59 #define TYPE_ICP "icp" 60 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) 61 62 struct ICPState { 63 /*< private >*/ 64 DeviceState parent_obj; 65 /*< public >*/ 66 uint32_t xirr; 67 uint8_t pending_priority; 68 uint8_t mfrr; 69 qemu_irq output; 70 }; 71 72 #define TYPE_ICS "ics" 73 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) 74 75 struct ICSState { 76 /*< private >*/ 77 DeviceState parent_obj; 78 /*< public >*/ 79 uint32_t nr_irqs; 80 uint32_t offset; 81 qemu_irq *qirqs; 82 bool *islsi; 83 ICSIRQState *irqs; 84 XICSState *icp; 85 }; 86 87 struct ICSIRQState { 88 uint32_t server; 89 uint8_t priority; 90 uint8_t saved_priority; 91 #define XICS_STATUS_ASSERTED 0x1 92 #define XICS_STATUS_SENT 0x2 93 #define XICS_STATUS_REJECTED 0x4 94 #define XICS_STATUS_MASKED_PENDING 0x8 95 uint8_t status; 96 }; 97 98 qemu_irq xics_get_qirq(XICSState *icp, int irq); 99 void xics_set_irq_type(XICSState *icp, int irq, bool lsi); 100 101 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); 102 103 #endif /* __XICS_H__ */ 104