1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PPC_SPAPR_XIVE_H 11 #define PPC_SPAPR_XIVE_H 12 13 #include "hw/ppc/spapr_irq.h" 14 #include "hw/ppc/xive.h" 15 16 #define TYPE_SPAPR_XIVE "spapr-xive" 17 #define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE) 18 19 typedef struct SpaprXive { 20 XiveRouter parent; 21 22 /* Internal interrupt source for IPIs and virtual devices */ 23 XiveSource source; 24 hwaddr vc_base; 25 26 /* END ESB MMIOs */ 27 XiveENDSource end_source; 28 hwaddr end_base; 29 30 /* DT */ 31 gchar *nodename; 32 33 /* Routing table */ 34 XiveEAS *eat; 35 uint32_t nr_irqs; 36 XiveEND *endt; 37 uint32_t nr_ends; 38 39 /* TIMA mapping address */ 40 hwaddr tm_base; 41 MemoryRegion tm_mmio; 42 43 /* KVM support */ 44 int fd; 45 void *tm_mmap; 46 MemoryRegion tm_mmio_kvm; 47 VMChangeStateEntry *change; 48 } SpaprXive; 49 50 /* 51 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 52 * to the controller block id value. It can nevertheless be changed 53 * for testing purpose. 54 */ 55 #define SPAPR_XIVE_BLOCK_ID 0x0 56 57 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon); 58 59 void spapr_xive_hcall_init(SpaprMachineState *spapr); 60 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable); 61 void spapr_xive_map_mmio(SpaprXive *xive); 62 63 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 64 uint32_t *out_server, uint8_t *out_prio); 65 66 /* 67 * KVM XIVE device helpers 68 */ 69 int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp); 70 void kvmppc_xive_disconnect(SpaprInterruptController *intc); 71 void kvmppc_xive_reset(SpaprXive *xive, Error **errp); 72 void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas, 73 Error **errp); 74 void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp); 75 uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset, 76 uint64_t data, bool write); 77 void kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk, 78 uint32_t end_idx, XiveEND *end, 79 Error **errp); 80 void kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk, 81 uint32_t end_idx, XiveEND *end, 82 Error **errp); 83 void kvmppc_xive_synchronize_state(SpaprXive *xive, Error **errp); 84 int kvmppc_xive_pre_save(SpaprXive *xive); 85 int kvmppc_xive_post_load(SpaprXive *xive, int version_id); 86 87 #endif /* PPC_SPAPR_XIVE_H */ 88