1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PPC_SPAPR_XIVE_H 11 #define PPC_SPAPR_XIVE_H 12 13 #include "hw/ppc/spapr_irq.h" 14 #include "hw/ppc/xive.h" 15 #include "sysemu/sysemu.h" 16 17 #define TYPE_SPAPR_XIVE "spapr-xive" 18 #define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE) 19 20 typedef struct SpaprXive { 21 XiveRouter parent; 22 23 /* Internal interrupt source for IPIs and virtual devices */ 24 XiveSource source; 25 hwaddr vc_base; 26 27 /* END ESB MMIOs */ 28 XiveENDSource end_source; 29 hwaddr end_base; 30 31 /* DT */ 32 gchar *nodename; 33 34 /* Routing table */ 35 XiveEAS *eat; 36 uint32_t nr_irqs; 37 XiveEND *endt; 38 uint32_t nr_ends; 39 40 /* TIMA mapping address */ 41 hwaddr tm_base; 42 MemoryRegion tm_mmio; 43 44 /* KVM support */ 45 int fd; 46 void *tm_mmap; 47 MemoryRegion tm_mmio_kvm; 48 VMChangeStateEntry *change; 49 } SpaprXive; 50 51 /* 52 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 53 * to the controller block id value. It can nevertheless be changed 54 * for testing purpose. 55 */ 56 #define SPAPR_XIVE_BLOCK_ID 0x0 57 58 bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi); 59 bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn); 60 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon); 61 int spapr_xive_post_load(SpaprXive *xive, int version_id); 62 63 void spapr_xive_hcall_init(SpaprMachineState *spapr); 64 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 65 uint32_t phandle); 66 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx); 67 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable); 68 void spapr_xive_map_mmio(SpaprXive *xive); 69 70 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 71 uint32_t *out_server, uint8_t *out_prio); 72 73 /* 74 * KVM XIVE device helpers 75 */ 76 void kvmppc_xive_connect(SpaprXive *xive, Error **errp); 77 void kvmppc_xive_disconnect(SpaprXive *xive, Error **errp); 78 void kvmppc_xive_reset(SpaprXive *xive, Error **errp); 79 void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas, 80 Error **errp); 81 void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp); 82 uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset, 83 uint64_t data, bool write); 84 void kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk, 85 uint32_t end_idx, XiveEND *end, 86 Error **errp); 87 void kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk, 88 uint32_t end_idx, XiveEND *end, 89 Error **errp); 90 void kvmppc_xive_synchronize_state(SpaprXive *xive, Error **errp); 91 int kvmppc_xive_pre_save(SpaprXive *xive); 92 int kvmppc_xive_post_load(SpaprXive *xive, int version_id); 93 94 #endif /* PPC_SPAPR_XIVE_H */ 95