1 /* 2 * QEMU PowerPC sPAPR IRQ backend definitions 3 * 4 * Copyright (c) 2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef HW_SPAPR_IRQ_H 11 #define HW_SPAPR_IRQ_H 12 13 #include "target/ppc/cpu-qom.h" 14 #include "qom/object.h" 15 16 /* 17 * The XIVE IRQ backend uses the same layout as the XICS backend but 18 * covers the full range of the IRQ number space. The IRQ numbers for 19 * the CPU IPIs are allocated at the bottom of this space, below 4K, 20 * to preserve compatibility with XICS which does not use that range. 21 */ 22 23 /* 24 * CPU IPI range (XIVE only) 25 */ 26 #define SPAPR_IRQ_IPI 0x0 27 #define SPAPR_IRQ_NR_IPIS 0x1000 28 29 /* 30 * IRQ range offsets per device type 31 */ 32 33 #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */ 34 #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000) 35 #define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001) 36 #define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */ 37 #define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */ 38 39 /* Offset of the dynamic range covered by the bitmap allocator */ 40 #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300) 41 42 #define SPAPR_NR_XIRQS 0x1000 43 44 struct SpaprMachineState; 45 46 typedef struct SpaprInterruptController SpaprInterruptController; 47 48 #define TYPE_SPAPR_INTC "spapr-interrupt-controller" 49 #define SPAPR_INTC(obj) \ 50 INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC) 51 typedef struct SpaprInterruptControllerClass SpaprInterruptControllerClass; 52 DECLARE_CLASS_CHECKERS(SpaprInterruptControllerClass, SPAPR_INTC, 53 TYPE_SPAPR_INTC) 54 55 struct SpaprInterruptControllerClass { 56 InterfaceClass parent; 57 58 int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers, 59 Error **errp); 60 void (*deactivate)(SpaprInterruptController *intc); 61 62 /* 63 * These methods will typically be called on all intcs, active and 64 * inactive 65 */ 66 int (*cpu_intc_create)(SpaprInterruptController *intc, 67 PowerPCCPU *cpu, Error **errp); 68 void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu); 69 void (*cpu_intc_destroy)(SpaprInterruptController *intc, PowerPCCPU *cpu); 70 int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi, 71 Error **errp); 72 void (*free_irq)(SpaprInterruptController *intc, int irq); 73 74 /* These methods should only be called on the active intc */ 75 void (*set_irq)(SpaprInterruptController *intc, int irq, int val); 76 void (*print_info)(SpaprInterruptController *intc, GString *buf); 77 void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers, 78 void *fdt, uint32_t phandle); 79 int (*post_load)(SpaprInterruptController *intc, int version_id); 80 }; 81 82 void spapr_irq_update_active_intc(struct SpaprMachineState *spapr); 83 84 int spapr_irq_cpu_intc_create(struct SpaprMachineState *spapr, 85 PowerPCCPU *cpu, Error **errp); 86 void spapr_irq_cpu_intc_reset(struct SpaprMachineState *spapr, PowerPCCPU *cpu); 87 void spapr_irq_cpu_intc_destroy(struct SpaprMachineState *spapr, PowerPCCPU *cpu); 88 void spapr_irq_print_info(struct SpaprMachineState *spapr, GString *buf); 89 void spapr_irq_dt(struct SpaprMachineState *spapr, uint32_t nr_servers, 90 void *fdt, uint32_t phandle); 91 92 uint32_t spapr_irq_nr_msis(struct SpaprMachineState *spapr); 93 int spapr_irq_msi_alloc(struct SpaprMachineState *spapr, uint32_t num, bool align, 94 Error **errp); 95 void spapr_irq_msi_free(struct SpaprMachineState *spapr, int irq, uint32_t num); 96 97 typedef struct SpaprIrq { 98 bool xics; 99 bool xive; 100 } SpaprIrq; 101 102 extern SpaprIrq spapr_irq_xics; 103 extern SpaprIrq spapr_irq_xics_legacy; 104 extern SpaprIrq spapr_irq_xive; 105 extern SpaprIrq spapr_irq_dual; 106 107 void spapr_irq_init(struct SpaprMachineState *spapr, Error **errp); 108 int spapr_irq_claim(struct SpaprMachineState *spapr, int irq, bool lsi, Error **errp); 109 void spapr_irq_free(struct SpaprMachineState *spapr, int irq, int num); 110 qemu_irq spapr_qirq(struct SpaprMachineState *spapr, int irq); 111 int spapr_irq_post_load(struct SpaprMachineState *spapr, int version_id); 112 void spapr_irq_reset(struct SpaprMachineState *spapr, Error **errp); 113 int spapr_irq_get_phandle(struct SpaprMachineState *spapr, void *fdt, Error **errp); 114 115 typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *, 116 uint32_t, Error **); 117 118 int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn, 119 SpaprInterruptController *intc, 120 uint32_t nr_servers, 121 Error **errp); 122 123 /* 124 * XICS legacy routines 125 */ 126 int spapr_irq_find(struct SpaprMachineState *spapr, int num, bool align, Error **errp); 127 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp) 128 129 #endif 130