1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 12 #include "hw/ppc/xics.h" /* For ICSState */ 13 #include "hw/ppc/spapr_tpm_proxy.h" 14 15 struct SpaprVioBus; 16 struct SpaprPhbState; 17 struct SpaprNvram; 18 19 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 20 typedef struct SpaprEventSource SpaprEventSource; 21 typedef struct SpaprPendingHpt SpaprPendingHpt; 22 23 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 24 #define SPAPR_ENTRY_POINT 0x100 25 26 #define SPAPR_TIMEBASE_FREQ 512000000ULL 27 28 #define TYPE_SPAPR_RTC "spapr-rtc" 29 30 #define SPAPR_RTC(obj) \ 31 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 32 33 typedef struct SpaprRtcState SpaprRtcState; 34 struct SpaprRtcState { 35 /*< private >*/ 36 DeviceState parent_obj; 37 int64_t ns_offset; 38 }; 39 40 typedef struct SpaprDimmState SpaprDimmState; 41 typedef struct SpaprMachineClass SpaprMachineClass; 42 43 #define TYPE_SPAPR_MACHINE "spapr-machine" 44 #define SPAPR_MACHINE(obj) \ 45 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 46 #define SPAPR_MACHINE_GET_CLASS(obj) \ 47 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 48 #define SPAPR_MACHINE_CLASS(klass) \ 49 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 50 51 typedef enum { 52 SPAPR_RESIZE_HPT_DEFAULT = 0, 53 SPAPR_RESIZE_HPT_DISABLED, 54 SPAPR_RESIZE_HPT_ENABLED, 55 SPAPR_RESIZE_HPT_REQUIRED, 56 } SpaprResizeHpt; 57 58 /** 59 * Capabilities 60 */ 61 62 /* Hardware Transactional Memory */ 63 #define SPAPR_CAP_HTM 0x00 64 /* Vector Scalar Extensions */ 65 #define SPAPR_CAP_VSX 0x01 66 /* Decimal Floating Point */ 67 #define SPAPR_CAP_DFP 0x02 68 /* Cache Flush on Privilege Change */ 69 #define SPAPR_CAP_CFPC 0x03 70 /* Speculation Barrier Bounds Checking */ 71 #define SPAPR_CAP_SBBC 0x04 72 /* Indirect Branch Serialisation */ 73 #define SPAPR_CAP_IBS 0x05 74 /* HPT Maximum Page Size (encoded as a shift) */ 75 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 76 /* Nested KVM-HV */ 77 #define SPAPR_CAP_NESTED_KVM_HV 0x07 78 /* Large Decrementer */ 79 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 80 /* Count Cache Flush Assist HW Instruction */ 81 #define SPAPR_CAP_CCF_ASSIST 0x09 82 /* Num Caps */ 83 #define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) 84 85 /* 86 * Capability Values 87 */ 88 /* Bool Caps */ 89 #define SPAPR_CAP_OFF 0x00 90 #define SPAPR_CAP_ON 0x01 91 92 /* Custom Caps */ 93 94 /* Generic */ 95 #define SPAPR_CAP_BROKEN 0x00 96 #define SPAPR_CAP_WORKAROUND 0x01 97 #define SPAPR_CAP_FIXED 0x02 98 /* SPAPR_CAP_IBS (cap-ibs) */ 99 #define SPAPR_CAP_FIXED_IBS 0x02 100 #define SPAPR_CAP_FIXED_CCD 0x03 101 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 102 103 typedef struct SpaprCapabilities SpaprCapabilities; 104 struct SpaprCapabilities { 105 uint8_t caps[SPAPR_CAP_NUM]; 106 }; 107 108 /** 109 * SpaprMachineClass: 110 */ 111 struct SpaprMachineClass { 112 /*< private >*/ 113 MachineClass parent_class; 114 115 /*< public >*/ 116 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 117 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 118 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 119 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 120 bool pre_2_10_has_unused_icps; 121 bool legacy_irq_allocation; 122 bool broken_host_serial_model; /* present real host info to the guest */ 123 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 124 bool linux_pci_probe; 125 126 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 127 uint64_t *buid, hwaddr *pio, 128 hwaddr *mmio32, hwaddr *mmio64, 129 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 130 hwaddr *nv2atsd, Error **errp); 131 SpaprResizeHpt resize_hpt_default; 132 SpaprCapabilities default_caps; 133 SpaprIrq *irq; 134 }; 135 136 /** 137 * SpaprMachineState: 138 */ 139 struct SpaprMachineState { 140 /*< private >*/ 141 MachineState parent_obj; 142 143 struct SpaprVioBus *vio_bus; 144 QLIST_HEAD(, SpaprPhbState) phbs; 145 struct SpaprNvram *nvram; 146 ICSState *ics; 147 SpaprRtcState rtc; 148 149 SpaprResizeHpt resize_hpt; 150 void *htab; 151 uint32_t htab_shift; 152 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 153 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 154 155 hwaddr rma_size; 156 int vrma_adjust; 157 ssize_t rtas_size; 158 void *rtas_blob; 159 uint32_t fdt_size; 160 uint32_t fdt_initial_size; 161 void *fdt_blob; 162 long kernel_size; 163 bool kernel_le; 164 uint32_t initrd_base; 165 long initrd_size; 166 uint64_t rtc_offset; /* Now used only during incoming migration */ 167 struct PPCTimebase tb; 168 bool has_graphics; 169 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 170 171 Notifier epow_notifier; 172 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 173 bool use_hotplug_event_source; 174 SpaprEventSource *event_sources; 175 176 /* ibm,client-architecture-support option negotiation */ 177 bool cas_reboot; 178 bool cas_legacy_guest_workaround; 179 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 180 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 181 uint32_t max_compat_pvr; 182 183 /* Migration state */ 184 int htab_save_index; 185 bool htab_first_pass; 186 int htab_fd; 187 188 /* Pending DIMM unplug cache. It is populated when a LMB 189 * unplug starts. It can be regenerated if a migration 190 * occurs during the unplug process. */ 191 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 192 193 /*< public >*/ 194 char *kvm_type; 195 char *host_model; 196 char *host_serial; 197 198 int32_t irq_map_nr; 199 unsigned long *irq_map; 200 SpaprXive *xive; 201 SpaprIrq *irq; 202 qemu_irq *qirqs; 203 204 bool cmd_line_caps[SPAPR_CAP_NUM]; 205 SpaprCapabilities def, eff, mig; 206 207 unsigned gpu_numa_id; 208 SpaprTpmProxy *tpm_proxy; 209 }; 210 211 #define H_SUCCESS 0 212 #define H_BUSY 1 /* Hardware busy -- retry later */ 213 #define H_CLOSED 2 /* Resource closed */ 214 #define H_NOT_AVAILABLE 3 215 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 216 #define H_PARTIAL 5 217 #define H_IN_PROGRESS 14 /* Kind of like busy */ 218 #define H_PAGE_REGISTERED 15 219 #define H_PARTIAL_STORE 16 220 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 221 #define H_CONTINUE 18 /* Returned from H_Join on success */ 222 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 223 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 224 is a good time to retry */ 225 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 226 is a good time to retry */ 227 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 228 is a good time to retry */ 229 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 230 is a good time to retry */ 231 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 232 is a good time to retry */ 233 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 234 is a good time to retry */ 235 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 236 #define H_HARDWARE -1 /* Hardware error */ 237 #define H_FUNCTION -2 /* Function not supported */ 238 #define H_PRIVILEGE -3 /* Caller not privileged */ 239 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 240 #define H_BAD_MODE -5 /* Illegal msr value */ 241 #define H_PTEG_FULL -6 /* PTEG is full */ 242 #define H_NOT_FOUND -7 /* PTE was not found" */ 243 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 244 #define H_NO_MEM -9 245 #define H_AUTHORITY -10 246 #define H_PERMISSION -11 247 #define H_DROPPED -12 248 #define H_SOURCE_PARM -13 249 #define H_DEST_PARM -14 250 #define H_REMOTE_PARM -15 251 #define H_RESOURCE -16 252 #define H_ADAPTER_PARM -17 253 #define H_RH_PARM -18 254 #define H_RCQ_PARM -19 255 #define H_SCQ_PARM -20 256 #define H_EQ_PARM -21 257 #define H_RT_PARM -22 258 #define H_ST_PARM -23 259 #define H_SIGT_PARM -24 260 #define H_TOKEN_PARM -25 261 #define H_MLENGTH_PARM -27 262 #define H_MEM_PARM -28 263 #define H_MEM_ACCESS_PARM -29 264 #define H_ATTR_PARM -30 265 #define H_PORT_PARM -31 266 #define H_MCG_PARM -32 267 #define H_VL_PARM -33 268 #define H_TSIZE_PARM -34 269 #define H_TRACE_PARM -35 270 271 #define H_MASK_PARM -37 272 #define H_MCG_FULL -38 273 #define H_ALIAS_EXIST -39 274 #define H_P_COUNTER -40 275 #define H_TABLE_FULL -41 276 #define H_ALT_TABLE -42 277 #define H_MR_CONDITION -43 278 #define H_NOT_ENOUGH_RESOURCES -44 279 #define H_R_STATE -45 280 #define H_RESCINDEND -46 281 #define H_P2 -55 282 #define H_P3 -56 283 #define H_P4 -57 284 #define H_P5 -58 285 #define H_P6 -59 286 #define H_P7 -60 287 #define H_P8 -61 288 #define H_P9 -62 289 #define H_UNSUPPORTED_FLAG -256 290 #define H_MULTI_THREADS_ACTIVE -9005 291 292 293 /* Long Busy is a condition that can be returned by the firmware 294 * when a call cannot be completed now, but the identical call 295 * should be retried later. This prevents calls blocking in the 296 * firmware for long periods of time. Annoyingly the firmware can return 297 * a range of return codes, hinting at how long we should wait before 298 * retrying. If you don't care for the hint, the macro below is a good 299 * way to check for the long_busy return codes 300 */ 301 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 302 && (x <= H_LONG_BUSY_END_RANGE)) 303 304 /* Flags */ 305 #define H_LARGE_PAGE (1ULL<<(63-16)) 306 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 307 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 308 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 309 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 310 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 311 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 312 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 313 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 314 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 315 #define H_ANDCOND (1ULL<<(63-33)) 316 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 317 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 318 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 319 #define H_COPY_PAGE (1ULL<<(63-49)) 320 #define H_N (1ULL<<(63-61)) 321 #define H_PP1 (1ULL<<(63-62)) 322 #define H_PP2 (1ULL<<(63-63)) 323 324 /* Values for 2nd argument to H_SET_MODE */ 325 #define H_SET_MODE_RESOURCE_SET_CIABR 1 326 #define H_SET_MODE_RESOURCE_SET_DAWR 2 327 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 328 #define H_SET_MODE_RESOURCE_LE 4 329 330 /* Flags for H_SET_MODE_RESOURCE_LE */ 331 #define H_SET_MODE_ENDIAN_BIG 0 332 #define H_SET_MODE_ENDIAN_LITTLE 1 333 334 /* VASI States */ 335 #define H_VASI_INVALID 0 336 #define H_VASI_ENABLED 1 337 #define H_VASI_ABORTED 2 338 #define H_VASI_SUSPENDING 3 339 #define H_VASI_SUSPENDED 4 340 #define H_VASI_RESUMED 5 341 #define H_VASI_COMPLETED 6 342 343 /* DABRX flags */ 344 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 345 #define H_DABRX_KERNEL (1ULL<<(63-62)) 346 #define H_DABRX_USER (1ULL<<(63-63)) 347 348 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 349 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 350 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 351 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 352 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 353 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 354 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 355 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 356 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 357 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 358 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 359 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 360 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 361 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 362 363 /* Each control block has to be on a 4K boundary */ 364 #define H_CB_ALIGNMENT 4096 365 366 /* pSeries hypervisor opcodes */ 367 #define H_REMOVE 0x04 368 #define H_ENTER 0x08 369 #define H_READ 0x0c 370 #define H_CLEAR_MOD 0x10 371 #define H_CLEAR_REF 0x14 372 #define H_PROTECT 0x18 373 #define H_GET_TCE 0x1c 374 #define H_PUT_TCE 0x20 375 #define H_SET_SPRG0 0x24 376 #define H_SET_DABR 0x28 377 #define H_PAGE_INIT 0x2c 378 #define H_SET_ASR 0x30 379 #define H_ASR_ON 0x34 380 #define H_ASR_OFF 0x38 381 #define H_LOGICAL_CI_LOAD 0x3c 382 #define H_LOGICAL_CI_STORE 0x40 383 #define H_LOGICAL_CACHE_LOAD 0x44 384 #define H_LOGICAL_CACHE_STORE 0x48 385 #define H_LOGICAL_ICBI 0x4c 386 #define H_LOGICAL_DCBF 0x50 387 #define H_GET_TERM_CHAR 0x54 388 #define H_PUT_TERM_CHAR 0x58 389 #define H_REAL_TO_LOGICAL 0x5c 390 #define H_HYPERVISOR_DATA 0x60 391 #define H_EOI 0x64 392 #define H_CPPR 0x68 393 #define H_IPI 0x6c 394 #define H_IPOLL 0x70 395 #define H_XIRR 0x74 396 #define H_PERFMON 0x7c 397 #define H_MIGRATE_DMA 0x78 398 #define H_REGISTER_VPA 0xDC 399 #define H_CEDE 0xE0 400 #define H_CONFER 0xE4 401 #define H_PROD 0xE8 402 #define H_GET_PPP 0xEC 403 #define H_SET_PPP 0xF0 404 #define H_PURR 0xF4 405 #define H_PIC 0xF8 406 #define H_REG_CRQ 0xFC 407 #define H_FREE_CRQ 0x100 408 #define H_VIO_SIGNAL 0x104 409 #define H_SEND_CRQ 0x108 410 #define H_COPY_RDMA 0x110 411 #define H_REGISTER_LOGICAL_LAN 0x114 412 #define H_FREE_LOGICAL_LAN 0x118 413 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 414 #define H_SEND_LOGICAL_LAN 0x120 415 #define H_BULK_REMOVE 0x124 416 #define H_MULTICAST_CTRL 0x130 417 #define H_SET_XDABR 0x134 418 #define H_STUFF_TCE 0x138 419 #define H_PUT_TCE_INDIRECT 0x13C 420 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 421 #define H_VTERM_PARTNER_INFO 0x150 422 #define H_REGISTER_VTERM 0x154 423 #define H_FREE_VTERM 0x158 424 #define H_RESET_EVENTS 0x15C 425 #define H_ALLOC_RESOURCE 0x160 426 #define H_FREE_RESOURCE 0x164 427 #define H_MODIFY_QP 0x168 428 #define H_QUERY_QP 0x16C 429 #define H_REREGISTER_PMR 0x170 430 #define H_REGISTER_SMR 0x174 431 #define H_QUERY_MR 0x178 432 #define H_QUERY_MW 0x17C 433 #define H_QUERY_HCA 0x180 434 #define H_QUERY_PORT 0x184 435 #define H_MODIFY_PORT 0x188 436 #define H_DEFINE_AQP1 0x18C 437 #define H_GET_TRACE_BUFFER 0x190 438 #define H_DEFINE_AQP0 0x194 439 #define H_RESIZE_MR 0x198 440 #define H_ATTACH_MCQP 0x19C 441 #define H_DETACH_MCQP 0x1A0 442 #define H_CREATE_RPT 0x1A4 443 #define H_REMOVE_RPT 0x1A8 444 #define H_REGISTER_RPAGES 0x1AC 445 #define H_DISABLE_AND_GETC 0x1B0 446 #define H_ERROR_DATA 0x1B4 447 #define H_GET_HCA_INFO 0x1B8 448 #define H_GET_PERF_COUNT 0x1BC 449 #define H_MANAGE_TRACE 0x1C0 450 #define H_GET_CPU_CHARACTERISTICS 0x1C8 451 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 452 #define H_QUERY_INT_STATE 0x1E4 453 #define H_POLL_PENDING 0x1D8 454 #define H_ILLAN_ATTRIBUTES 0x244 455 #define H_MODIFY_HEA_QP 0x250 456 #define H_QUERY_HEA_QP 0x254 457 #define H_QUERY_HEA 0x258 458 #define H_QUERY_HEA_PORT 0x25C 459 #define H_MODIFY_HEA_PORT 0x260 460 #define H_REG_BCMC 0x264 461 #define H_DEREG_BCMC 0x268 462 #define H_REGISTER_HEA_RPAGES 0x26C 463 #define H_DISABLE_AND_GET_HEA 0x270 464 #define H_GET_HEA_INFO 0x274 465 #define H_ALLOC_HEA_RESOURCE 0x278 466 #define H_ADD_CONN 0x284 467 #define H_DEL_CONN 0x288 468 #define H_JOIN 0x298 469 #define H_VASI_STATE 0x2A4 470 #define H_ENABLE_CRQ 0x2B0 471 #define H_GET_EM_PARMS 0x2B8 472 #define H_SET_MPP 0x2D0 473 #define H_GET_MPP 0x2D4 474 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 475 #define H_XIRR_X 0x2FC 476 #define H_RANDOM 0x300 477 #define H_SET_MODE 0x31C 478 #define H_RESIZE_HPT_PREPARE 0x36C 479 #define H_RESIZE_HPT_COMMIT 0x370 480 #define H_CLEAN_SLB 0x374 481 #define H_INVALIDATE_PID 0x378 482 #define H_REGISTER_PROC_TBL 0x37C 483 #define H_SIGNAL_SYS_RESET 0x380 484 485 #define H_INT_GET_SOURCE_INFO 0x3A8 486 #define H_INT_SET_SOURCE_CONFIG 0x3AC 487 #define H_INT_GET_SOURCE_CONFIG 0x3B0 488 #define H_INT_GET_QUEUE_INFO 0x3B4 489 #define H_INT_SET_QUEUE_CONFIG 0x3B8 490 #define H_INT_GET_QUEUE_CONFIG 0x3BC 491 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 492 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 493 #define H_INT_ESB 0x3C8 494 #define H_INT_SYNC 0x3CC 495 #define H_INT_RESET 0x3D0 496 497 #define MAX_HCALL_OPCODE H_INT_RESET 498 499 /* The hcalls above are standardized in PAPR and implemented by pHyp 500 * as well. 501 * 502 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 503 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 504 * for "platform-specific" hcalls. 505 */ 506 #define KVMPPC_HCALL_BASE 0xf000 507 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 508 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 509 /* Client Architecture support */ 510 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 511 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 512 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 513 514 /* 515 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 516 * Secure VM mode via an Ultravisor / Protected Execution Facility 517 */ 518 #define SVM_HCALL_BASE 0xEF00 519 #define SVM_H_TPM_COMM 0xEF10 520 #define SVM_HCALL_MAX SVM_H_TPM_COMM 521 522 523 typedef struct SpaprDeviceTreeUpdateHeader { 524 uint32_t version_id; 525 } SpaprDeviceTreeUpdateHeader; 526 527 #define hcall_dprintf(fmt, ...) \ 528 do { \ 529 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 530 } while (0) 531 532 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 533 target_ulong opcode, 534 target_ulong *args); 535 536 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 537 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 538 target_ulong *args); 539 540 /* Virtual Processor Area structure constants */ 541 #define VPA_MIN_SIZE 640 542 #define VPA_SIZE_OFFSET 0x4 543 #define VPA_SHARED_PROC_OFFSET 0x9 544 #define VPA_SHARED_PROC_VAL 0x2 545 #define VPA_DISPATCH_COUNTER 0x100 546 547 /* ibm,set-eeh-option */ 548 #define RTAS_EEH_DISABLE 0 549 #define RTAS_EEH_ENABLE 1 550 #define RTAS_EEH_THAW_IO 2 551 #define RTAS_EEH_THAW_DMA 3 552 553 /* ibm,get-config-addr-info2 */ 554 #define RTAS_GET_PE_ADDR 0 555 #define RTAS_GET_PE_MODE 1 556 #define RTAS_PE_MODE_NONE 0 557 #define RTAS_PE_MODE_NOT_SHARED 1 558 #define RTAS_PE_MODE_SHARED 2 559 560 /* ibm,read-slot-reset-state2 */ 561 #define RTAS_EEH_PE_STATE_NORMAL 0 562 #define RTAS_EEH_PE_STATE_RESET 1 563 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 564 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 565 #define RTAS_EEH_PE_STATE_UNAVAIL 5 566 #define RTAS_EEH_NOT_SUPPORT 0 567 #define RTAS_EEH_SUPPORT 1 568 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 569 #define RTAS_EEH_PE_RECOVER_INFO 0 570 571 /* ibm,set-slot-reset */ 572 #define RTAS_SLOT_RESET_DEACTIVATE 0 573 #define RTAS_SLOT_RESET_HOT 1 574 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 575 576 /* ibm,slot-error-detail */ 577 #define RTAS_SLOT_TEMP_ERR_LOG 1 578 #define RTAS_SLOT_PERM_ERR_LOG 2 579 580 /* RTAS return codes */ 581 #define RTAS_OUT_SUCCESS 0 582 #define RTAS_OUT_NO_ERRORS_FOUND 1 583 #define RTAS_OUT_HW_ERROR -1 584 #define RTAS_OUT_BUSY -2 585 #define RTAS_OUT_PARAM_ERROR -3 586 #define RTAS_OUT_NOT_SUPPORTED -3 587 #define RTAS_OUT_NO_SUCH_INDICATOR -3 588 #define RTAS_OUT_NOT_AUTHORIZED -9002 589 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 590 591 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 592 #define RTAS_DDW_PGSIZE_4K 0x01 593 #define RTAS_DDW_PGSIZE_64K 0x02 594 #define RTAS_DDW_PGSIZE_16M 0x04 595 #define RTAS_DDW_PGSIZE_32M 0x08 596 #define RTAS_DDW_PGSIZE_64M 0x10 597 #define RTAS_DDW_PGSIZE_128M 0x20 598 #define RTAS_DDW_PGSIZE_256M 0x40 599 #define RTAS_DDW_PGSIZE_16G 0x80 600 601 /* RTAS tokens */ 602 #define RTAS_TOKEN_BASE 0x2000 603 604 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 605 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 606 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 607 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 608 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 609 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 610 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 611 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 612 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 613 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 614 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 615 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 616 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 617 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 618 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 619 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 620 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 621 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 622 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 623 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 624 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 625 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 626 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 627 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 628 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 629 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 630 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 631 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 632 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 633 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 634 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 635 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 636 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 637 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 638 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 639 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 640 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 641 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 642 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 643 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 644 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 645 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 646 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 647 648 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2B) 649 650 /* RTAS ibm,get-system-parameter token values */ 651 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 652 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 653 #define RTAS_SYSPARM_UUID 48 654 655 /* RTAS indicator/sensor types 656 * 657 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 658 * 659 * NOTE: currently only DR-related sensors are implemented here 660 */ 661 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 662 #define RTAS_SENSOR_TYPE_DR 9002 663 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 664 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 665 666 /* Possible values for the platform-processor-diagnostics-run-mode parameter 667 * of the RTAS ibm,get-system-parameter call. 668 */ 669 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 670 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 671 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 672 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 673 674 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 675 { 676 return addr & ~0xF000000000000000ULL; 677 } 678 679 static inline uint32_t rtas_ld(target_ulong phys, int n) 680 { 681 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 682 } 683 684 static inline uint64_t rtas_ldq(target_ulong phys, int n) 685 { 686 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 687 } 688 689 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 690 { 691 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 692 } 693 694 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 695 uint32_t token, 696 uint32_t nargs, target_ulong args, 697 uint32_t nret, target_ulong rets); 698 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 699 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 700 uint32_t token, uint32_t nargs, target_ulong args, 701 uint32_t nret, target_ulong rets); 702 void spapr_dt_rtas_tokens(void *fdt, int rtas); 703 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 704 705 #define SPAPR_TCE_PAGE_SHIFT 12 706 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 707 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 708 709 #define SPAPR_VIO_BASE_LIOBN 0x00000000 710 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 711 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 712 (0x80000000 | ((phb_index) << 8) | (window_num)) 713 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 714 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 715 716 #define RTAS_ERROR_LOG_MAX 2048 717 718 #define RTAS_EVENT_SCAN_RATE 1 719 720 /* This helper should be used to encode interrupt specifiers when the related 721 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 722 * VIO devices, RTAS event sources and PHBs). 723 */ 724 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 725 { 726 intspec[0] = cpu_to_be32(irq); 727 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 728 } 729 730 typedef struct SpaprTceTable SpaprTceTable; 731 732 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 733 #define SPAPR_TCE_TABLE(obj) \ 734 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 735 736 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 737 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 738 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 739 740 struct SpaprTceTable { 741 DeviceState parent; 742 uint32_t liobn; 743 uint32_t nb_table; 744 uint64_t bus_offset; 745 uint32_t page_shift; 746 uint64_t *table; 747 uint32_t mig_nb_table; 748 uint64_t *mig_table; 749 bool bypass; 750 bool need_vfio; 751 bool skipping_replay; 752 int fd; 753 MemoryRegion root; 754 IOMMUMemoryRegion iommu; 755 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 756 QLIST_ENTRY(SpaprTceTable) list; 757 }; 758 759 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 760 761 struct SpaprEventLogEntry { 762 uint32_t summary; 763 uint32_t extended_length; 764 void *extended_log; 765 QTAILQ_ENTRY(SpaprEventLogEntry) next; 766 }; 767 768 void spapr_events_init(SpaprMachineState *sm); 769 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 770 int spapr_h_cas_compose_response(SpaprMachineState *sm, 771 target_ulong addr, target_ulong size, 772 SpaprOptionVector *ov5_updates); 773 void close_htab_fd(SpaprMachineState *spapr); 774 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr); 775 void spapr_free_hpt(SpaprMachineState *spapr); 776 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 777 void spapr_tce_table_enable(SpaprTceTable *tcet, 778 uint32_t page_shift, uint64_t bus_offset, 779 uint32_t nb_table); 780 void spapr_tce_table_disable(SpaprTceTable *tcet); 781 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 782 783 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 784 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 785 uint32_t liobn, uint64_t window, uint32_t size); 786 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 787 SpaprTceTable *tcet); 788 void spapr_pci_switch_vga(bool big_endian); 789 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 790 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 791 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 792 uint32_t count); 793 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 794 uint32_t count); 795 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 796 uint32_t count, uint32_t index); 797 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 798 uint32_t count, uint32_t index); 799 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 800 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 801 Error **errp); 802 void spapr_clear_pending_events(SpaprMachineState *spapr); 803 int spapr_max_server_number(SpaprMachineState *spapr); 804 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 805 uint64_t pte0, uint64_t pte1); 806 807 /* DRC callbacks. */ 808 void spapr_core_release(DeviceState *dev); 809 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 810 void *fdt, int *fdt_start_offset, Error **errp); 811 void spapr_lmb_release(DeviceState *dev); 812 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 813 void *fdt, int *fdt_start_offset, Error **errp); 814 void spapr_phb_release(DeviceState *dev); 815 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 816 void *fdt, int *fdt_start_offset, Error **errp); 817 818 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 819 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 820 821 #define TYPE_SPAPR_RNG "spapr-rng" 822 823 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 824 825 /* 826 * This defines the maximum number of DIMM slots we can have for sPAPR 827 * guest. This is not defined by sPAPR but we are defining it to 32 slots 828 * based on default number of slots provided by PowerPC kernel. 829 */ 830 #define SPAPR_MAX_RAM_SLOTS 32 831 832 /* 1GB alignment for hotplug memory region */ 833 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 834 835 /* 836 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 837 * property under ibm,dynamic-reconfiguration-memory node. 838 */ 839 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 840 841 /* 842 * Defines for flag value in ibm,dynamic-memory property under 843 * ibm,dynamic-reconfiguration-memory node. 844 */ 845 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 846 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 847 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 848 849 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 850 851 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 852 853 int spapr_get_vcpu_id(PowerPCCPU *cpu); 854 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 855 PowerPCCPU *spapr_find_cpu(int vcpu_id); 856 857 int spapr_caps_pre_load(void *opaque); 858 int spapr_caps_pre_save(void *opaque); 859 860 /* 861 * Handling of optional capabilities 862 */ 863 extern const VMStateDescription vmstate_spapr_cap_htm; 864 extern const VMStateDescription vmstate_spapr_cap_vsx; 865 extern const VMStateDescription vmstate_spapr_cap_dfp; 866 extern const VMStateDescription vmstate_spapr_cap_cfpc; 867 extern const VMStateDescription vmstate_spapr_cap_sbbc; 868 extern const VMStateDescription vmstate_spapr_cap_ibs; 869 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 870 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 871 extern const VMStateDescription vmstate_spapr_cap_large_decr; 872 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 873 874 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 875 { 876 return spapr->eff.caps[cap]; 877 } 878 879 void spapr_caps_init(SpaprMachineState *spapr); 880 void spapr_caps_apply(SpaprMachineState *spapr); 881 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 882 void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp); 883 int spapr_caps_post_migration(SpaprMachineState *spapr); 884 885 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 886 Error **errp); 887 /* 888 * XIVE definitions 889 */ 890 #define SPAPR_OV5_XIVE_LEGACY 0x0 891 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 892 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 893 894 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 895 #endif /* HW_SPAPR_H */ 896