1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 11 struct VIOsPAPRBus; 12 struct sPAPRPHBState; 13 struct sPAPRNVRAM; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 typedef struct sPAPREventSource sPAPREventSource; 16 17 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 18 #define SPAPR_ENTRY_POINT 0x100 19 20 #define SPAPR_TIMEBASE_FREQ 512000000ULL 21 22 #define TYPE_SPAPR_RTC "spapr-rtc" 23 24 #define SPAPR_RTC(obj) \ 25 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 26 27 typedef struct sPAPRRTCState sPAPRRTCState; 28 struct sPAPRRTCState { 29 /*< private >*/ 30 DeviceState parent_obj; 31 int64_t ns_offset; 32 }; 33 34 typedef struct sPAPRDIMMState sPAPRDIMMState; 35 typedef struct sPAPRMachineClass sPAPRMachineClass; 36 37 #define TYPE_SPAPR_MACHINE "spapr-machine" 38 #define SPAPR_MACHINE(obj) \ 39 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 40 #define SPAPR_MACHINE_GET_CLASS(obj) \ 41 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 42 #define SPAPR_MACHINE_CLASS(klass) \ 43 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 44 45 /** 46 * sPAPRMachineClass: 47 */ 48 struct sPAPRMachineClass { 49 /*< private >*/ 50 MachineClass parent_class; 51 52 /*< public >*/ 53 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 54 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 55 const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */ 56 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 57 uint64_t *buid, hwaddr *pio, 58 hwaddr *mmio32, hwaddr *mmio64, 59 unsigned n_dma, uint32_t *liobns, Error **errp); 60 }; 61 62 /** 63 * sPAPRMachineState: 64 */ 65 struct sPAPRMachineState { 66 /*< private >*/ 67 MachineState parent_obj; 68 69 struct VIOsPAPRBus *vio_bus; 70 QLIST_HEAD(, sPAPRPHBState) phbs; 71 struct sPAPRNVRAM *nvram; 72 ICSState *ics; 73 sPAPRRTCState rtc; 74 75 void *htab; 76 uint32_t htab_shift; 77 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 78 hwaddr rma_size; 79 int vrma_adjust; 80 ssize_t rtas_size; 81 void *rtas_blob; 82 long kernel_size; 83 bool kernel_le; 84 uint32_t initrd_base; 85 long initrd_size; 86 uint64_t rtc_offset; /* Now used only during incoming migration */ 87 struct PPCTimebase tb; 88 bool has_graphics; 89 90 Notifier epow_notifier; 91 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 92 bool use_hotplug_event_source; 93 sPAPREventSource *event_sources; 94 95 /* ibm,client-architecture-support option negotiation */ 96 bool cas_reboot; 97 bool cas_legacy_guest_workaround; 98 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 99 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 100 uint32_t max_compat_pvr; 101 102 /* Migration state */ 103 int htab_save_index; 104 bool htab_first_pass; 105 int htab_fd; 106 107 /* Pending DIMM unplug cache. It is populated when a LMB 108 * unplug starts. It can be regenerated if a migration 109 * occurs during the unplug process. */ 110 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 111 112 /*< public >*/ 113 char *kvm_type; 114 MemoryHotplugState hotplug_memory; 115 116 const char *icp_type; 117 }; 118 119 #define H_SUCCESS 0 120 #define H_BUSY 1 /* Hardware busy -- retry later */ 121 #define H_CLOSED 2 /* Resource closed */ 122 #define H_NOT_AVAILABLE 3 123 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 124 #define H_PARTIAL 5 125 #define H_IN_PROGRESS 14 /* Kind of like busy */ 126 #define H_PAGE_REGISTERED 15 127 #define H_PARTIAL_STORE 16 128 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 129 #define H_CONTINUE 18 /* Returned from H_Join on success */ 130 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 131 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 132 is a good time to retry */ 133 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 134 is a good time to retry */ 135 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 136 is a good time to retry */ 137 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 138 is a good time to retry */ 139 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 140 is a good time to retry */ 141 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 142 is a good time to retry */ 143 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 144 #define H_HARDWARE -1 /* Hardware error */ 145 #define H_FUNCTION -2 /* Function not supported */ 146 #define H_PRIVILEGE -3 /* Caller not privileged */ 147 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 148 #define H_BAD_MODE -5 /* Illegal msr value */ 149 #define H_PTEG_FULL -6 /* PTEG is full */ 150 #define H_NOT_FOUND -7 /* PTE was not found" */ 151 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 152 #define H_NO_MEM -9 153 #define H_AUTHORITY -10 154 #define H_PERMISSION -11 155 #define H_DROPPED -12 156 #define H_SOURCE_PARM -13 157 #define H_DEST_PARM -14 158 #define H_REMOTE_PARM -15 159 #define H_RESOURCE -16 160 #define H_ADAPTER_PARM -17 161 #define H_RH_PARM -18 162 #define H_RCQ_PARM -19 163 #define H_SCQ_PARM -20 164 #define H_EQ_PARM -21 165 #define H_RT_PARM -22 166 #define H_ST_PARM -23 167 #define H_SIGT_PARM -24 168 #define H_TOKEN_PARM -25 169 #define H_MLENGTH_PARM -27 170 #define H_MEM_PARM -28 171 #define H_MEM_ACCESS_PARM -29 172 #define H_ATTR_PARM -30 173 #define H_PORT_PARM -31 174 #define H_MCG_PARM -32 175 #define H_VL_PARM -33 176 #define H_TSIZE_PARM -34 177 #define H_TRACE_PARM -35 178 179 #define H_MASK_PARM -37 180 #define H_MCG_FULL -38 181 #define H_ALIAS_EXIST -39 182 #define H_P_COUNTER -40 183 #define H_TABLE_FULL -41 184 #define H_ALT_TABLE -42 185 #define H_MR_CONDITION -43 186 #define H_NOT_ENOUGH_RESOURCES -44 187 #define H_R_STATE -45 188 #define H_RESCINDEND -46 189 #define H_P2 -55 190 #define H_P3 -56 191 #define H_P4 -57 192 #define H_P5 -58 193 #define H_P6 -59 194 #define H_P7 -60 195 #define H_P8 -61 196 #define H_P9 -62 197 #define H_UNSUPPORTED_FLAG -256 198 #define H_MULTI_THREADS_ACTIVE -9005 199 200 201 /* Long Busy is a condition that can be returned by the firmware 202 * when a call cannot be completed now, but the identical call 203 * should be retried later. This prevents calls blocking in the 204 * firmware for long periods of time. Annoyingly the firmware can return 205 * a range of return codes, hinting at how long we should wait before 206 * retrying. If you don't care for the hint, the macro below is a good 207 * way to check for the long_busy return codes 208 */ 209 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 210 && (x <= H_LONG_BUSY_END_RANGE)) 211 212 /* Flags */ 213 #define H_LARGE_PAGE (1ULL<<(63-16)) 214 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 215 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 216 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 217 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 218 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 219 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 220 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 221 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 222 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 223 #define H_ANDCOND (1ULL<<(63-33)) 224 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 225 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 226 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 227 #define H_COPY_PAGE (1ULL<<(63-49)) 228 #define H_N (1ULL<<(63-61)) 229 #define H_PP1 (1ULL<<(63-62)) 230 #define H_PP2 (1ULL<<(63-63)) 231 232 /* Values for 2nd argument to H_SET_MODE */ 233 #define H_SET_MODE_RESOURCE_SET_CIABR 1 234 #define H_SET_MODE_RESOURCE_SET_DAWR 2 235 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 236 #define H_SET_MODE_RESOURCE_LE 4 237 238 /* Flags for H_SET_MODE_RESOURCE_LE */ 239 #define H_SET_MODE_ENDIAN_BIG 0 240 #define H_SET_MODE_ENDIAN_LITTLE 1 241 242 /* VASI States */ 243 #define H_VASI_INVALID 0 244 #define H_VASI_ENABLED 1 245 #define H_VASI_ABORTED 2 246 #define H_VASI_SUSPENDING 3 247 #define H_VASI_SUSPENDED 4 248 #define H_VASI_RESUMED 5 249 #define H_VASI_COMPLETED 6 250 251 /* DABRX flags */ 252 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 253 #define H_DABRX_KERNEL (1ULL<<(63-62)) 254 #define H_DABRX_USER (1ULL<<(63-63)) 255 256 /* Each control block has to be on a 4K boundary */ 257 #define H_CB_ALIGNMENT 4096 258 259 /* pSeries hypervisor opcodes */ 260 #define H_REMOVE 0x04 261 #define H_ENTER 0x08 262 #define H_READ 0x0c 263 #define H_CLEAR_MOD 0x10 264 #define H_CLEAR_REF 0x14 265 #define H_PROTECT 0x18 266 #define H_GET_TCE 0x1c 267 #define H_PUT_TCE 0x20 268 #define H_SET_SPRG0 0x24 269 #define H_SET_DABR 0x28 270 #define H_PAGE_INIT 0x2c 271 #define H_SET_ASR 0x30 272 #define H_ASR_ON 0x34 273 #define H_ASR_OFF 0x38 274 #define H_LOGICAL_CI_LOAD 0x3c 275 #define H_LOGICAL_CI_STORE 0x40 276 #define H_LOGICAL_CACHE_LOAD 0x44 277 #define H_LOGICAL_CACHE_STORE 0x48 278 #define H_LOGICAL_ICBI 0x4c 279 #define H_LOGICAL_DCBF 0x50 280 #define H_GET_TERM_CHAR 0x54 281 #define H_PUT_TERM_CHAR 0x58 282 #define H_REAL_TO_LOGICAL 0x5c 283 #define H_HYPERVISOR_DATA 0x60 284 #define H_EOI 0x64 285 #define H_CPPR 0x68 286 #define H_IPI 0x6c 287 #define H_IPOLL 0x70 288 #define H_XIRR 0x74 289 #define H_PERFMON 0x7c 290 #define H_MIGRATE_DMA 0x78 291 #define H_REGISTER_VPA 0xDC 292 #define H_CEDE 0xE0 293 #define H_CONFER 0xE4 294 #define H_PROD 0xE8 295 #define H_GET_PPP 0xEC 296 #define H_SET_PPP 0xF0 297 #define H_PURR 0xF4 298 #define H_PIC 0xF8 299 #define H_REG_CRQ 0xFC 300 #define H_FREE_CRQ 0x100 301 #define H_VIO_SIGNAL 0x104 302 #define H_SEND_CRQ 0x108 303 #define H_COPY_RDMA 0x110 304 #define H_REGISTER_LOGICAL_LAN 0x114 305 #define H_FREE_LOGICAL_LAN 0x118 306 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 307 #define H_SEND_LOGICAL_LAN 0x120 308 #define H_BULK_REMOVE 0x124 309 #define H_MULTICAST_CTRL 0x130 310 #define H_SET_XDABR 0x134 311 #define H_STUFF_TCE 0x138 312 #define H_PUT_TCE_INDIRECT 0x13C 313 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 314 #define H_VTERM_PARTNER_INFO 0x150 315 #define H_REGISTER_VTERM 0x154 316 #define H_FREE_VTERM 0x158 317 #define H_RESET_EVENTS 0x15C 318 #define H_ALLOC_RESOURCE 0x160 319 #define H_FREE_RESOURCE 0x164 320 #define H_MODIFY_QP 0x168 321 #define H_QUERY_QP 0x16C 322 #define H_REREGISTER_PMR 0x170 323 #define H_REGISTER_SMR 0x174 324 #define H_QUERY_MR 0x178 325 #define H_QUERY_MW 0x17C 326 #define H_QUERY_HCA 0x180 327 #define H_QUERY_PORT 0x184 328 #define H_MODIFY_PORT 0x188 329 #define H_DEFINE_AQP1 0x18C 330 #define H_GET_TRACE_BUFFER 0x190 331 #define H_DEFINE_AQP0 0x194 332 #define H_RESIZE_MR 0x198 333 #define H_ATTACH_MCQP 0x19C 334 #define H_DETACH_MCQP 0x1A0 335 #define H_CREATE_RPT 0x1A4 336 #define H_REMOVE_RPT 0x1A8 337 #define H_REGISTER_RPAGES 0x1AC 338 #define H_DISABLE_AND_GETC 0x1B0 339 #define H_ERROR_DATA 0x1B4 340 #define H_GET_HCA_INFO 0x1B8 341 #define H_GET_PERF_COUNT 0x1BC 342 #define H_MANAGE_TRACE 0x1C0 343 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 344 #define H_QUERY_INT_STATE 0x1E4 345 #define H_POLL_PENDING 0x1D8 346 #define H_ILLAN_ATTRIBUTES 0x244 347 #define H_MODIFY_HEA_QP 0x250 348 #define H_QUERY_HEA_QP 0x254 349 #define H_QUERY_HEA 0x258 350 #define H_QUERY_HEA_PORT 0x25C 351 #define H_MODIFY_HEA_PORT 0x260 352 #define H_REG_BCMC 0x264 353 #define H_DEREG_BCMC 0x268 354 #define H_REGISTER_HEA_RPAGES 0x26C 355 #define H_DISABLE_AND_GET_HEA 0x270 356 #define H_GET_HEA_INFO 0x274 357 #define H_ALLOC_HEA_RESOURCE 0x278 358 #define H_ADD_CONN 0x284 359 #define H_DEL_CONN 0x288 360 #define H_JOIN 0x298 361 #define H_VASI_STATE 0x2A4 362 #define H_ENABLE_CRQ 0x2B0 363 #define H_GET_EM_PARMS 0x2B8 364 #define H_SET_MPP 0x2D0 365 #define H_GET_MPP 0x2D4 366 #define H_XIRR_X 0x2FC 367 #define H_RANDOM 0x300 368 #define H_SET_MODE 0x31C 369 #define H_CLEAN_SLB 0x374 370 #define H_INVALIDATE_PID 0x378 371 #define H_REGISTER_PROC_TBL 0x37C 372 #define H_SIGNAL_SYS_RESET 0x380 373 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET 374 375 /* The hcalls above are standardized in PAPR and implemented by pHyp 376 * as well. 377 * 378 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 379 * So far we just need one for H_RTAS, but in future we'll need more 380 * for extensions like virtio. We put those into the 0xf000-0xfffc 381 * range which is reserved by PAPR for "platform-specific" hcalls. 382 */ 383 #define KVMPPC_HCALL_BASE 0xf000 384 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 385 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 386 /* Client Architecture support */ 387 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 388 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 389 390 typedef struct sPAPRDeviceTreeUpdateHeader { 391 uint32_t version_id; 392 } sPAPRDeviceTreeUpdateHeader; 393 394 #define hcall_dprintf(fmt, ...) \ 395 do { \ 396 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 397 } while (0) 398 399 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 400 target_ulong opcode, 401 target_ulong *args); 402 403 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 404 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 405 target_ulong *args); 406 407 /* ibm,set-eeh-option */ 408 #define RTAS_EEH_DISABLE 0 409 #define RTAS_EEH_ENABLE 1 410 #define RTAS_EEH_THAW_IO 2 411 #define RTAS_EEH_THAW_DMA 3 412 413 /* ibm,get-config-addr-info2 */ 414 #define RTAS_GET_PE_ADDR 0 415 #define RTAS_GET_PE_MODE 1 416 #define RTAS_PE_MODE_NONE 0 417 #define RTAS_PE_MODE_NOT_SHARED 1 418 #define RTAS_PE_MODE_SHARED 2 419 420 /* ibm,read-slot-reset-state2 */ 421 #define RTAS_EEH_PE_STATE_NORMAL 0 422 #define RTAS_EEH_PE_STATE_RESET 1 423 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 424 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 425 #define RTAS_EEH_PE_STATE_UNAVAIL 5 426 #define RTAS_EEH_NOT_SUPPORT 0 427 #define RTAS_EEH_SUPPORT 1 428 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 429 #define RTAS_EEH_PE_RECOVER_INFO 0 430 431 /* ibm,set-slot-reset */ 432 #define RTAS_SLOT_RESET_DEACTIVATE 0 433 #define RTAS_SLOT_RESET_HOT 1 434 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 435 436 /* ibm,slot-error-detail */ 437 #define RTAS_SLOT_TEMP_ERR_LOG 1 438 #define RTAS_SLOT_PERM_ERR_LOG 2 439 440 /* RTAS return codes */ 441 #define RTAS_OUT_SUCCESS 0 442 #define RTAS_OUT_NO_ERRORS_FOUND 1 443 #define RTAS_OUT_HW_ERROR -1 444 #define RTAS_OUT_BUSY -2 445 #define RTAS_OUT_PARAM_ERROR -3 446 #define RTAS_OUT_NOT_SUPPORTED -3 447 #define RTAS_OUT_NO_SUCH_INDICATOR -3 448 #define RTAS_OUT_NOT_AUTHORIZED -9002 449 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 450 451 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 452 #define RTAS_DDW_PGSIZE_4K 0x01 453 #define RTAS_DDW_PGSIZE_64K 0x02 454 #define RTAS_DDW_PGSIZE_16M 0x04 455 #define RTAS_DDW_PGSIZE_32M 0x08 456 #define RTAS_DDW_PGSIZE_64M 0x10 457 #define RTAS_DDW_PGSIZE_128M 0x20 458 #define RTAS_DDW_PGSIZE_256M 0x40 459 #define RTAS_DDW_PGSIZE_16G 0x80 460 461 /* RTAS tokens */ 462 #define RTAS_TOKEN_BASE 0x2000 463 464 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 465 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 466 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 467 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 468 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 469 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 470 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 471 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 472 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 473 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 474 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 475 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 476 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 477 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 478 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 479 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 480 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 481 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 482 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 483 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 484 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 485 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 486 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 487 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 488 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 489 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 490 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 491 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 492 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 493 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 494 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 495 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 496 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 497 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 498 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 499 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 500 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 501 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 502 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 503 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 504 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 505 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 506 507 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 508 509 /* RTAS ibm,get-system-parameter token values */ 510 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 511 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 512 #define RTAS_SYSPARM_UUID 48 513 514 /* RTAS indicator/sensor types 515 * 516 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 517 * 518 * NOTE: currently only DR-related sensors are implemented here 519 */ 520 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 521 #define RTAS_SENSOR_TYPE_DR 9002 522 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 523 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 524 525 /* Possible values for the platform-processor-diagnostics-run-mode parameter 526 * of the RTAS ibm,get-system-parameter call. 527 */ 528 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 529 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 530 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 531 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 532 533 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 534 { 535 return addr & ~0xF000000000000000ULL; 536 } 537 538 static inline uint32_t rtas_ld(target_ulong phys, int n) 539 { 540 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 541 } 542 543 static inline uint64_t rtas_ldq(target_ulong phys, int n) 544 { 545 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 546 } 547 548 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 549 { 550 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 551 } 552 553 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 554 uint32_t token, 555 uint32_t nargs, target_ulong args, 556 uint32_t nret, target_ulong rets); 557 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 558 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 559 uint32_t token, uint32_t nargs, target_ulong args, 560 uint32_t nret, target_ulong rets); 561 void spapr_dt_rtas_tokens(void *fdt, int rtas); 562 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 563 564 #define SPAPR_TCE_PAGE_SHIFT 12 565 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 566 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 567 568 #define SPAPR_VIO_BASE_LIOBN 0x00000000 569 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 570 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 571 (0x80000000 | ((phb_index) << 8) | (window_num)) 572 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 573 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 574 575 #define RTAS_ERROR_LOG_MAX 2048 576 577 #define RTAS_EVENT_SCAN_RATE 1 578 579 typedef struct sPAPRTCETable sPAPRTCETable; 580 581 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 582 #define SPAPR_TCE_TABLE(obj) \ 583 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 584 585 struct sPAPRTCETable { 586 DeviceState parent; 587 uint32_t liobn; 588 uint32_t nb_table; 589 uint64_t bus_offset; 590 uint32_t page_shift; 591 uint64_t *table; 592 uint32_t mig_nb_table; 593 uint64_t *mig_table; 594 bool bypass; 595 bool need_vfio; 596 int fd; 597 MemoryRegion root, iommu; 598 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 599 QLIST_ENTRY(sPAPRTCETable) list; 600 }; 601 602 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 603 604 struct sPAPREventLogEntry { 605 int log_type; 606 void *data; 607 QTAILQ_ENTRY(sPAPREventLogEntry) next; 608 }; 609 610 void spapr_events_init(sPAPRMachineState *sm); 611 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 612 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 613 target_ulong addr, target_ulong size, 614 sPAPROptionVector *ov5_updates); 615 void close_htab_fd(sPAPRMachineState *spapr); 616 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 617 void spapr_free_hpt(sPAPRMachineState *spapr); 618 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 619 void spapr_tce_table_enable(sPAPRTCETable *tcet, 620 uint32_t page_shift, uint64_t bus_offset, 621 uint32_t nb_table); 622 void spapr_tce_table_disable(sPAPRTCETable *tcet); 623 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 624 625 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 626 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 627 uint32_t liobn, uint64_t window, uint32_t size); 628 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 629 sPAPRTCETable *tcet); 630 void spapr_pci_switch_vga(bool big_endian); 631 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 632 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 633 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 634 uint32_t count); 635 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 636 uint32_t count); 637 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 638 uint32_t count, uint32_t index); 639 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 640 uint32_t count, uint32_t index); 641 void spapr_cpu_parse_features(sPAPRMachineState *spapr); 642 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 643 sPAPRMachineState *spapr); 644 645 /* CPU and LMB DRC release callbacks. */ 646 void spapr_core_release(DeviceState *dev); 647 void spapr_lmb_release(DeviceState *dev); 648 649 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 650 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 651 652 #define TYPE_SPAPR_RNG "spapr-rng" 653 654 int spapr_rng_populate_dt(void *fdt); 655 656 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 657 658 /* 659 * This defines the maximum number of DIMM slots we can have for sPAPR 660 * guest. This is not defined by sPAPR but we are defining it to 32 slots 661 * based on default number of slots provided by PowerPC kernel. 662 */ 663 #define SPAPR_MAX_RAM_SLOTS 32 664 665 /* 1GB alignment for hotplug memory region */ 666 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 667 668 /* 669 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 670 * property under ibm,dynamic-reconfiguration-memory node. 671 */ 672 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 673 674 /* 675 * Defines for flag value in ibm,dynamic-memory property under 676 * ibm,dynamic-reconfiguration-memory node. 677 */ 678 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 679 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 680 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 681 682 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 683 684 #endif /* HW_SPAPR_H */ 685