1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/xics.h" 8 #include "hw/ppc/spapr_drc.h" 9 #include "hw/mem/pc-dimm.h" 10 #include "hw/ppc/spapr_ovec.h" 11 12 struct VIOsPAPRBus; 13 struct sPAPRPHBState; 14 struct sPAPRNVRAM; 15 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 16 typedef struct sPAPREventSource sPAPREventSource; 17 typedef struct sPAPRPendingHPT sPAPRPendingHPT; 18 19 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 20 #define SPAPR_ENTRY_POINT 0x100 21 22 #define SPAPR_TIMEBASE_FREQ 512000000ULL 23 24 #define TYPE_SPAPR_RTC "spapr-rtc" 25 26 #define SPAPR_RTC(obj) \ 27 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 28 29 typedef struct sPAPRRTCState sPAPRRTCState; 30 struct sPAPRRTCState { 31 /*< private >*/ 32 DeviceState parent_obj; 33 int64_t ns_offset; 34 }; 35 36 typedef struct sPAPRDIMMState sPAPRDIMMState; 37 typedef struct sPAPRMachineClass sPAPRMachineClass; 38 39 #define TYPE_SPAPR_MACHINE "spapr-machine" 40 #define SPAPR_MACHINE(obj) \ 41 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 42 #define SPAPR_MACHINE_GET_CLASS(obj) \ 43 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 44 #define SPAPR_MACHINE_CLASS(klass) \ 45 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 46 47 typedef enum { 48 SPAPR_RESIZE_HPT_DEFAULT = 0, 49 SPAPR_RESIZE_HPT_DISABLED, 50 SPAPR_RESIZE_HPT_ENABLED, 51 SPAPR_RESIZE_HPT_REQUIRED, 52 } sPAPRResizeHPT; 53 54 /** 55 * Capabilities 56 */ 57 58 /* Hardware Transactional Memory */ 59 #define SPAPR_CAP_HTM 0x00 60 /* Vector Scalar Extensions */ 61 #define SPAPR_CAP_VSX 0x01 62 /* Decimal Floating Point */ 63 #define SPAPR_CAP_DFP 0x02 64 /* Cache Flush on Privilege Change */ 65 #define SPAPR_CAP_CFPC 0x03 66 /* Speculation Barrier Bounds Checking */ 67 #define SPAPR_CAP_SBBC 0x04 68 /* Indirect Branch Serialisation */ 69 #define SPAPR_CAP_IBS 0x05 70 /* HPT Maximum Page Size (encoded as a shift) */ 71 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 72 /* Num Caps */ 73 #define SPAPR_CAP_NUM (SPAPR_CAP_HPT_MAXPAGESIZE + 1) 74 75 /* 76 * Capability Values 77 */ 78 /* Bool Caps */ 79 #define SPAPR_CAP_OFF 0x00 80 #define SPAPR_CAP_ON 0x01 81 /* Custom Caps */ 82 #define SPAPR_CAP_BROKEN 0x00 83 #define SPAPR_CAP_WORKAROUND 0x01 84 #define SPAPR_CAP_FIXED 0x02 85 #define SPAPR_CAP_FIXED_IBS 0x02 86 #define SPAPR_CAP_FIXED_CCD 0x03 87 88 typedef struct sPAPRCapabilities sPAPRCapabilities; 89 struct sPAPRCapabilities { 90 uint8_t caps[SPAPR_CAP_NUM]; 91 }; 92 93 /** 94 * sPAPRMachineClass: 95 */ 96 struct sPAPRMachineClass { 97 /*< private >*/ 98 MachineClass parent_class; 99 100 /*< public >*/ 101 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 102 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 103 bool pre_2_10_has_unused_icps; 104 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 105 uint64_t *buid, hwaddr *pio, 106 hwaddr *mmio32, hwaddr *mmio64, 107 unsigned n_dma, uint32_t *liobns, Error **errp); 108 sPAPRResizeHPT resize_hpt_default; 109 sPAPRCapabilities default_caps; 110 }; 111 112 /** 113 * sPAPRMachineState: 114 */ 115 struct sPAPRMachineState { 116 /*< private >*/ 117 MachineState parent_obj; 118 119 struct VIOsPAPRBus *vio_bus; 120 QLIST_HEAD(, sPAPRPHBState) phbs; 121 struct sPAPRNVRAM *nvram; 122 ICSState *ics; 123 sPAPRRTCState rtc; 124 125 sPAPRResizeHPT resize_hpt; 126 void *htab; 127 uint32_t htab_shift; 128 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 129 sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 130 131 hwaddr rma_size; 132 int vrma_adjust; 133 ssize_t rtas_size; 134 void *rtas_blob; 135 long kernel_size; 136 bool kernel_le; 137 uint32_t initrd_base; 138 long initrd_size; 139 uint64_t rtc_offset; /* Now used only during incoming migration */ 140 struct PPCTimebase tb; 141 bool has_graphics; 142 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 143 144 Notifier epow_notifier; 145 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 146 bool use_hotplug_event_source; 147 sPAPREventSource *event_sources; 148 149 /* ibm,client-architecture-support option negotiation */ 150 bool cas_reboot; 151 bool cas_legacy_guest_workaround; 152 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 153 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 154 uint32_t max_compat_pvr; 155 156 /* Migration state */ 157 int htab_save_index; 158 bool htab_first_pass; 159 int htab_fd; 160 161 /* Pending DIMM unplug cache. It is populated when a LMB 162 * unplug starts. It can be regenerated if a migration 163 * occurs during the unplug process. */ 164 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 165 166 /*< public >*/ 167 char *kvm_type; 168 169 const char *icp_type; 170 171 bool cmd_line_caps[SPAPR_CAP_NUM]; 172 sPAPRCapabilities def, eff, mig; 173 }; 174 175 #define H_SUCCESS 0 176 #define H_BUSY 1 /* Hardware busy -- retry later */ 177 #define H_CLOSED 2 /* Resource closed */ 178 #define H_NOT_AVAILABLE 3 179 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 180 #define H_PARTIAL 5 181 #define H_IN_PROGRESS 14 /* Kind of like busy */ 182 #define H_PAGE_REGISTERED 15 183 #define H_PARTIAL_STORE 16 184 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 185 #define H_CONTINUE 18 /* Returned from H_Join on success */ 186 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 187 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 188 is a good time to retry */ 189 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 190 is a good time to retry */ 191 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 192 is a good time to retry */ 193 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 194 is a good time to retry */ 195 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 196 is a good time to retry */ 197 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 198 is a good time to retry */ 199 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 200 #define H_HARDWARE -1 /* Hardware error */ 201 #define H_FUNCTION -2 /* Function not supported */ 202 #define H_PRIVILEGE -3 /* Caller not privileged */ 203 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 204 #define H_BAD_MODE -5 /* Illegal msr value */ 205 #define H_PTEG_FULL -6 /* PTEG is full */ 206 #define H_NOT_FOUND -7 /* PTE was not found" */ 207 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 208 #define H_NO_MEM -9 209 #define H_AUTHORITY -10 210 #define H_PERMISSION -11 211 #define H_DROPPED -12 212 #define H_SOURCE_PARM -13 213 #define H_DEST_PARM -14 214 #define H_REMOTE_PARM -15 215 #define H_RESOURCE -16 216 #define H_ADAPTER_PARM -17 217 #define H_RH_PARM -18 218 #define H_RCQ_PARM -19 219 #define H_SCQ_PARM -20 220 #define H_EQ_PARM -21 221 #define H_RT_PARM -22 222 #define H_ST_PARM -23 223 #define H_SIGT_PARM -24 224 #define H_TOKEN_PARM -25 225 #define H_MLENGTH_PARM -27 226 #define H_MEM_PARM -28 227 #define H_MEM_ACCESS_PARM -29 228 #define H_ATTR_PARM -30 229 #define H_PORT_PARM -31 230 #define H_MCG_PARM -32 231 #define H_VL_PARM -33 232 #define H_TSIZE_PARM -34 233 #define H_TRACE_PARM -35 234 235 #define H_MASK_PARM -37 236 #define H_MCG_FULL -38 237 #define H_ALIAS_EXIST -39 238 #define H_P_COUNTER -40 239 #define H_TABLE_FULL -41 240 #define H_ALT_TABLE -42 241 #define H_MR_CONDITION -43 242 #define H_NOT_ENOUGH_RESOURCES -44 243 #define H_R_STATE -45 244 #define H_RESCINDEND -46 245 #define H_P2 -55 246 #define H_P3 -56 247 #define H_P4 -57 248 #define H_P5 -58 249 #define H_P6 -59 250 #define H_P7 -60 251 #define H_P8 -61 252 #define H_P9 -62 253 #define H_UNSUPPORTED_FLAG -256 254 #define H_MULTI_THREADS_ACTIVE -9005 255 256 257 /* Long Busy is a condition that can be returned by the firmware 258 * when a call cannot be completed now, but the identical call 259 * should be retried later. This prevents calls blocking in the 260 * firmware for long periods of time. Annoyingly the firmware can return 261 * a range of return codes, hinting at how long we should wait before 262 * retrying. If you don't care for the hint, the macro below is a good 263 * way to check for the long_busy return codes 264 */ 265 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 266 && (x <= H_LONG_BUSY_END_RANGE)) 267 268 /* Flags */ 269 #define H_LARGE_PAGE (1ULL<<(63-16)) 270 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 271 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 272 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 273 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 274 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 275 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 276 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 277 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 278 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 279 #define H_ANDCOND (1ULL<<(63-33)) 280 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 281 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 282 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 283 #define H_COPY_PAGE (1ULL<<(63-49)) 284 #define H_N (1ULL<<(63-61)) 285 #define H_PP1 (1ULL<<(63-62)) 286 #define H_PP2 (1ULL<<(63-63)) 287 288 /* Values for 2nd argument to H_SET_MODE */ 289 #define H_SET_MODE_RESOURCE_SET_CIABR 1 290 #define H_SET_MODE_RESOURCE_SET_DAWR 2 291 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 292 #define H_SET_MODE_RESOURCE_LE 4 293 294 /* Flags for H_SET_MODE_RESOURCE_LE */ 295 #define H_SET_MODE_ENDIAN_BIG 0 296 #define H_SET_MODE_ENDIAN_LITTLE 1 297 298 /* VASI States */ 299 #define H_VASI_INVALID 0 300 #define H_VASI_ENABLED 1 301 #define H_VASI_ABORTED 2 302 #define H_VASI_SUSPENDING 3 303 #define H_VASI_SUSPENDED 4 304 #define H_VASI_RESUMED 5 305 #define H_VASI_COMPLETED 6 306 307 /* DABRX flags */ 308 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 309 #define H_DABRX_KERNEL (1ULL<<(63-62)) 310 #define H_DABRX_USER (1ULL<<(63-63)) 311 312 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 313 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 314 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 315 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 316 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 317 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 318 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 319 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 320 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 321 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 322 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 323 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 324 325 /* Each control block has to be on a 4K boundary */ 326 #define H_CB_ALIGNMENT 4096 327 328 /* pSeries hypervisor opcodes */ 329 #define H_REMOVE 0x04 330 #define H_ENTER 0x08 331 #define H_READ 0x0c 332 #define H_CLEAR_MOD 0x10 333 #define H_CLEAR_REF 0x14 334 #define H_PROTECT 0x18 335 #define H_GET_TCE 0x1c 336 #define H_PUT_TCE 0x20 337 #define H_SET_SPRG0 0x24 338 #define H_SET_DABR 0x28 339 #define H_PAGE_INIT 0x2c 340 #define H_SET_ASR 0x30 341 #define H_ASR_ON 0x34 342 #define H_ASR_OFF 0x38 343 #define H_LOGICAL_CI_LOAD 0x3c 344 #define H_LOGICAL_CI_STORE 0x40 345 #define H_LOGICAL_CACHE_LOAD 0x44 346 #define H_LOGICAL_CACHE_STORE 0x48 347 #define H_LOGICAL_ICBI 0x4c 348 #define H_LOGICAL_DCBF 0x50 349 #define H_GET_TERM_CHAR 0x54 350 #define H_PUT_TERM_CHAR 0x58 351 #define H_REAL_TO_LOGICAL 0x5c 352 #define H_HYPERVISOR_DATA 0x60 353 #define H_EOI 0x64 354 #define H_CPPR 0x68 355 #define H_IPI 0x6c 356 #define H_IPOLL 0x70 357 #define H_XIRR 0x74 358 #define H_PERFMON 0x7c 359 #define H_MIGRATE_DMA 0x78 360 #define H_REGISTER_VPA 0xDC 361 #define H_CEDE 0xE0 362 #define H_CONFER 0xE4 363 #define H_PROD 0xE8 364 #define H_GET_PPP 0xEC 365 #define H_SET_PPP 0xF0 366 #define H_PURR 0xF4 367 #define H_PIC 0xF8 368 #define H_REG_CRQ 0xFC 369 #define H_FREE_CRQ 0x100 370 #define H_VIO_SIGNAL 0x104 371 #define H_SEND_CRQ 0x108 372 #define H_COPY_RDMA 0x110 373 #define H_REGISTER_LOGICAL_LAN 0x114 374 #define H_FREE_LOGICAL_LAN 0x118 375 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 376 #define H_SEND_LOGICAL_LAN 0x120 377 #define H_BULK_REMOVE 0x124 378 #define H_MULTICAST_CTRL 0x130 379 #define H_SET_XDABR 0x134 380 #define H_STUFF_TCE 0x138 381 #define H_PUT_TCE_INDIRECT 0x13C 382 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 383 #define H_VTERM_PARTNER_INFO 0x150 384 #define H_REGISTER_VTERM 0x154 385 #define H_FREE_VTERM 0x158 386 #define H_RESET_EVENTS 0x15C 387 #define H_ALLOC_RESOURCE 0x160 388 #define H_FREE_RESOURCE 0x164 389 #define H_MODIFY_QP 0x168 390 #define H_QUERY_QP 0x16C 391 #define H_REREGISTER_PMR 0x170 392 #define H_REGISTER_SMR 0x174 393 #define H_QUERY_MR 0x178 394 #define H_QUERY_MW 0x17C 395 #define H_QUERY_HCA 0x180 396 #define H_QUERY_PORT 0x184 397 #define H_MODIFY_PORT 0x188 398 #define H_DEFINE_AQP1 0x18C 399 #define H_GET_TRACE_BUFFER 0x190 400 #define H_DEFINE_AQP0 0x194 401 #define H_RESIZE_MR 0x198 402 #define H_ATTACH_MCQP 0x19C 403 #define H_DETACH_MCQP 0x1A0 404 #define H_CREATE_RPT 0x1A4 405 #define H_REMOVE_RPT 0x1A8 406 #define H_REGISTER_RPAGES 0x1AC 407 #define H_DISABLE_AND_GETC 0x1B0 408 #define H_ERROR_DATA 0x1B4 409 #define H_GET_HCA_INFO 0x1B8 410 #define H_GET_PERF_COUNT 0x1BC 411 #define H_MANAGE_TRACE 0x1C0 412 #define H_GET_CPU_CHARACTERISTICS 0x1C8 413 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 414 #define H_QUERY_INT_STATE 0x1E4 415 #define H_POLL_PENDING 0x1D8 416 #define H_ILLAN_ATTRIBUTES 0x244 417 #define H_MODIFY_HEA_QP 0x250 418 #define H_QUERY_HEA_QP 0x254 419 #define H_QUERY_HEA 0x258 420 #define H_QUERY_HEA_PORT 0x25C 421 #define H_MODIFY_HEA_PORT 0x260 422 #define H_REG_BCMC 0x264 423 #define H_DEREG_BCMC 0x268 424 #define H_REGISTER_HEA_RPAGES 0x26C 425 #define H_DISABLE_AND_GET_HEA 0x270 426 #define H_GET_HEA_INFO 0x274 427 #define H_ALLOC_HEA_RESOURCE 0x278 428 #define H_ADD_CONN 0x284 429 #define H_DEL_CONN 0x288 430 #define H_JOIN 0x298 431 #define H_VASI_STATE 0x2A4 432 #define H_ENABLE_CRQ 0x2B0 433 #define H_GET_EM_PARMS 0x2B8 434 #define H_SET_MPP 0x2D0 435 #define H_GET_MPP 0x2D4 436 #define H_XIRR_X 0x2FC 437 #define H_RANDOM 0x300 438 #define H_SET_MODE 0x31C 439 #define H_RESIZE_HPT_PREPARE 0x36C 440 #define H_RESIZE_HPT_COMMIT 0x370 441 #define H_CLEAN_SLB 0x374 442 #define H_INVALIDATE_PID 0x378 443 #define H_REGISTER_PROC_TBL 0x37C 444 #define H_SIGNAL_SYS_RESET 0x380 445 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET 446 447 /* The hcalls above are standardized in PAPR and implemented by pHyp 448 * as well. 449 * 450 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 451 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 452 * for "platform-specific" hcalls. 453 */ 454 #define KVMPPC_HCALL_BASE 0xf000 455 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 456 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 457 /* Client Architecture support */ 458 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 459 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 460 461 typedef struct sPAPRDeviceTreeUpdateHeader { 462 uint32_t version_id; 463 } sPAPRDeviceTreeUpdateHeader; 464 465 #define hcall_dprintf(fmt, ...) \ 466 do { \ 467 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 468 } while (0) 469 470 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 471 target_ulong opcode, 472 target_ulong *args); 473 474 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 475 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 476 target_ulong *args); 477 478 /* ibm,set-eeh-option */ 479 #define RTAS_EEH_DISABLE 0 480 #define RTAS_EEH_ENABLE 1 481 #define RTAS_EEH_THAW_IO 2 482 #define RTAS_EEH_THAW_DMA 3 483 484 /* ibm,get-config-addr-info2 */ 485 #define RTAS_GET_PE_ADDR 0 486 #define RTAS_GET_PE_MODE 1 487 #define RTAS_PE_MODE_NONE 0 488 #define RTAS_PE_MODE_NOT_SHARED 1 489 #define RTAS_PE_MODE_SHARED 2 490 491 /* ibm,read-slot-reset-state2 */ 492 #define RTAS_EEH_PE_STATE_NORMAL 0 493 #define RTAS_EEH_PE_STATE_RESET 1 494 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 495 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 496 #define RTAS_EEH_PE_STATE_UNAVAIL 5 497 #define RTAS_EEH_NOT_SUPPORT 0 498 #define RTAS_EEH_SUPPORT 1 499 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 500 #define RTAS_EEH_PE_RECOVER_INFO 0 501 502 /* ibm,set-slot-reset */ 503 #define RTAS_SLOT_RESET_DEACTIVATE 0 504 #define RTAS_SLOT_RESET_HOT 1 505 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 506 507 /* ibm,slot-error-detail */ 508 #define RTAS_SLOT_TEMP_ERR_LOG 1 509 #define RTAS_SLOT_PERM_ERR_LOG 2 510 511 /* RTAS return codes */ 512 #define RTAS_OUT_SUCCESS 0 513 #define RTAS_OUT_NO_ERRORS_FOUND 1 514 #define RTAS_OUT_HW_ERROR -1 515 #define RTAS_OUT_BUSY -2 516 #define RTAS_OUT_PARAM_ERROR -3 517 #define RTAS_OUT_NOT_SUPPORTED -3 518 #define RTAS_OUT_NO_SUCH_INDICATOR -3 519 #define RTAS_OUT_NOT_AUTHORIZED -9002 520 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 521 522 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 523 #define RTAS_DDW_PGSIZE_4K 0x01 524 #define RTAS_DDW_PGSIZE_64K 0x02 525 #define RTAS_DDW_PGSIZE_16M 0x04 526 #define RTAS_DDW_PGSIZE_32M 0x08 527 #define RTAS_DDW_PGSIZE_64M 0x10 528 #define RTAS_DDW_PGSIZE_128M 0x20 529 #define RTAS_DDW_PGSIZE_256M 0x40 530 #define RTAS_DDW_PGSIZE_16G 0x80 531 532 /* RTAS tokens */ 533 #define RTAS_TOKEN_BASE 0x2000 534 535 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 536 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 537 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 538 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 539 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 540 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 541 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 542 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 543 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 544 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 545 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 546 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 547 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 548 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 549 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 550 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 551 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 552 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 553 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 554 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 555 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 556 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 557 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 558 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 559 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 560 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 561 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 562 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 563 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 564 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 565 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 566 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 567 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 568 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 569 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 570 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 571 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 572 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 573 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 574 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 575 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 576 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 577 578 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 579 580 /* RTAS ibm,get-system-parameter token values */ 581 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 582 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 583 #define RTAS_SYSPARM_UUID 48 584 585 /* RTAS indicator/sensor types 586 * 587 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 588 * 589 * NOTE: currently only DR-related sensors are implemented here 590 */ 591 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 592 #define RTAS_SENSOR_TYPE_DR 9002 593 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 594 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 595 596 /* Possible values for the platform-processor-diagnostics-run-mode parameter 597 * of the RTAS ibm,get-system-parameter call. 598 */ 599 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 600 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 601 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 602 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 603 604 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 605 { 606 return addr & ~0xF000000000000000ULL; 607 } 608 609 static inline uint32_t rtas_ld(target_ulong phys, int n) 610 { 611 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 612 } 613 614 static inline uint64_t rtas_ldq(target_ulong phys, int n) 615 { 616 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 617 } 618 619 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 620 { 621 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 622 } 623 624 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 625 uint32_t token, 626 uint32_t nargs, target_ulong args, 627 uint32_t nret, target_ulong rets); 628 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 629 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 630 uint32_t token, uint32_t nargs, target_ulong args, 631 uint32_t nret, target_ulong rets); 632 void spapr_dt_rtas_tokens(void *fdt, int rtas); 633 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 634 635 #define SPAPR_TCE_PAGE_SHIFT 12 636 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 637 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 638 639 #define SPAPR_VIO_BASE_LIOBN 0x00000000 640 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 641 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 642 (0x80000000 | ((phb_index) << 8) | (window_num)) 643 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 644 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 645 646 #define RTAS_ERROR_LOG_MAX 2048 647 648 #define RTAS_EVENT_SCAN_RATE 1 649 650 /* This helper should be used to encode interrupt specifiers when the related 651 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 652 * VIO devices, RTAS event sources and PHBs). 653 */ 654 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi) 655 { 656 intspec[0] = cpu_to_be32(irq); 657 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 658 } 659 660 typedef struct sPAPRTCETable sPAPRTCETable; 661 662 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 663 #define SPAPR_TCE_TABLE(obj) \ 664 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 665 666 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 667 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 668 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 669 670 struct sPAPRTCETable { 671 DeviceState parent; 672 uint32_t liobn; 673 uint32_t nb_table; 674 uint64_t bus_offset; 675 uint32_t page_shift; 676 uint64_t *table; 677 uint32_t mig_nb_table; 678 uint64_t *mig_table; 679 bool bypass; 680 bool need_vfio; 681 int fd; 682 MemoryRegion root; 683 IOMMUMemoryRegion iommu; 684 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 685 QLIST_ENTRY(sPAPRTCETable) list; 686 }; 687 688 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 689 690 struct sPAPREventLogEntry { 691 uint32_t summary; 692 uint32_t extended_length; 693 void *extended_log; 694 QTAILQ_ENTRY(sPAPREventLogEntry) next; 695 }; 696 697 void spapr_events_init(sPAPRMachineState *sm); 698 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 699 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 700 target_ulong addr, target_ulong size, 701 sPAPROptionVector *ov5_updates); 702 void close_htab_fd(sPAPRMachineState *spapr); 703 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 704 void spapr_free_hpt(sPAPRMachineState *spapr); 705 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 706 void spapr_tce_table_enable(sPAPRTCETable *tcet, 707 uint32_t page_shift, uint64_t bus_offset, 708 uint32_t nb_table); 709 void spapr_tce_table_disable(sPAPRTCETable *tcet); 710 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 711 712 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 713 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 714 uint32_t liobn, uint64_t window, uint32_t size); 715 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 716 sPAPRTCETable *tcet); 717 void spapr_pci_switch_vga(bool big_endian); 718 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 719 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 720 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 721 uint32_t count); 722 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 723 uint32_t count); 724 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 725 uint32_t count, uint32_t index); 726 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 727 uint32_t count, uint32_t index); 728 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 729 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 730 Error **errp); 731 void spapr_clear_pending_events(sPAPRMachineState *spapr); 732 733 /* CPU and LMB DRC release callbacks. */ 734 void spapr_core_release(DeviceState *dev); 735 void spapr_lmb_release(DeviceState *dev); 736 737 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 738 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 739 740 #define TYPE_SPAPR_RNG "spapr-rng" 741 742 int spapr_rng_populate_dt(void *fdt); 743 744 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 745 746 /* 747 * This defines the maximum number of DIMM slots we can have for sPAPR 748 * guest. This is not defined by sPAPR but we are defining it to 32 slots 749 * based on default number of slots provided by PowerPC kernel. 750 */ 751 #define SPAPR_MAX_RAM_SLOTS 32 752 753 /* 1GB alignment for hotplug memory region */ 754 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 755 756 /* 757 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 758 * property under ibm,dynamic-reconfiguration-memory node. 759 */ 760 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 761 762 /* 763 * Defines for flag value in ibm,dynamic-memory property under 764 * ibm,dynamic-reconfiguration-memory node. 765 */ 766 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 767 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 768 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 769 770 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 771 772 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 773 774 int spapr_get_vcpu_id(PowerPCCPU *cpu); 775 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 776 PowerPCCPU *spapr_find_cpu(int vcpu_id); 777 778 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, 779 Error **errp); 780 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp) 781 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp); 782 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); 783 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); 784 785 786 int spapr_caps_pre_load(void *opaque); 787 int spapr_caps_pre_save(void *opaque); 788 789 /* 790 * Handling of optional capabilities 791 */ 792 extern const VMStateDescription vmstate_spapr_cap_htm; 793 extern const VMStateDescription vmstate_spapr_cap_vsx; 794 extern const VMStateDescription vmstate_spapr_cap_dfp; 795 extern const VMStateDescription vmstate_spapr_cap_cfpc; 796 extern const VMStateDescription vmstate_spapr_cap_sbbc; 797 extern const VMStateDescription vmstate_spapr_cap_ibs; 798 799 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap) 800 { 801 return spapr->eff.caps[cap]; 802 } 803 804 void spapr_caps_init(sPAPRMachineState *spapr); 805 void spapr_caps_apply(sPAPRMachineState *spapr); 806 void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu); 807 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); 808 int spapr_caps_post_migration(sPAPRMachineState *spapr); 809 810 void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize, 811 Error **errp); 812 813 #endif /* HW_SPAPR_H */ 814