1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 12 #include "hw/ppc/xics.h" /* For ICSState */ 13 #include "hw/ppc/spapr_tpm_proxy.h" 14 15 struct SpaprVioBus; 16 struct SpaprPhbState; 17 struct SpaprNvram; 18 19 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 20 typedef struct SpaprEventSource SpaprEventSource; 21 typedef struct SpaprPendingHpt SpaprPendingHpt; 22 23 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 24 #define SPAPR_ENTRY_POINT 0x100 25 26 #define SPAPR_TIMEBASE_FREQ 512000000ULL 27 28 #define TYPE_SPAPR_RTC "spapr-rtc" 29 30 #define SPAPR_RTC(obj) \ 31 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 32 33 typedef struct SpaprRtcState SpaprRtcState; 34 struct SpaprRtcState { 35 /*< private >*/ 36 DeviceState parent_obj; 37 int64_t ns_offset; 38 }; 39 40 typedef struct SpaprDimmState SpaprDimmState; 41 typedef struct SpaprMachineClass SpaprMachineClass; 42 43 #define TYPE_SPAPR_MACHINE "spapr-machine" 44 typedef struct SpaprMachineState SpaprMachineState; 45 #define SPAPR_MACHINE(obj) \ 46 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 47 #define SPAPR_MACHINE_GET_CLASS(obj) \ 48 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 49 #define SPAPR_MACHINE_CLASS(klass) \ 50 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 51 52 typedef enum { 53 SPAPR_RESIZE_HPT_DEFAULT = 0, 54 SPAPR_RESIZE_HPT_DISABLED, 55 SPAPR_RESIZE_HPT_ENABLED, 56 SPAPR_RESIZE_HPT_REQUIRED, 57 } SpaprResizeHpt; 58 59 /** 60 * Capabilities 61 */ 62 63 /* Hardware Transactional Memory */ 64 #define SPAPR_CAP_HTM 0x00 65 /* Vector Scalar Extensions */ 66 #define SPAPR_CAP_VSX 0x01 67 /* Decimal Floating Point */ 68 #define SPAPR_CAP_DFP 0x02 69 /* Cache Flush on Privilege Change */ 70 #define SPAPR_CAP_CFPC 0x03 71 /* Speculation Barrier Bounds Checking */ 72 #define SPAPR_CAP_SBBC 0x04 73 /* Indirect Branch Serialisation */ 74 #define SPAPR_CAP_IBS 0x05 75 /* HPT Maximum Page Size (encoded as a shift) */ 76 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 77 /* Nested KVM-HV */ 78 #define SPAPR_CAP_NESTED_KVM_HV 0x07 79 /* Large Decrementer */ 80 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 81 /* Count Cache Flush Assist HW Instruction */ 82 #define SPAPR_CAP_CCF_ASSIST 0x09 83 /* Implements PAPR FWNMI option */ 84 #define SPAPR_CAP_FWNMI 0x0A 85 /* Num Caps */ 86 #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1) 87 88 /* 89 * Capability Values 90 */ 91 /* Bool Caps */ 92 #define SPAPR_CAP_OFF 0x00 93 #define SPAPR_CAP_ON 0x01 94 95 /* Custom Caps */ 96 97 /* Generic */ 98 #define SPAPR_CAP_BROKEN 0x00 99 #define SPAPR_CAP_WORKAROUND 0x01 100 #define SPAPR_CAP_FIXED 0x02 101 /* SPAPR_CAP_IBS (cap-ibs) */ 102 #define SPAPR_CAP_FIXED_IBS 0x02 103 #define SPAPR_CAP_FIXED_CCD 0x03 104 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 105 106 #define FDT_MAX_SIZE 0x100000 107 108 /* 109 * NUMA related macros. MAX_DISTANCE_REF_POINTS was taken 110 * from Linux kernel arch/powerpc/mm/numa.h. It represents the 111 * amount of associativity domains for non-CPU resources. 112 * 113 * NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 114 * array for any non-CPU resource. 115 * 116 * VCPU_ASSOC_SIZE represents the size of ibm,associativity array 117 * for CPUs, which has an extra element (vcpu_id) in the end. 118 */ 119 #define MAX_DISTANCE_REF_POINTS 4 120 #define NUMA_ASSOC_SIZE (MAX_DISTANCE_REF_POINTS + 1) 121 #define VCPU_ASSOC_SIZE (NUMA_ASSOC_SIZE + 1) 122 123 typedef struct SpaprCapabilities SpaprCapabilities; 124 struct SpaprCapabilities { 125 uint8_t caps[SPAPR_CAP_NUM]; 126 }; 127 128 /** 129 * SpaprMachineClass: 130 */ 131 struct SpaprMachineClass { 132 /*< private >*/ 133 MachineClass parent_class; 134 135 /*< public >*/ 136 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 137 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 138 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 139 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 140 bool pre_2_10_has_unused_icps; 141 bool legacy_irq_allocation; 142 uint32_t nr_xirqs; 143 bool broken_host_serial_model; /* present real host info to the guest */ 144 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 145 bool linux_pci_probe; 146 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 147 hwaddr rma_limit; /* clamp the RMA to this size */ 148 bool pre_5_1_assoc_refpoints; 149 150 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 151 uint64_t *buid, hwaddr *pio, 152 hwaddr *mmio32, hwaddr *mmio64, 153 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 154 hwaddr *nv2atsd, Error **errp); 155 SpaprResizeHpt resize_hpt_default; 156 SpaprCapabilities default_caps; 157 SpaprIrq *irq; 158 }; 159 160 /** 161 * SpaprMachineState: 162 */ 163 struct SpaprMachineState { 164 /*< private >*/ 165 MachineState parent_obj; 166 167 struct SpaprVioBus *vio_bus; 168 QLIST_HEAD(, SpaprPhbState) phbs; 169 struct SpaprNvram *nvram; 170 SpaprRtcState rtc; 171 172 SpaprResizeHpt resize_hpt; 173 void *htab; 174 uint32_t htab_shift; 175 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 176 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 177 178 hwaddr rma_size; 179 uint32_t fdt_size; 180 uint32_t fdt_initial_size; 181 void *fdt_blob; 182 long kernel_size; 183 bool kernel_le; 184 uint64_t kernel_addr; 185 uint32_t initrd_base; 186 long initrd_size; 187 uint64_t rtc_offset; /* Now used only during incoming migration */ 188 struct PPCTimebase tb; 189 bool has_graphics; 190 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 191 192 Notifier epow_notifier; 193 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 194 bool use_hotplug_event_source; 195 SpaprEventSource *event_sources; 196 197 /* ibm,client-architecture-support option negotiation */ 198 bool cas_pre_isa3_guest; 199 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 200 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 201 uint32_t max_compat_pvr; 202 203 /* Migration state */ 204 int htab_save_index; 205 bool htab_first_pass; 206 int htab_fd; 207 208 /* Pending DIMM unplug cache. It is populated when a LMB 209 * unplug starts. It can be regenerated if a migration 210 * occurs during the unplug process. */ 211 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 212 213 /* State related to FWNMI option */ 214 215 /* System Reset and Machine Check Notification Routine addresses 216 * registered by "ibm,nmi-register" RTAS call. 217 */ 218 target_ulong fwnmi_system_reset_addr; 219 target_ulong fwnmi_machine_check_addr; 220 221 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 222 * set to -1 if a FWNMI machine check is not in progress, else is set to 223 * the CPU that was delivered the machine check, and is set back to -1 224 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 225 * to synchronize other CPUs. 226 */ 227 int fwnmi_machine_check_interlock; 228 QemuCond fwnmi_machine_check_interlock_cond; 229 230 /*< public >*/ 231 char *kvm_type; 232 char *host_model; 233 char *host_serial; 234 235 int32_t irq_map_nr; 236 unsigned long *irq_map; 237 SpaprIrq *irq; 238 qemu_irq *qirqs; 239 SpaprInterruptController *active_intc; 240 ICSState *ics; 241 SpaprXive *xive; 242 243 bool cmd_line_caps[SPAPR_CAP_NUM]; 244 SpaprCapabilities def, eff, mig; 245 246 unsigned gpu_numa_id; 247 SpaprTpmProxy *tpm_proxy; 248 249 uint32_t numa_assoc_array[MAX_NODES][NUMA_ASSOC_SIZE]; 250 251 Error *fwnmi_migration_blocker; 252 }; 253 254 #define H_SUCCESS 0 255 #define H_BUSY 1 /* Hardware busy -- retry later */ 256 #define H_CLOSED 2 /* Resource closed */ 257 #define H_NOT_AVAILABLE 3 258 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 259 #define H_PARTIAL 5 260 #define H_IN_PROGRESS 14 /* Kind of like busy */ 261 #define H_PAGE_REGISTERED 15 262 #define H_PARTIAL_STORE 16 263 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 264 #define H_CONTINUE 18 /* Returned from H_Join on success */ 265 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 266 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 267 is a good time to retry */ 268 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 269 is a good time to retry */ 270 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 271 is a good time to retry */ 272 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 273 is a good time to retry */ 274 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 275 is a good time to retry */ 276 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 277 is a good time to retry */ 278 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 279 #define H_HARDWARE -1 /* Hardware error */ 280 #define H_FUNCTION -2 /* Function not supported */ 281 #define H_PRIVILEGE -3 /* Caller not privileged */ 282 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 283 #define H_BAD_MODE -5 /* Illegal msr value */ 284 #define H_PTEG_FULL -6 /* PTEG is full */ 285 #define H_NOT_FOUND -7 /* PTE was not found" */ 286 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 287 #define H_NO_MEM -9 288 #define H_AUTHORITY -10 289 #define H_PERMISSION -11 290 #define H_DROPPED -12 291 #define H_SOURCE_PARM -13 292 #define H_DEST_PARM -14 293 #define H_REMOTE_PARM -15 294 #define H_RESOURCE -16 295 #define H_ADAPTER_PARM -17 296 #define H_RH_PARM -18 297 #define H_RCQ_PARM -19 298 #define H_SCQ_PARM -20 299 #define H_EQ_PARM -21 300 #define H_RT_PARM -22 301 #define H_ST_PARM -23 302 #define H_SIGT_PARM -24 303 #define H_TOKEN_PARM -25 304 #define H_MLENGTH_PARM -27 305 #define H_MEM_PARM -28 306 #define H_MEM_ACCESS_PARM -29 307 #define H_ATTR_PARM -30 308 #define H_PORT_PARM -31 309 #define H_MCG_PARM -32 310 #define H_VL_PARM -33 311 #define H_TSIZE_PARM -34 312 #define H_TRACE_PARM -35 313 314 #define H_MASK_PARM -37 315 #define H_MCG_FULL -38 316 #define H_ALIAS_EXIST -39 317 #define H_P_COUNTER -40 318 #define H_TABLE_FULL -41 319 #define H_ALT_TABLE -42 320 #define H_MR_CONDITION -43 321 #define H_NOT_ENOUGH_RESOURCES -44 322 #define H_R_STATE -45 323 #define H_RESCINDEND -46 324 #define H_P2 -55 325 #define H_P3 -56 326 #define H_P4 -57 327 #define H_P5 -58 328 #define H_P6 -59 329 #define H_P7 -60 330 #define H_P8 -61 331 #define H_P9 -62 332 #define H_OVERLAP -68 333 #define H_UNSUPPORTED_FLAG -256 334 #define H_MULTI_THREADS_ACTIVE -9005 335 336 337 /* Long Busy is a condition that can be returned by the firmware 338 * when a call cannot be completed now, but the identical call 339 * should be retried later. This prevents calls blocking in the 340 * firmware for long periods of time. Annoyingly the firmware can return 341 * a range of return codes, hinting at how long we should wait before 342 * retrying. If you don't care for the hint, the macro below is a good 343 * way to check for the long_busy return codes 344 */ 345 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 346 && (x <= H_LONG_BUSY_END_RANGE)) 347 348 /* Flags */ 349 #define H_LARGE_PAGE (1ULL<<(63-16)) 350 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 351 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 352 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 353 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 354 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 355 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 356 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 357 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 358 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 359 #define H_ANDCOND (1ULL<<(63-33)) 360 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 361 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 362 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 363 #define H_COPY_PAGE (1ULL<<(63-49)) 364 #define H_N (1ULL<<(63-61)) 365 #define H_PP1 (1ULL<<(63-62)) 366 #define H_PP2 (1ULL<<(63-63)) 367 368 /* Values for 2nd argument to H_SET_MODE */ 369 #define H_SET_MODE_RESOURCE_SET_CIABR 1 370 #define H_SET_MODE_RESOURCE_SET_DAWR 2 371 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 372 #define H_SET_MODE_RESOURCE_LE 4 373 374 /* Flags for H_SET_MODE_RESOURCE_LE */ 375 #define H_SET_MODE_ENDIAN_BIG 0 376 #define H_SET_MODE_ENDIAN_LITTLE 1 377 378 /* VASI States */ 379 #define H_VASI_INVALID 0 380 #define H_VASI_ENABLED 1 381 #define H_VASI_ABORTED 2 382 #define H_VASI_SUSPENDING 3 383 #define H_VASI_SUSPENDED 4 384 #define H_VASI_RESUMED 5 385 #define H_VASI_COMPLETED 6 386 387 /* DABRX flags */ 388 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 389 #define H_DABRX_KERNEL (1ULL<<(63-62)) 390 #define H_DABRX_USER (1ULL<<(63-63)) 391 392 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 393 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 394 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 395 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 396 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 397 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 398 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 399 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 400 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 401 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 402 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 403 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 404 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 405 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 406 407 /* Each control block has to be on a 4K boundary */ 408 #define H_CB_ALIGNMENT 4096 409 410 /* pSeries hypervisor opcodes */ 411 #define H_REMOVE 0x04 412 #define H_ENTER 0x08 413 #define H_READ 0x0c 414 #define H_CLEAR_MOD 0x10 415 #define H_CLEAR_REF 0x14 416 #define H_PROTECT 0x18 417 #define H_GET_TCE 0x1c 418 #define H_PUT_TCE 0x20 419 #define H_SET_SPRG0 0x24 420 #define H_SET_DABR 0x28 421 #define H_PAGE_INIT 0x2c 422 #define H_SET_ASR 0x30 423 #define H_ASR_ON 0x34 424 #define H_ASR_OFF 0x38 425 #define H_LOGICAL_CI_LOAD 0x3c 426 #define H_LOGICAL_CI_STORE 0x40 427 #define H_LOGICAL_CACHE_LOAD 0x44 428 #define H_LOGICAL_CACHE_STORE 0x48 429 #define H_LOGICAL_ICBI 0x4c 430 #define H_LOGICAL_DCBF 0x50 431 #define H_GET_TERM_CHAR 0x54 432 #define H_PUT_TERM_CHAR 0x58 433 #define H_REAL_TO_LOGICAL 0x5c 434 #define H_HYPERVISOR_DATA 0x60 435 #define H_EOI 0x64 436 #define H_CPPR 0x68 437 #define H_IPI 0x6c 438 #define H_IPOLL 0x70 439 #define H_XIRR 0x74 440 #define H_PERFMON 0x7c 441 #define H_MIGRATE_DMA 0x78 442 #define H_REGISTER_VPA 0xDC 443 #define H_CEDE 0xE0 444 #define H_CONFER 0xE4 445 #define H_PROD 0xE8 446 #define H_GET_PPP 0xEC 447 #define H_SET_PPP 0xF0 448 #define H_PURR 0xF4 449 #define H_PIC 0xF8 450 #define H_REG_CRQ 0xFC 451 #define H_FREE_CRQ 0x100 452 #define H_VIO_SIGNAL 0x104 453 #define H_SEND_CRQ 0x108 454 #define H_COPY_RDMA 0x110 455 #define H_REGISTER_LOGICAL_LAN 0x114 456 #define H_FREE_LOGICAL_LAN 0x118 457 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 458 #define H_SEND_LOGICAL_LAN 0x120 459 #define H_BULK_REMOVE 0x124 460 #define H_MULTICAST_CTRL 0x130 461 #define H_SET_XDABR 0x134 462 #define H_STUFF_TCE 0x138 463 #define H_PUT_TCE_INDIRECT 0x13C 464 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 465 #define H_VTERM_PARTNER_INFO 0x150 466 #define H_REGISTER_VTERM 0x154 467 #define H_FREE_VTERM 0x158 468 #define H_RESET_EVENTS 0x15C 469 #define H_ALLOC_RESOURCE 0x160 470 #define H_FREE_RESOURCE 0x164 471 #define H_MODIFY_QP 0x168 472 #define H_QUERY_QP 0x16C 473 #define H_REREGISTER_PMR 0x170 474 #define H_REGISTER_SMR 0x174 475 #define H_QUERY_MR 0x178 476 #define H_QUERY_MW 0x17C 477 #define H_QUERY_HCA 0x180 478 #define H_QUERY_PORT 0x184 479 #define H_MODIFY_PORT 0x188 480 #define H_DEFINE_AQP1 0x18C 481 #define H_GET_TRACE_BUFFER 0x190 482 #define H_DEFINE_AQP0 0x194 483 #define H_RESIZE_MR 0x198 484 #define H_ATTACH_MCQP 0x19C 485 #define H_DETACH_MCQP 0x1A0 486 #define H_CREATE_RPT 0x1A4 487 #define H_REMOVE_RPT 0x1A8 488 #define H_REGISTER_RPAGES 0x1AC 489 #define H_DISABLE_AND_GETC 0x1B0 490 #define H_ERROR_DATA 0x1B4 491 #define H_GET_HCA_INFO 0x1B8 492 #define H_GET_PERF_COUNT 0x1BC 493 #define H_MANAGE_TRACE 0x1C0 494 #define H_GET_CPU_CHARACTERISTICS 0x1C8 495 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 496 #define H_QUERY_INT_STATE 0x1E4 497 #define H_POLL_PENDING 0x1D8 498 #define H_ILLAN_ATTRIBUTES 0x244 499 #define H_MODIFY_HEA_QP 0x250 500 #define H_QUERY_HEA_QP 0x254 501 #define H_QUERY_HEA 0x258 502 #define H_QUERY_HEA_PORT 0x25C 503 #define H_MODIFY_HEA_PORT 0x260 504 #define H_REG_BCMC 0x264 505 #define H_DEREG_BCMC 0x268 506 #define H_REGISTER_HEA_RPAGES 0x26C 507 #define H_DISABLE_AND_GET_HEA 0x270 508 #define H_GET_HEA_INFO 0x274 509 #define H_ALLOC_HEA_RESOURCE 0x278 510 #define H_ADD_CONN 0x284 511 #define H_DEL_CONN 0x288 512 #define H_JOIN 0x298 513 #define H_VASI_STATE 0x2A4 514 #define H_ENABLE_CRQ 0x2B0 515 #define H_GET_EM_PARMS 0x2B8 516 #define H_SET_MPP 0x2D0 517 #define H_GET_MPP 0x2D4 518 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 519 #define H_XIRR_X 0x2FC 520 #define H_RANDOM 0x300 521 #define H_SET_MODE 0x31C 522 #define H_RESIZE_HPT_PREPARE 0x36C 523 #define H_RESIZE_HPT_COMMIT 0x370 524 #define H_CLEAN_SLB 0x374 525 #define H_INVALIDATE_PID 0x378 526 #define H_REGISTER_PROC_TBL 0x37C 527 #define H_SIGNAL_SYS_RESET 0x380 528 529 #define H_INT_GET_SOURCE_INFO 0x3A8 530 #define H_INT_SET_SOURCE_CONFIG 0x3AC 531 #define H_INT_GET_SOURCE_CONFIG 0x3B0 532 #define H_INT_GET_QUEUE_INFO 0x3B4 533 #define H_INT_SET_QUEUE_CONFIG 0x3B8 534 #define H_INT_GET_QUEUE_CONFIG 0x3BC 535 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 536 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 537 #define H_INT_ESB 0x3C8 538 #define H_INT_SYNC 0x3CC 539 #define H_INT_RESET 0x3D0 540 #define H_SCM_READ_METADATA 0x3E4 541 #define H_SCM_WRITE_METADATA 0x3E8 542 #define H_SCM_BIND_MEM 0x3EC 543 #define H_SCM_UNBIND_MEM 0x3F0 544 #define H_SCM_UNBIND_ALL 0x3FC 545 546 #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL 547 548 /* The hcalls above are standardized in PAPR and implemented by pHyp 549 * as well. 550 * 551 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 552 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 553 * for "platform-specific" hcalls. 554 */ 555 #define KVMPPC_HCALL_BASE 0xf000 556 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 557 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 558 /* Client Architecture support */ 559 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 560 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 561 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 562 563 /* 564 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 565 * Secure VM mode via an Ultravisor / Protected Execution Facility 566 */ 567 #define SVM_HCALL_BASE 0xEF00 568 #define SVM_H_TPM_COMM 0xEF10 569 #define SVM_HCALL_MAX SVM_H_TPM_COMM 570 571 572 typedef struct SpaprDeviceTreeUpdateHeader { 573 uint32_t version_id; 574 } SpaprDeviceTreeUpdateHeader; 575 576 #define hcall_dprintf(fmt, ...) \ 577 do { \ 578 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 579 } while (0) 580 581 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 582 target_ulong opcode, 583 target_ulong *args); 584 585 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 586 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 587 target_ulong *args); 588 589 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 590 SpaprMachineState *spapr, 591 target_ulong addr, 592 target_ulong fdt_bufsize); 593 594 /* Virtual Processor Area structure constants */ 595 #define VPA_MIN_SIZE 640 596 #define VPA_SIZE_OFFSET 0x4 597 #define VPA_SHARED_PROC_OFFSET 0x9 598 #define VPA_SHARED_PROC_VAL 0x2 599 #define VPA_DISPATCH_COUNTER 0x100 600 601 /* ibm,set-eeh-option */ 602 #define RTAS_EEH_DISABLE 0 603 #define RTAS_EEH_ENABLE 1 604 #define RTAS_EEH_THAW_IO 2 605 #define RTAS_EEH_THAW_DMA 3 606 607 /* ibm,get-config-addr-info2 */ 608 #define RTAS_GET_PE_ADDR 0 609 #define RTAS_GET_PE_MODE 1 610 #define RTAS_PE_MODE_NONE 0 611 #define RTAS_PE_MODE_NOT_SHARED 1 612 #define RTAS_PE_MODE_SHARED 2 613 614 /* ibm,read-slot-reset-state2 */ 615 #define RTAS_EEH_PE_STATE_NORMAL 0 616 #define RTAS_EEH_PE_STATE_RESET 1 617 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 618 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 619 #define RTAS_EEH_PE_STATE_UNAVAIL 5 620 #define RTAS_EEH_NOT_SUPPORT 0 621 #define RTAS_EEH_SUPPORT 1 622 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 623 #define RTAS_EEH_PE_RECOVER_INFO 0 624 625 /* ibm,set-slot-reset */ 626 #define RTAS_SLOT_RESET_DEACTIVATE 0 627 #define RTAS_SLOT_RESET_HOT 1 628 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 629 630 /* ibm,slot-error-detail */ 631 #define RTAS_SLOT_TEMP_ERR_LOG 1 632 #define RTAS_SLOT_PERM_ERR_LOG 2 633 634 /* RTAS return codes */ 635 #define RTAS_OUT_SUCCESS 0 636 #define RTAS_OUT_NO_ERRORS_FOUND 1 637 #define RTAS_OUT_HW_ERROR -1 638 #define RTAS_OUT_BUSY -2 639 #define RTAS_OUT_PARAM_ERROR -3 640 #define RTAS_OUT_NOT_SUPPORTED -3 641 #define RTAS_OUT_NO_SUCH_INDICATOR -3 642 #define RTAS_OUT_NOT_AUTHORIZED -9002 643 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 644 645 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 646 #define RTAS_DDW_PGSIZE_4K 0x01 647 #define RTAS_DDW_PGSIZE_64K 0x02 648 #define RTAS_DDW_PGSIZE_16M 0x04 649 #define RTAS_DDW_PGSIZE_32M 0x08 650 #define RTAS_DDW_PGSIZE_64M 0x10 651 #define RTAS_DDW_PGSIZE_128M 0x20 652 #define RTAS_DDW_PGSIZE_256M 0x40 653 #define RTAS_DDW_PGSIZE_16G 0x80 654 655 /* RTAS tokens */ 656 #define RTAS_TOKEN_BASE 0x2000 657 658 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 659 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 660 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 661 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 662 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 663 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 664 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 665 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 666 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 667 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 668 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 669 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 670 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 671 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 672 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 673 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 674 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 675 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 676 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 677 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 678 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 679 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 680 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 681 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 682 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 683 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 684 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 685 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 686 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 687 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 688 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 689 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 690 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 691 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 692 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 693 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 694 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 695 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 696 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 697 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 698 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 699 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 700 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 701 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 702 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 703 704 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 705 706 /* RTAS ibm,get-system-parameter token values */ 707 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 708 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 709 #define RTAS_SYSPARM_UUID 48 710 711 /* RTAS indicator/sensor types 712 * 713 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 714 * 715 * NOTE: currently only DR-related sensors are implemented here 716 */ 717 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 718 #define RTAS_SENSOR_TYPE_DR 9002 719 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 720 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 721 722 /* Possible values for the platform-processor-diagnostics-run-mode parameter 723 * of the RTAS ibm,get-system-parameter call. 724 */ 725 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 726 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 727 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 728 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 729 730 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 731 { 732 return addr & ~0xF000000000000000ULL; 733 } 734 735 static inline uint32_t rtas_ld(target_ulong phys, int n) 736 { 737 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 738 } 739 740 static inline uint64_t rtas_ldq(target_ulong phys, int n) 741 { 742 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 743 } 744 745 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 746 { 747 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 748 } 749 750 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 751 uint32_t token, 752 uint32_t nargs, target_ulong args, 753 uint32_t nret, target_ulong rets); 754 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 755 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 756 uint32_t token, uint32_t nargs, target_ulong args, 757 uint32_t nret, target_ulong rets); 758 void spapr_dt_rtas_tokens(void *fdt, int rtas); 759 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 760 761 #define SPAPR_TCE_PAGE_SHIFT 12 762 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 763 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 764 765 #define SPAPR_VIO_BASE_LIOBN 0x00000000 766 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 767 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 768 (0x80000000 | ((phb_index) << 8) | (window_num)) 769 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 770 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 771 772 #define RTAS_SIZE 2048 773 #define RTAS_ERROR_LOG_MAX 2048 774 775 /* Offset from rtas-base where error log is placed */ 776 #define RTAS_ERROR_LOG_OFFSET 0x30 777 778 #define RTAS_EVENT_SCAN_RATE 1 779 780 /* This helper should be used to encode interrupt specifiers when the related 781 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 782 * VIO devices, RTAS event sources and PHBs). 783 */ 784 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 785 { 786 intspec[0] = cpu_to_be32(irq); 787 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 788 } 789 790 typedef struct SpaprTceTable SpaprTceTable; 791 792 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 793 #define SPAPR_TCE_TABLE(obj) \ 794 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 795 796 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 797 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 798 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 799 800 struct SpaprTceTable { 801 DeviceState parent; 802 uint32_t liobn; 803 uint32_t nb_table; 804 uint64_t bus_offset; 805 uint32_t page_shift; 806 uint64_t *table; 807 uint32_t mig_nb_table; 808 uint64_t *mig_table; 809 bool bypass; 810 bool need_vfio; 811 bool skipping_replay; 812 int fd; 813 MemoryRegion root; 814 IOMMUMemoryRegion iommu; 815 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 816 QLIST_ENTRY(SpaprTceTable) list; 817 }; 818 819 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 820 821 struct SpaprEventLogEntry { 822 uint32_t summary; 823 uint32_t extended_length; 824 void *extended_log; 825 QTAILQ_ENTRY(SpaprEventLogEntry) next; 826 }; 827 828 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 829 void spapr_events_init(SpaprMachineState *sm); 830 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 831 void close_htab_fd(SpaprMachineState *spapr); 832 void spapr_setup_hpt(SpaprMachineState *spapr); 833 void spapr_free_hpt(SpaprMachineState *spapr); 834 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 835 void spapr_tce_table_enable(SpaprTceTable *tcet, 836 uint32_t page_shift, uint64_t bus_offset, 837 uint32_t nb_table); 838 void spapr_tce_table_disable(SpaprTceTable *tcet); 839 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 840 841 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 842 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 843 uint32_t liobn, uint64_t window, uint32_t size); 844 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 845 SpaprTceTable *tcet); 846 void spapr_pci_switch_vga(bool big_endian); 847 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 848 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 849 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 850 uint32_t count); 851 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 852 uint32_t count); 853 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 854 uint32_t count, uint32_t index); 855 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 856 uint32_t count, uint32_t index); 857 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 858 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 859 Error **errp); 860 void spapr_clear_pending_events(SpaprMachineState *spapr); 861 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 862 int spapr_max_server_number(SpaprMachineState *spapr); 863 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 864 uint64_t pte0, uint64_t pte1); 865 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 866 867 /* DRC callbacks. */ 868 void spapr_core_release(DeviceState *dev); 869 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 870 void *fdt, int *fdt_start_offset, Error **errp); 871 void spapr_lmb_release(DeviceState *dev); 872 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 873 void *fdt, int *fdt_start_offset, Error **errp); 874 void spapr_phb_release(DeviceState *dev); 875 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 876 void *fdt, int *fdt_start_offset, Error **errp); 877 878 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 879 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 880 881 #define TYPE_SPAPR_RNG "spapr-rng" 882 883 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 884 885 /* 886 * This defines the maximum number of DIMM slots we can have for sPAPR 887 * guest. This is not defined by sPAPR but we are defining it to 32 slots 888 * based on default number of slots provided by PowerPC kernel. 889 */ 890 #define SPAPR_MAX_RAM_SLOTS 32 891 892 /* 1GB alignment for hotplug memory region */ 893 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 894 895 /* 896 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 897 * property under ibm,dynamic-reconfiguration-memory node. 898 */ 899 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 900 901 /* 902 * Defines for flag value in ibm,dynamic-memory property under 903 * ibm,dynamic-reconfiguration-memory node. 904 */ 905 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 906 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 907 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 908 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 909 910 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 911 912 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 913 914 int spapr_get_vcpu_id(PowerPCCPU *cpu); 915 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 916 PowerPCCPU *spapr_find_cpu(int vcpu_id); 917 918 int spapr_caps_pre_load(void *opaque); 919 int spapr_caps_pre_save(void *opaque); 920 921 /* 922 * Handling of optional capabilities 923 */ 924 extern const VMStateDescription vmstate_spapr_cap_htm; 925 extern const VMStateDescription vmstate_spapr_cap_vsx; 926 extern const VMStateDescription vmstate_spapr_cap_dfp; 927 extern const VMStateDescription vmstate_spapr_cap_cfpc; 928 extern const VMStateDescription vmstate_spapr_cap_sbbc; 929 extern const VMStateDescription vmstate_spapr_cap_ibs; 930 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 931 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 932 extern const VMStateDescription vmstate_spapr_cap_large_decr; 933 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 934 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 935 936 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 937 { 938 return spapr->eff.caps[cap]; 939 } 940 941 void spapr_caps_init(SpaprMachineState *spapr); 942 void spapr_caps_apply(SpaprMachineState *spapr); 943 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 944 void spapr_caps_add_properties(SpaprMachineClass *smc); 945 int spapr_caps_post_migration(SpaprMachineState *spapr); 946 947 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 948 Error **errp); 949 /* 950 * XIVE definitions 951 */ 952 #define SPAPR_OV5_XIVE_LEGACY 0x0 953 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 954 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 955 956 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 957 hwaddr spapr_get_rtas_addr(void); 958 #endif /* HW_SPAPR_H */ 959