1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 12 #include "hw/ppc/xics.h" /* For ICSState */ 13 14 struct SpaprVioBus; 15 struct SpaprPhbState; 16 struct SpaprNvram; 17 18 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 19 typedef struct SpaprEventSource SpaprEventSource; 20 typedef struct SpaprPendingHpt SpaprPendingHpt; 21 22 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 23 #define SPAPR_ENTRY_POINT 0x100 24 25 #define SPAPR_TIMEBASE_FREQ 512000000ULL 26 27 #define TYPE_SPAPR_RTC "spapr-rtc" 28 29 #define SPAPR_RTC(obj) \ 30 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 31 32 typedef struct SpaprRtcState SpaprRtcState; 33 struct SpaprRtcState { 34 /*< private >*/ 35 DeviceState parent_obj; 36 int64_t ns_offset; 37 }; 38 39 typedef struct SpaprDimmState SpaprDimmState; 40 typedef struct SpaprMachineClass SpaprMachineClass; 41 42 #define TYPE_SPAPR_MACHINE "spapr-machine" 43 #define SPAPR_MACHINE(obj) \ 44 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 45 #define SPAPR_MACHINE_GET_CLASS(obj) \ 46 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 47 #define SPAPR_MACHINE_CLASS(klass) \ 48 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 49 50 typedef enum { 51 SPAPR_RESIZE_HPT_DEFAULT = 0, 52 SPAPR_RESIZE_HPT_DISABLED, 53 SPAPR_RESIZE_HPT_ENABLED, 54 SPAPR_RESIZE_HPT_REQUIRED, 55 } SpaprResizeHpt; 56 57 /** 58 * Capabilities 59 */ 60 61 /* Hardware Transactional Memory */ 62 #define SPAPR_CAP_HTM 0x00 63 /* Vector Scalar Extensions */ 64 #define SPAPR_CAP_VSX 0x01 65 /* Decimal Floating Point */ 66 #define SPAPR_CAP_DFP 0x02 67 /* Cache Flush on Privilege Change */ 68 #define SPAPR_CAP_CFPC 0x03 69 /* Speculation Barrier Bounds Checking */ 70 #define SPAPR_CAP_SBBC 0x04 71 /* Indirect Branch Serialisation */ 72 #define SPAPR_CAP_IBS 0x05 73 /* HPT Maximum Page Size (encoded as a shift) */ 74 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 75 /* Nested KVM-HV */ 76 #define SPAPR_CAP_NESTED_KVM_HV 0x07 77 /* Large Decrementer */ 78 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 79 /* Count Cache Flush Assist HW Instruction */ 80 #define SPAPR_CAP_CCF_ASSIST 0x09 81 /* Num Caps */ 82 #define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) 83 84 /* 85 * Capability Values 86 */ 87 /* Bool Caps */ 88 #define SPAPR_CAP_OFF 0x00 89 #define SPAPR_CAP_ON 0x01 90 91 /* Custom Caps */ 92 93 /* Generic */ 94 #define SPAPR_CAP_BROKEN 0x00 95 #define SPAPR_CAP_WORKAROUND 0x01 96 #define SPAPR_CAP_FIXED 0x02 97 /* SPAPR_CAP_IBS (cap-ibs) */ 98 #define SPAPR_CAP_FIXED_IBS 0x02 99 #define SPAPR_CAP_FIXED_CCD 0x03 100 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 101 102 typedef struct SpaprCapabilities SpaprCapabilities; 103 struct SpaprCapabilities { 104 uint8_t caps[SPAPR_CAP_NUM]; 105 }; 106 107 /** 108 * SpaprMachineClass: 109 */ 110 struct SpaprMachineClass { 111 /*< private >*/ 112 MachineClass parent_class; 113 114 /*< public >*/ 115 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 116 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 117 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 118 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 119 bool pre_2_10_has_unused_icps; 120 bool legacy_irq_allocation; 121 bool broken_host_serial_model; /* present real host info to the guest */ 122 123 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 124 uint64_t *buid, hwaddr *pio, 125 hwaddr *mmio32, hwaddr *mmio64, 126 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 127 hwaddr *nv2atsd, Error **errp); 128 SpaprResizeHpt resize_hpt_default; 129 SpaprCapabilities default_caps; 130 SpaprIrq *irq; 131 }; 132 133 /** 134 * SpaprMachineState: 135 */ 136 struct SpaprMachineState { 137 /*< private >*/ 138 MachineState parent_obj; 139 140 struct SpaprVioBus *vio_bus; 141 QLIST_HEAD(, SpaprPhbState) phbs; 142 struct SpaprNvram *nvram; 143 ICSState *ics; 144 SpaprRtcState rtc; 145 146 SpaprResizeHpt resize_hpt; 147 void *htab; 148 uint32_t htab_shift; 149 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 150 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 151 152 hwaddr rma_size; 153 int vrma_adjust; 154 ssize_t rtas_size; 155 void *rtas_blob; 156 uint32_t fdt_size; 157 uint32_t fdt_initial_size; 158 void *fdt_blob; 159 long kernel_size; 160 bool kernel_le; 161 uint32_t initrd_base; 162 long initrd_size; 163 uint64_t rtc_offset; /* Now used only during incoming migration */ 164 struct PPCTimebase tb; 165 bool has_graphics; 166 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 167 168 Notifier epow_notifier; 169 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 170 bool use_hotplug_event_source; 171 SpaprEventSource *event_sources; 172 173 /* ibm,client-architecture-support option negotiation */ 174 bool cas_reboot; 175 bool cas_legacy_guest_workaround; 176 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 177 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 178 uint32_t max_compat_pvr; 179 180 /* Migration state */ 181 int htab_save_index; 182 bool htab_first_pass; 183 int htab_fd; 184 185 /* Pending DIMM unplug cache. It is populated when a LMB 186 * unplug starts. It can be regenerated if a migration 187 * occurs during the unplug process. */ 188 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 189 190 /*< public >*/ 191 char *kvm_type; 192 char *host_model; 193 char *host_serial; 194 195 int32_t irq_map_nr; 196 unsigned long *irq_map; 197 SpaprXive *xive; 198 SpaprIrq *irq; 199 qemu_irq *qirqs; 200 201 bool cmd_line_caps[SPAPR_CAP_NUM]; 202 SpaprCapabilities def, eff, mig; 203 204 unsigned gpu_numa_id; 205 }; 206 207 #define H_SUCCESS 0 208 #define H_BUSY 1 /* Hardware busy -- retry later */ 209 #define H_CLOSED 2 /* Resource closed */ 210 #define H_NOT_AVAILABLE 3 211 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 212 #define H_PARTIAL 5 213 #define H_IN_PROGRESS 14 /* Kind of like busy */ 214 #define H_PAGE_REGISTERED 15 215 #define H_PARTIAL_STORE 16 216 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 217 #define H_CONTINUE 18 /* Returned from H_Join on success */ 218 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 219 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 220 is a good time to retry */ 221 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 222 is a good time to retry */ 223 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 224 is a good time to retry */ 225 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 226 is a good time to retry */ 227 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 228 is a good time to retry */ 229 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 230 is a good time to retry */ 231 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 232 #define H_HARDWARE -1 /* Hardware error */ 233 #define H_FUNCTION -2 /* Function not supported */ 234 #define H_PRIVILEGE -3 /* Caller not privileged */ 235 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 236 #define H_BAD_MODE -5 /* Illegal msr value */ 237 #define H_PTEG_FULL -6 /* PTEG is full */ 238 #define H_NOT_FOUND -7 /* PTE was not found" */ 239 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 240 #define H_NO_MEM -9 241 #define H_AUTHORITY -10 242 #define H_PERMISSION -11 243 #define H_DROPPED -12 244 #define H_SOURCE_PARM -13 245 #define H_DEST_PARM -14 246 #define H_REMOTE_PARM -15 247 #define H_RESOURCE -16 248 #define H_ADAPTER_PARM -17 249 #define H_RH_PARM -18 250 #define H_RCQ_PARM -19 251 #define H_SCQ_PARM -20 252 #define H_EQ_PARM -21 253 #define H_RT_PARM -22 254 #define H_ST_PARM -23 255 #define H_SIGT_PARM -24 256 #define H_TOKEN_PARM -25 257 #define H_MLENGTH_PARM -27 258 #define H_MEM_PARM -28 259 #define H_MEM_ACCESS_PARM -29 260 #define H_ATTR_PARM -30 261 #define H_PORT_PARM -31 262 #define H_MCG_PARM -32 263 #define H_VL_PARM -33 264 #define H_TSIZE_PARM -34 265 #define H_TRACE_PARM -35 266 267 #define H_MASK_PARM -37 268 #define H_MCG_FULL -38 269 #define H_ALIAS_EXIST -39 270 #define H_P_COUNTER -40 271 #define H_TABLE_FULL -41 272 #define H_ALT_TABLE -42 273 #define H_MR_CONDITION -43 274 #define H_NOT_ENOUGH_RESOURCES -44 275 #define H_R_STATE -45 276 #define H_RESCINDEND -46 277 #define H_P2 -55 278 #define H_P3 -56 279 #define H_P4 -57 280 #define H_P5 -58 281 #define H_P6 -59 282 #define H_P7 -60 283 #define H_P8 -61 284 #define H_P9 -62 285 #define H_UNSUPPORTED_FLAG -256 286 #define H_MULTI_THREADS_ACTIVE -9005 287 288 289 /* Long Busy is a condition that can be returned by the firmware 290 * when a call cannot be completed now, but the identical call 291 * should be retried later. This prevents calls blocking in the 292 * firmware for long periods of time. Annoyingly the firmware can return 293 * a range of return codes, hinting at how long we should wait before 294 * retrying. If you don't care for the hint, the macro below is a good 295 * way to check for the long_busy return codes 296 */ 297 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 298 && (x <= H_LONG_BUSY_END_RANGE)) 299 300 /* Flags */ 301 #define H_LARGE_PAGE (1ULL<<(63-16)) 302 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 303 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 304 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 305 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 306 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 307 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 308 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 309 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 310 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 311 #define H_ANDCOND (1ULL<<(63-33)) 312 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 313 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 314 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 315 #define H_COPY_PAGE (1ULL<<(63-49)) 316 #define H_N (1ULL<<(63-61)) 317 #define H_PP1 (1ULL<<(63-62)) 318 #define H_PP2 (1ULL<<(63-63)) 319 320 /* Values for 2nd argument to H_SET_MODE */ 321 #define H_SET_MODE_RESOURCE_SET_CIABR 1 322 #define H_SET_MODE_RESOURCE_SET_DAWR 2 323 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 324 #define H_SET_MODE_RESOURCE_LE 4 325 326 /* Flags for H_SET_MODE_RESOURCE_LE */ 327 #define H_SET_MODE_ENDIAN_BIG 0 328 #define H_SET_MODE_ENDIAN_LITTLE 1 329 330 /* VASI States */ 331 #define H_VASI_INVALID 0 332 #define H_VASI_ENABLED 1 333 #define H_VASI_ABORTED 2 334 #define H_VASI_SUSPENDING 3 335 #define H_VASI_SUSPENDED 4 336 #define H_VASI_RESUMED 5 337 #define H_VASI_COMPLETED 6 338 339 /* DABRX flags */ 340 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 341 #define H_DABRX_KERNEL (1ULL<<(63-62)) 342 #define H_DABRX_USER (1ULL<<(63-63)) 343 344 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 345 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 346 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 347 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 348 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 349 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 350 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 351 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 352 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 353 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 354 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 355 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 356 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 357 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 358 359 /* Each control block has to be on a 4K boundary */ 360 #define H_CB_ALIGNMENT 4096 361 362 /* pSeries hypervisor opcodes */ 363 #define H_REMOVE 0x04 364 #define H_ENTER 0x08 365 #define H_READ 0x0c 366 #define H_CLEAR_MOD 0x10 367 #define H_CLEAR_REF 0x14 368 #define H_PROTECT 0x18 369 #define H_GET_TCE 0x1c 370 #define H_PUT_TCE 0x20 371 #define H_SET_SPRG0 0x24 372 #define H_SET_DABR 0x28 373 #define H_PAGE_INIT 0x2c 374 #define H_SET_ASR 0x30 375 #define H_ASR_ON 0x34 376 #define H_ASR_OFF 0x38 377 #define H_LOGICAL_CI_LOAD 0x3c 378 #define H_LOGICAL_CI_STORE 0x40 379 #define H_LOGICAL_CACHE_LOAD 0x44 380 #define H_LOGICAL_CACHE_STORE 0x48 381 #define H_LOGICAL_ICBI 0x4c 382 #define H_LOGICAL_DCBF 0x50 383 #define H_GET_TERM_CHAR 0x54 384 #define H_PUT_TERM_CHAR 0x58 385 #define H_REAL_TO_LOGICAL 0x5c 386 #define H_HYPERVISOR_DATA 0x60 387 #define H_EOI 0x64 388 #define H_CPPR 0x68 389 #define H_IPI 0x6c 390 #define H_IPOLL 0x70 391 #define H_XIRR 0x74 392 #define H_PERFMON 0x7c 393 #define H_MIGRATE_DMA 0x78 394 #define H_REGISTER_VPA 0xDC 395 #define H_CEDE 0xE0 396 #define H_CONFER 0xE4 397 #define H_PROD 0xE8 398 #define H_GET_PPP 0xEC 399 #define H_SET_PPP 0xF0 400 #define H_PURR 0xF4 401 #define H_PIC 0xF8 402 #define H_REG_CRQ 0xFC 403 #define H_FREE_CRQ 0x100 404 #define H_VIO_SIGNAL 0x104 405 #define H_SEND_CRQ 0x108 406 #define H_COPY_RDMA 0x110 407 #define H_REGISTER_LOGICAL_LAN 0x114 408 #define H_FREE_LOGICAL_LAN 0x118 409 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 410 #define H_SEND_LOGICAL_LAN 0x120 411 #define H_BULK_REMOVE 0x124 412 #define H_MULTICAST_CTRL 0x130 413 #define H_SET_XDABR 0x134 414 #define H_STUFF_TCE 0x138 415 #define H_PUT_TCE_INDIRECT 0x13C 416 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 417 #define H_VTERM_PARTNER_INFO 0x150 418 #define H_REGISTER_VTERM 0x154 419 #define H_FREE_VTERM 0x158 420 #define H_RESET_EVENTS 0x15C 421 #define H_ALLOC_RESOURCE 0x160 422 #define H_FREE_RESOURCE 0x164 423 #define H_MODIFY_QP 0x168 424 #define H_QUERY_QP 0x16C 425 #define H_REREGISTER_PMR 0x170 426 #define H_REGISTER_SMR 0x174 427 #define H_QUERY_MR 0x178 428 #define H_QUERY_MW 0x17C 429 #define H_QUERY_HCA 0x180 430 #define H_QUERY_PORT 0x184 431 #define H_MODIFY_PORT 0x188 432 #define H_DEFINE_AQP1 0x18C 433 #define H_GET_TRACE_BUFFER 0x190 434 #define H_DEFINE_AQP0 0x194 435 #define H_RESIZE_MR 0x198 436 #define H_ATTACH_MCQP 0x19C 437 #define H_DETACH_MCQP 0x1A0 438 #define H_CREATE_RPT 0x1A4 439 #define H_REMOVE_RPT 0x1A8 440 #define H_REGISTER_RPAGES 0x1AC 441 #define H_DISABLE_AND_GETC 0x1B0 442 #define H_ERROR_DATA 0x1B4 443 #define H_GET_HCA_INFO 0x1B8 444 #define H_GET_PERF_COUNT 0x1BC 445 #define H_MANAGE_TRACE 0x1C0 446 #define H_GET_CPU_CHARACTERISTICS 0x1C8 447 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 448 #define H_QUERY_INT_STATE 0x1E4 449 #define H_POLL_PENDING 0x1D8 450 #define H_ILLAN_ATTRIBUTES 0x244 451 #define H_MODIFY_HEA_QP 0x250 452 #define H_QUERY_HEA_QP 0x254 453 #define H_QUERY_HEA 0x258 454 #define H_QUERY_HEA_PORT 0x25C 455 #define H_MODIFY_HEA_PORT 0x260 456 #define H_REG_BCMC 0x264 457 #define H_DEREG_BCMC 0x268 458 #define H_REGISTER_HEA_RPAGES 0x26C 459 #define H_DISABLE_AND_GET_HEA 0x270 460 #define H_GET_HEA_INFO 0x274 461 #define H_ALLOC_HEA_RESOURCE 0x278 462 #define H_ADD_CONN 0x284 463 #define H_DEL_CONN 0x288 464 #define H_JOIN 0x298 465 #define H_VASI_STATE 0x2A4 466 #define H_ENABLE_CRQ 0x2B0 467 #define H_GET_EM_PARMS 0x2B8 468 #define H_SET_MPP 0x2D0 469 #define H_GET_MPP 0x2D4 470 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 471 #define H_XIRR_X 0x2FC 472 #define H_RANDOM 0x300 473 #define H_SET_MODE 0x31C 474 #define H_RESIZE_HPT_PREPARE 0x36C 475 #define H_RESIZE_HPT_COMMIT 0x370 476 #define H_CLEAN_SLB 0x374 477 #define H_INVALIDATE_PID 0x378 478 #define H_REGISTER_PROC_TBL 0x37C 479 #define H_SIGNAL_SYS_RESET 0x380 480 481 #define H_INT_GET_SOURCE_INFO 0x3A8 482 #define H_INT_SET_SOURCE_CONFIG 0x3AC 483 #define H_INT_GET_SOURCE_CONFIG 0x3B0 484 #define H_INT_GET_QUEUE_INFO 0x3B4 485 #define H_INT_SET_QUEUE_CONFIG 0x3B8 486 #define H_INT_GET_QUEUE_CONFIG 0x3BC 487 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 488 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 489 #define H_INT_ESB 0x3C8 490 #define H_INT_SYNC 0x3CC 491 #define H_INT_RESET 0x3D0 492 493 #define MAX_HCALL_OPCODE H_INT_RESET 494 495 /* The hcalls above are standardized in PAPR and implemented by pHyp 496 * as well. 497 * 498 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 499 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 500 * for "platform-specific" hcalls. 501 */ 502 #define KVMPPC_HCALL_BASE 0xf000 503 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 504 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 505 /* Client Architecture support */ 506 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 507 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 508 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 509 510 typedef struct SpaprDeviceTreeUpdateHeader { 511 uint32_t version_id; 512 } SpaprDeviceTreeUpdateHeader; 513 514 #define hcall_dprintf(fmt, ...) \ 515 do { \ 516 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 517 } while (0) 518 519 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 520 target_ulong opcode, 521 target_ulong *args); 522 523 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 524 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 525 target_ulong *args); 526 527 /* ibm,set-eeh-option */ 528 #define RTAS_EEH_DISABLE 0 529 #define RTAS_EEH_ENABLE 1 530 #define RTAS_EEH_THAW_IO 2 531 #define RTAS_EEH_THAW_DMA 3 532 533 /* ibm,get-config-addr-info2 */ 534 #define RTAS_GET_PE_ADDR 0 535 #define RTAS_GET_PE_MODE 1 536 #define RTAS_PE_MODE_NONE 0 537 #define RTAS_PE_MODE_NOT_SHARED 1 538 #define RTAS_PE_MODE_SHARED 2 539 540 /* ibm,read-slot-reset-state2 */ 541 #define RTAS_EEH_PE_STATE_NORMAL 0 542 #define RTAS_EEH_PE_STATE_RESET 1 543 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 544 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 545 #define RTAS_EEH_PE_STATE_UNAVAIL 5 546 #define RTAS_EEH_NOT_SUPPORT 0 547 #define RTAS_EEH_SUPPORT 1 548 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 549 #define RTAS_EEH_PE_RECOVER_INFO 0 550 551 /* ibm,set-slot-reset */ 552 #define RTAS_SLOT_RESET_DEACTIVATE 0 553 #define RTAS_SLOT_RESET_HOT 1 554 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 555 556 /* ibm,slot-error-detail */ 557 #define RTAS_SLOT_TEMP_ERR_LOG 1 558 #define RTAS_SLOT_PERM_ERR_LOG 2 559 560 /* RTAS return codes */ 561 #define RTAS_OUT_SUCCESS 0 562 #define RTAS_OUT_NO_ERRORS_FOUND 1 563 #define RTAS_OUT_HW_ERROR -1 564 #define RTAS_OUT_BUSY -2 565 #define RTAS_OUT_PARAM_ERROR -3 566 #define RTAS_OUT_NOT_SUPPORTED -3 567 #define RTAS_OUT_NO_SUCH_INDICATOR -3 568 #define RTAS_OUT_NOT_AUTHORIZED -9002 569 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 570 571 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 572 #define RTAS_DDW_PGSIZE_4K 0x01 573 #define RTAS_DDW_PGSIZE_64K 0x02 574 #define RTAS_DDW_PGSIZE_16M 0x04 575 #define RTAS_DDW_PGSIZE_32M 0x08 576 #define RTAS_DDW_PGSIZE_64M 0x10 577 #define RTAS_DDW_PGSIZE_128M 0x20 578 #define RTAS_DDW_PGSIZE_256M 0x40 579 #define RTAS_DDW_PGSIZE_16G 0x80 580 581 /* RTAS tokens */ 582 #define RTAS_TOKEN_BASE 0x2000 583 584 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 585 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 586 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 587 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 588 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 589 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 590 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 591 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 592 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 593 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 594 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 595 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 596 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 597 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 598 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 599 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 600 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 601 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 602 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 603 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 604 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 605 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 606 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 607 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 608 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 609 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 610 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 611 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 612 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 613 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 614 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 615 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 616 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 617 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 618 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 619 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 620 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 621 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 622 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 623 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 624 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 625 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 626 627 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 628 629 /* RTAS ibm,get-system-parameter token values */ 630 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 631 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 632 #define RTAS_SYSPARM_UUID 48 633 634 /* RTAS indicator/sensor types 635 * 636 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 637 * 638 * NOTE: currently only DR-related sensors are implemented here 639 */ 640 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 641 #define RTAS_SENSOR_TYPE_DR 9002 642 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 643 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 644 645 /* Possible values for the platform-processor-diagnostics-run-mode parameter 646 * of the RTAS ibm,get-system-parameter call. 647 */ 648 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 649 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 650 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 651 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 652 653 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 654 { 655 return addr & ~0xF000000000000000ULL; 656 } 657 658 static inline uint32_t rtas_ld(target_ulong phys, int n) 659 { 660 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 661 } 662 663 static inline uint64_t rtas_ldq(target_ulong phys, int n) 664 { 665 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 666 } 667 668 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 669 { 670 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 671 } 672 673 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 674 uint32_t token, 675 uint32_t nargs, target_ulong args, 676 uint32_t nret, target_ulong rets); 677 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 678 static inline void spapr_rtas_unregister(int token) 679 { 680 spapr_rtas_register(token, NULL, NULL); 681 } 682 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 683 uint32_t token, uint32_t nargs, target_ulong args, 684 uint32_t nret, target_ulong rets); 685 void spapr_dt_rtas_tokens(void *fdt, int rtas); 686 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 687 688 #define SPAPR_TCE_PAGE_SHIFT 12 689 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 690 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 691 692 #define SPAPR_VIO_BASE_LIOBN 0x00000000 693 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 694 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 695 (0x80000000 | ((phb_index) << 8) | (window_num)) 696 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 697 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 698 699 #define RTAS_ERROR_LOG_MAX 2048 700 701 #define RTAS_EVENT_SCAN_RATE 1 702 703 /* This helper should be used to encode interrupt specifiers when the related 704 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 705 * VIO devices, RTAS event sources and PHBs). 706 */ 707 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 708 { 709 intspec[0] = cpu_to_be32(irq); 710 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 711 } 712 713 typedef struct SpaprTceTable SpaprTceTable; 714 715 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 716 #define SPAPR_TCE_TABLE(obj) \ 717 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 718 719 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 720 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 721 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 722 723 struct SpaprTceTable { 724 DeviceState parent; 725 uint32_t liobn; 726 uint32_t nb_table; 727 uint64_t bus_offset; 728 uint32_t page_shift; 729 uint64_t *table; 730 uint32_t mig_nb_table; 731 uint64_t *mig_table; 732 bool bypass; 733 bool need_vfio; 734 bool skipping_replay; 735 int fd; 736 MemoryRegion root; 737 IOMMUMemoryRegion iommu; 738 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 739 QLIST_ENTRY(SpaprTceTable) list; 740 }; 741 742 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 743 744 struct SpaprEventLogEntry { 745 uint32_t summary; 746 uint32_t extended_length; 747 void *extended_log; 748 QTAILQ_ENTRY(SpaprEventLogEntry) next; 749 }; 750 751 void spapr_events_init(SpaprMachineState *sm); 752 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 753 int spapr_h_cas_compose_response(SpaprMachineState *sm, 754 target_ulong addr, target_ulong size, 755 SpaprOptionVector *ov5_updates); 756 void close_htab_fd(SpaprMachineState *spapr); 757 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr); 758 void spapr_free_hpt(SpaprMachineState *spapr); 759 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 760 void spapr_tce_table_enable(SpaprTceTable *tcet, 761 uint32_t page_shift, uint64_t bus_offset, 762 uint32_t nb_table); 763 void spapr_tce_table_disable(SpaprTceTable *tcet); 764 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 765 766 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 767 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 768 uint32_t liobn, uint64_t window, uint32_t size); 769 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 770 SpaprTceTable *tcet); 771 void spapr_pci_switch_vga(bool big_endian); 772 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 773 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 774 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 775 uint32_t count); 776 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 777 uint32_t count); 778 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 779 uint32_t count, uint32_t index); 780 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 781 uint32_t count, uint32_t index); 782 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 783 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 784 Error **errp); 785 void spapr_clear_pending_events(SpaprMachineState *spapr); 786 int spapr_max_server_number(SpaprMachineState *spapr); 787 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 788 uint64_t pte0, uint64_t pte1); 789 790 /* DRC callbacks. */ 791 void spapr_core_release(DeviceState *dev); 792 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 793 void *fdt, int *fdt_start_offset, Error **errp); 794 void spapr_lmb_release(DeviceState *dev); 795 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 796 void *fdt, int *fdt_start_offset, Error **errp); 797 void spapr_phb_release(DeviceState *dev); 798 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 799 void *fdt, int *fdt_start_offset, Error **errp); 800 801 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 802 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 803 804 #define TYPE_SPAPR_RNG "spapr-rng" 805 806 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 807 808 /* 809 * This defines the maximum number of DIMM slots we can have for sPAPR 810 * guest. This is not defined by sPAPR but we are defining it to 32 slots 811 * based on default number of slots provided by PowerPC kernel. 812 */ 813 #define SPAPR_MAX_RAM_SLOTS 32 814 815 /* 1GB alignment for hotplug memory region */ 816 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 817 818 /* 819 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 820 * property under ibm,dynamic-reconfiguration-memory node. 821 */ 822 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 823 824 /* 825 * Defines for flag value in ibm,dynamic-memory property under 826 * ibm,dynamic-reconfiguration-memory node. 827 */ 828 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 829 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 830 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 831 832 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 833 834 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 835 836 int spapr_get_vcpu_id(PowerPCCPU *cpu); 837 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 838 PowerPCCPU *spapr_find_cpu(int vcpu_id); 839 840 int spapr_caps_pre_load(void *opaque); 841 int spapr_caps_pre_save(void *opaque); 842 843 /* 844 * Handling of optional capabilities 845 */ 846 extern const VMStateDescription vmstate_spapr_cap_htm; 847 extern const VMStateDescription vmstate_spapr_cap_vsx; 848 extern const VMStateDescription vmstate_spapr_cap_dfp; 849 extern const VMStateDescription vmstate_spapr_cap_cfpc; 850 extern const VMStateDescription vmstate_spapr_cap_sbbc; 851 extern const VMStateDescription vmstate_spapr_cap_ibs; 852 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 853 extern const VMStateDescription vmstate_spapr_cap_large_decr; 854 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 855 856 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 857 { 858 return spapr->eff.caps[cap]; 859 } 860 861 void spapr_caps_init(SpaprMachineState *spapr); 862 void spapr_caps_apply(SpaprMachineState *spapr); 863 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 864 void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp); 865 int spapr_caps_post_migration(SpaprMachineState *spapr); 866 867 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 868 Error **errp); 869 /* 870 * XIVE definitions 871 */ 872 #define SPAPR_OV5_XIVE_LEGACY 0x0 873 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 874 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 875 876 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 877 #endif /* HW_SPAPR_H */ 878