1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 11 struct VIOsPAPRBus; 12 struct sPAPRPHBState; 13 struct sPAPRNVRAM; 14 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState; 15 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 16 17 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 18 #define SPAPR_ENTRY_POINT 0x100 19 20 #define SPAPR_TIMEBASE_FREQ 512000000ULL 21 22 typedef struct sPAPRMachineClass sPAPRMachineClass; 23 typedef struct sPAPRMachineState sPAPRMachineState; 24 25 #define TYPE_SPAPR_MACHINE "spapr-machine" 26 #define SPAPR_MACHINE(obj) \ 27 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 28 #define SPAPR_MACHINE_GET_CLASS(obj) \ 29 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 30 #define SPAPR_MACHINE_CLASS(klass) \ 31 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 32 33 /** 34 * sPAPRMachineClass: 35 */ 36 struct sPAPRMachineClass { 37 /*< private >*/ 38 MachineClass parent_class; 39 40 /*< public >*/ 41 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 42 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 43 const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */ 44 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 45 uint64_t *buid, hwaddr *pio, 46 hwaddr *mmio32, hwaddr *mmio64, 47 unsigned n_dma, uint32_t *liobns, Error **errp); 48 }; 49 50 /** 51 * sPAPRMachineState: 52 */ 53 struct sPAPRMachineState { 54 /*< private >*/ 55 MachineState parent_obj; 56 57 struct VIOsPAPRBus *vio_bus; 58 QLIST_HEAD(, sPAPRPHBState) phbs; 59 struct sPAPRNVRAM *nvram; 60 XICSState *xics; 61 DeviceState *rtc; 62 63 void *htab; 64 uint32_t htab_shift; 65 hwaddr rma_size; 66 int vrma_adjust; 67 ssize_t rtas_size; 68 void *rtas_blob; 69 long kernel_size; 70 bool kernel_le; 71 uint32_t initrd_base; 72 long initrd_size; 73 uint64_t rtc_offset; /* Now used only during incoming migration */ 74 struct PPCTimebase tb; 75 bool has_graphics; 76 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 77 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 78 bool cas_reboot; 79 80 uint32_t check_exception_irq; 81 Notifier epow_notifier; 82 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 83 84 /* Migration state */ 85 int htab_save_index; 86 bool htab_first_pass; 87 int htab_fd; 88 89 /* RTAS state */ 90 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list; 91 92 /*< public >*/ 93 char *kvm_type; 94 MemoryHotplugState hotplug_memory; 95 Object **cores; 96 }; 97 98 #define H_SUCCESS 0 99 #define H_BUSY 1 /* Hardware busy -- retry later */ 100 #define H_CLOSED 2 /* Resource closed */ 101 #define H_NOT_AVAILABLE 3 102 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 103 #define H_PARTIAL 5 104 #define H_IN_PROGRESS 14 /* Kind of like busy */ 105 #define H_PAGE_REGISTERED 15 106 #define H_PARTIAL_STORE 16 107 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 108 #define H_CONTINUE 18 /* Returned from H_Join on success */ 109 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 110 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 111 is a good time to retry */ 112 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 113 is a good time to retry */ 114 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 115 is a good time to retry */ 116 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 117 is a good time to retry */ 118 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 119 is a good time to retry */ 120 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 121 is a good time to retry */ 122 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 123 #define H_HARDWARE -1 /* Hardware error */ 124 #define H_FUNCTION -2 /* Function not supported */ 125 #define H_PRIVILEGE -3 /* Caller not privileged */ 126 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 127 #define H_BAD_MODE -5 /* Illegal msr value */ 128 #define H_PTEG_FULL -6 /* PTEG is full */ 129 #define H_NOT_FOUND -7 /* PTE was not found" */ 130 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 131 #define H_NO_MEM -9 132 #define H_AUTHORITY -10 133 #define H_PERMISSION -11 134 #define H_DROPPED -12 135 #define H_SOURCE_PARM -13 136 #define H_DEST_PARM -14 137 #define H_REMOTE_PARM -15 138 #define H_RESOURCE -16 139 #define H_ADAPTER_PARM -17 140 #define H_RH_PARM -18 141 #define H_RCQ_PARM -19 142 #define H_SCQ_PARM -20 143 #define H_EQ_PARM -21 144 #define H_RT_PARM -22 145 #define H_ST_PARM -23 146 #define H_SIGT_PARM -24 147 #define H_TOKEN_PARM -25 148 #define H_MLENGTH_PARM -27 149 #define H_MEM_PARM -28 150 #define H_MEM_ACCESS_PARM -29 151 #define H_ATTR_PARM -30 152 #define H_PORT_PARM -31 153 #define H_MCG_PARM -32 154 #define H_VL_PARM -33 155 #define H_TSIZE_PARM -34 156 #define H_TRACE_PARM -35 157 158 #define H_MASK_PARM -37 159 #define H_MCG_FULL -38 160 #define H_ALIAS_EXIST -39 161 #define H_P_COUNTER -40 162 #define H_TABLE_FULL -41 163 #define H_ALT_TABLE -42 164 #define H_MR_CONDITION -43 165 #define H_NOT_ENOUGH_RESOURCES -44 166 #define H_R_STATE -45 167 #define H_RESCINDEND -46 168 #define H_P2 -55 169 #define H_P3 -56 170 #define H_P4 -57 171 #define H_P5 -58 172 #define H_P6 -59 173 #define H_P7 -60 174 #define H_P8 -61 175 #define H_P9 -62 176 #define H_UNSUPPORTED_FLAG -256 177 #define H_MULTI_THREADS_ACTIVE -9005 178 179 180 /* Long Busy is a condition that can be returned by the firmware 181 * when a call cannot be completed now, but the identical call 182 * should be retried later. This prevents calls blocking in the 183 * firmware for long periods of time. Annoyingly the firmware can return 184 * a range of return codes, hinting at how long we should wait before 185 * retrying. If you don't care for the hint, the macro below is a good 186 * way to check for the long_busy return codes 187 */ 188 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 189 && (x <= H_LONG_BUSY_END_RANGE)) 190 191 /* Flags */ 192 #define H_LARGE_PAGE (1ULL<<(63-16)) 193 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 194 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 195 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 196 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 197 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 198 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 199 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 200 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 201 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 202 #define H_ANDCOND (1ULL<<(63-33)) 203 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 204 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 205 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 206 #define H_COPY_PAGE (1ULL<<(63-49)) 207 #define H_N (1ULL<<(63-61)) 208 #define H_PP1 (1ULL<<(63-62)) 209 #define H_PP2 (1ULL<<(63-63)) 210 211 /* Values for 2nd argument to H_SET_MODE */ 212 #define H_SET_MODE_RESOURCE_SET_CIABR 1 213 #define H_SET_MODE_RESOURCE_SET_DAWR 2 214 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 215 #define H_SET_MODE_RESOURCE_LE 4 216 217 /* Flags for H_SET_MODE_RESOURCE_LE */ 218 #define H_SET_MODE_ENDIAN_BIG 0 219 #define H_SET_MODE_ENDIAN_LITTLE 1 220 221 /* VASI States */ 222 #define H_VASI_INVALID 0 223 #define H_VASI_ENABLED 1 224 #define H_VASI_ABORTED 2 225 #define H_VASI_SUSPENDING 3 226 #define H_VASI_SUSPENDED 4 227 #define H_VASI_RESUMED 5 228 #define H_VASI_COMPLETED 6 229 230 /* DABRX flags */ 231 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 232 #define H_DABRX_KERNEL (1ULL<<(63-62)) 233 #define H_DABRX_USER (1ULL<<(63-63)) 234 235 /* Each control block has to be on a 4K boundary */ 236 #define H_CB_ALIGNMENT 4096 237 238 /* pSeries hypervisor opcodes */ 239 #define H_REMOVE 0x04 240 #define H_ENTER 0x08 241 #define H_READ 0x0c 242 #define H_CLEAR_MOD 0x10 243 #define H_CLEAR_REF 0x14 244 #define H_PROTECT 0x18 245 #define H_GET_TCE 0x1c 246 #define H_PUT_TCE 0x20 247 #define H_SET_SPRG0 0x24 248 #define H_SET_DABR 0x28 249 #define H_PAGE_INIT 0x2c 250 #define H_SET_ASR 0x30 251 #define H_ASR_ON 0x34 252 #define H_ASR_OFF 0x38 253 #define H_LOGICAL_CI_LOAD 0x3c 254 #define H_LOGICAL_CI_STORE 0x40 255 #define H_LOGICAL_CACHE_LOAD 0x44 256 #define H_LOGICAL_CACHE_STORE 0x48 257 #define H_LOGICAL_ICBI 0x4c 258 #define H_LOGICAL_DCBF 0x50 259 #define H_GET_TERM_CHAR 0x54 260 #define H_PUT_TERM_CHAR 0x58 261 #define H_REAL_TO_LOGICAL 0x5c 262 #define H_HYPERVISOR_DATA 0x60 263 #define H_EOI 0x64 264 #define H_CPPR 0x68 265 #define H_IPI 0x6c 266 #define H_IPOLL 0x70 267 #define H_XIRR 0x74 268 #define H_PERFMON 0x7c 269 #define H_MIGRATE_DMA 0x78 270 #define H_REGISTER_VPA 0xDC 271 #define H_CEDE 0xE0 272 #define H_CONFER 0xE4 273 #define H_PROD 0xE8 274 #define H_GET_PPP 0xEC 275 #define H_SET_PPP 0xF0 276 #define H_PURR 0xF4 277 #define H_PIC 0xF8 278 #define H_REG_CRQ 0xFC 279 #define H_FREE_CRQ 0x100 280 #define H_VIO_SIGNAL 0x104 281 #define H_SEND_CRQ 0x108 282 #define H_COPY_RDMA 0x110 283 #define H_REGISTER_LOGICAL_LAN 0x114 284 #define H_FREE_LOGICAL_LAN 0x118 285 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 286 #define H_SEND_LOGICAL_LAN 0x120 287 #define H_BULK_REMOVE 0x124 288 #define H_MULTICAST_CTRL 0x130 289 #define H_SET_XDABR 0x134 290 #define H_STUFF_TCE 0x138 291 #define H_PUT_TCE_INDIRECT 0x13C 292 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 293 #define H_VTERM_PARTNER_INFO 0x150 294 #define H_REGISTER_VTERM 0x154 295 #define H_FREE_VTERM 0x158 296 #define H_RESET_EVENTS 0x15C 297 #define H_ALLOC_RESOURCE 0x160 298 #define H_FREE_RESOURCE 0x164 299 #define H_MODIFY_QP 0x168 300 #define H_QUERY_QP 0x16C 301 #define H_REREGISTER_PMR 0x170 302 #define H_REGISTER_SMR 0x174 303 #define H_QUERY_MR 0x178 304 #define H_QUERY_MW 0x17C 305 #define H_QUERY_HCA 0x180 306 #define H_QUERY_PORT 0x184 307 #define H_MODIFY_PORT 0x188 308 #define H_DEFINE_AQP1 0x18C 309 #define H_GET_TRACE_BUFFER 0x190 310 #define H_DEFINE_AQP0 0x194 311 #define H_RESIZE_MR 0x198 312 #define H_ATTACH_MCQP 0x19C 313 #define H_DETACH_MCQP 0x1A0 314 #define H_CREATE_RPT 0x1A4 315 #define H_REMOVE_RPT 0x1A8 316 #define H_REGISTER_RPAGES 0x1AC 317 #define H_DISABLE_AND_GETC 0x1B0 318 #define H_ERROR_DATA 0x1B4 319 #define H_GET_HCA_INFO 0x1B8 320 #define H_GET_PERF_COUNT 0x1BC 321 #define H_MANAGE_TRACE 0x1C0 322 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 323 #define H_QUERY_INT_STATE 0x1E4 324 #define H_POLL_PENDING 0x1D8 325 #define H_ILLAN_ATTRIBUTES 0x244 326 #define H_MODIFY_HEA_QP 0x250 327 #define H_QUERY_HEA_QP 0x254 328 #define H_QUERY_HEA 0x258 329 #define H_QUERY_HEA_PORT 0x25C 330 #define H_MODIFY_HEA_PORT 0x260 331 #define H_REG_BCMC 0x264 332 #define H_DEREG_BCMC 0x268 333 #define H_REGISTER_HEA_RPAGES 0x26C 334 #define H_DISABLE_AND_GET_HEA 0x270 335 #define H_GET_HEA_INFO 0x274 336 #define H_ALLOC_HEA_RESOURCE 0x278 337 #define H_ADD_CONN 0x284 338 #define H_DEL_CONN 0x288 339 #define H_JOIN 0x298 340 #define H_VASI_STATE 0x2A4 341 #define H_ENABLE_CRQ 0x2B0 342 #define H_GET_EM_PARMS 0x2B8 343 #define H_SET_MPP 0x2D0 344 #define H_GET_MPP 0x2D4 345 #define H_XIRR_X 0x2FC 346 #define H_RANDOM 0x300 347 #define H_SET_MODE 0x31C 348 #define MAX_HCALL_OPCODE H_SET_MODE 349 350 /* The hcalls above are standardized in PAPR and implemented by pHyp 351 * as well. 352 * 353 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 354 * So far we just need one for H_RTAS, but in future we'll need more 355 * for extensions like virtio. We put those into the 0xf000-0xfffc 356 * range which is reserved by PAPR for "platform-specific" hcalls. 357 */ 358 #define KVMPPC_HCALL_BASE 0xf000 359 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 360 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 361 /* Client Architecture support */ 362 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 363 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 364 365 typedef struct sPAPRDeviceTreeUpdateHeader { 366 uint32_t version_id; 367 } sPAPRDeviceTreeUpdateHeader; 368 369 #define hcall_dprintf(fmt, ...) \ 370 do { \ 371 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 372 } while (0) 373 374 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 375 target_ulong opcode, 376 target_ulong *args); 377 378 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 379 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 380 target_ulong *args); 381 382 /* ibm,set-eeh-option */ 383 #define RTAS_EEH_DISABLE 0 384 #define RTAS_EEH_ENABLE 1 385 #define RTAS_EEH_THAW_IO 2 386 #define RTAS_EEH_THAW_DMA 3 387 388 /* ibm,get-config-addr-info2 */ 389 #define RTAS_GET_PE_ADDR 0 390 #define RTAS_GET_PE_MODE 1 391 #define RTAS_PE_MODE_NONE 0 392 #define RTAS_PE_MODE_NOT_SHARED 1 393 #define RTAS_PE_MODE_SHARED 2 394 395 /* ibm,read-slot-reset-state2 */ 396 #define RTAS_EEH_PE_STATE_NORMAL 0 397 #define RTAS_EEH_PE_STATE_RESET 1 398 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 399 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 400 #define RTAS_EEH_PE_STATE_UNAVAIL 5 401 #define RTAS_EEH_NOT_SUPPORT 0 402 #define RTAS_EEH_SUPPORT 1 403 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 404 #define RTAS_EEH_PE_RECOVER_INFO 0 405 406 /* ibm,set-slot-reset */ 407 #define RTAS_SLOT_RESET_DEACTIVATE 0 408 #define RTAS_SLOT_RESET_HOT 1 409 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 410 411 /* ibm,slot-error-detail */ 412 #define RTAS_SLOT_TEMP_ERR_LOG 1 413 #define RTAS_SLOT_PERM_ERR_LOG 2 414 415 /* RTAS return codes */ 416 #define RTAS_OUT_SUCCESS 0 417 #define RTAS_OUT_NO_ERRORS_FOUND 1 418 #define RTAS_OUT_HW_ERROR -1 419 #define RTAS_OUT_BUSY -2 420 #define RTAS_OUT_PARAM_ERROR -3 421 #define RTAS_OUT_NOT_SUPPORTED -3 422 #define RTAS_OUT_NO_SUCH_INDICATOR -3 423 #define RTAS_OUT_NOT_AUTHORIZED -9002 424 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 425 426 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 427 #define RTAS_DDW_PGSIZE_4K 0x01 428 #define RTAS_DDW_PGSIZE_64K 0x02 429 #define RTAS_DDW_PGSIZE_16M 0x04 430 #define RTAS_DDW_PGSIZE_32M 0x08 431 #define RTAS_DDW_PGSIZE_64M 0x10 432 #define RTAS_DDW_PGSIZE_128M 0x20 433 #define RTAS_DDW_PGSIZE_256M 0x40 434 #define RTAS_DDW_PGSIZE_16G 0x80 435 436 /* RTAS tokens */ 437 #define RTAS_TOKEN_BASE 0x2000 438 439 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 440 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 441 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 442 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 443 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 444 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 445 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 446 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 447 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 448 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 449 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 450 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 451 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 452 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 453 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 454 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 455 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 456 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 457 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 458 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 459 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 460 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 461 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 462 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 463 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 464 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 465 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 466 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 467 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 468 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 469 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 470 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 471 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 472 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 473 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 474 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 475 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 476 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 477 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 478 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 479 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 480 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 481 482 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 483 484 /* RTAS ibm,get-system-parameter token values */ 485 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 486 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 487 #define RTAS_SYSPARM_UUID 48 488 489 /* RTAS indicator/sensor types 490 * 491 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 492 * 493 * NOTE: currently only DR-related sensors are implemented here 494 */ 495 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 496 #define RTAS_SENSOR_TYPE_DR 9002 497 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 498 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 499 500 /* Possible values for the platform-processor-diagnostics-run-mode parameter 501 * of the RTAS ibm,get-system-parameter call. 502 */ 503 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 504 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 505 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 506 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 507 508 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 509 { 510 return addr & ~0xF000000000000000ULL; 511 } 512 513 static inline uint32_t rtas_ld(target_ulong phys, int n) 514 { 515 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 516 } 517 518 static inline uint64_t rtas_ldq(target_ulong phys, int n) 519 { 520 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 521 } 522 523 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 524 { 525 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 526 } 527 528 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 529 uint32_t token, 530 uint32_t nargs, target_ulong args, 531 uint32_t nret, target_ulong rets); 532 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 533 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 534 uint32_t token, uint32_t nargs, target_ulong args, 535 uint32_t nret, target_ulong rets); 536 void spapr_dt_rtas_tokens(void *fdt, int rtas); 537 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 538 539 #define SPAPR_TCE_PAGE_SHIFT 12 540 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 541 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 542 543 #define SPAPR_VIO_BASE_LIOBN 0x00000000 544 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 545 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 546 (0x80000000 | ((phb_index) << 8) | (window_num)) 547 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 548 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 549 550 #define RTAS_ERROR_LOG_MAX 2048 551 552 #define RTAS_EVENT_SCAN_RATE 1 553 554 typedef struct sPAPRTCETable sPAPRTCETable; 555 556 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 557 #define SPAPR_TCE_TABLE(obj) \ 558 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 559 560 struct sPAPRTCETable { 561 DeviceState parent; 562 uint32_t liobn; 563 uint32_t nb_table; 564 uint64_t bus_offset; 565 uint32_t page_shift; 566 uint64_t *table; 567 uint32_t mig_nb_table; 568 uint64_t *mig_table; 569 bool bypass; 570 bool need_vfio; 571 int fd; 572 MemoryRegion root, iommu; 573 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 574 QLIST_ENTRY(sPAPRTCETable) list; 575 }; 576 577 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 578 579 struct sPAPREventLogEntry { 580 int log_type; 581 bool exception; 582 void *data; 583 QTAILQ_ENTRY(sPAPREventLogEntry) next; 584 }; 585 586 void spapr_events_init(sPAPRMachineState *sm); 587 void spapr_dt_events(void *fdt, uint32_t check_exception_irq); 588 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 589 target_ulong addr, target_ulong size, 590 bool cpu_update, 591 sPAPROptionVector *ov5_updates); 592 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 593 void spapr_tce_table_enable(sPAPRTCETable *tcet, 594 uint32_t page_shift, uint64_t bus_offset, 595 uint32_t nb_table); 596 void spapr_tce_table_disable(sPAPRTCETable *tcet); 597 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 598 599 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 600 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 601 uint32_t liobn, uint64_t window, uint32_t size); 602 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 603 sPAPRTCETable *tcet); 604 void spapr_pci_switch_vga(bool big_endian); 605 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 606 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 607 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 608 uint32_t count); 609 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 610 uint32_t count); 611 void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp); 612 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 613 sPAPRMachineState *spapr); 614 615 /* rtas-configure-connector state */ 616 struct sPAPRConfigureConnectorState { 617 uint32_t drc_index; 618 int fdt_offset; 619 int fdt_depth; 620 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next; 621 }; 622 623 void spapr_ccs_reset_hook(void *opaque); 624 625 #define TYPE_SPAPR_RTC "spapr-rtc" 626 #define TYPE_SPAPR_RNG "spapr-rng" 627 628 void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); 629 int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); 630 631 int spapr_rng_populate_dt(void *fdt); 632 633 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 634 635 /* 636 * This defines the maximum number of DIMM slots we can have for sPAPR 637 * guest. This is not defined by sPAPR but we are defining it to 32 slots 638 * based on default number of slots provided by PowerPC kernel. 639 */ 640 #define SPAPR_MAX_RAM_SLOTS 32 641 642 /* 1GB alignment for hotplug memory region */ 643 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 644 645 /* 646 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 647 * property under ibm,dynamic-reconfiguration-memory node. 648 */ 649 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 650 651 /* 652 * Defines for flag value in ibm,dynamic-memory property under 653 * ibm,dynamic-reconfiguration-memory node. 654 */ 655 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 656 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 657 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 658 659 #endif /* HW_SPAPR_H */ 660