1 #if !defined(__HW_SPAPR_H__) 2 #define __HW_SPAPR_H__ 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 10 struct VIOsPAPRBus; 11 struct sPAPRPHBState; 12 struct sPAPRNVRAM; 13 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 16 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 17 #define SPAPR_ENTRY_POINT 0x100 18 19 typedef struct sPAPRMachineClass sPAPRMachineClass; 20 typedef struct sPAPRMachineState sPAPRMachineState; 21 22 #define TYPE_SPAPR_MACHINE "spapr-machine" 23 #define SPAPR_MACHINE(obj) \ 24 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 25 #define SPAPR_MACHINE_GET_CLASS(obj) \ 26 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 27 #define SPAPR_MACHINE_CLASS(klass) \ 28 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 29 30 /** 31 * sPAPRMachineClass: 32 */ 33 struct sPAPRMachineClass { 34 /*< private >*/ 35 MachineClass parent_class; 36 37 /*< public >*/ 38 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 39 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 40 }; 41 42 /** 43 * sPAPRMachineState: 44 */ 45 struct sPAPRMachineState { 46 /*< private >*/ 47 MachineState parent_obj; 48 49 struct VIOsPAPRBus *vio_bus; 50 QLIST_HEAD(, sPAPRPHBState) phbs; 51 struct sPAPRNVRAM *nvram; 52 XICSState *icp; 53 DeviceState *rtc; 54 55 void *htab; 56 uint32_t htab_shift; 57 hwaddr rma_size; 58 int vrma_adjust; 59 hwaddr fdt_addr, rtas_addr; 60 ssize_t rtas_size; 61 void *rtas_blob; 62 void *fdt_skel; 63 uint64_t rtc_offset; /* Now used only during incoming migration */ 64 struct PPCTimebase tb; 65 bool has_graphics; 66 67 uint32_t check_exception_irq; 68 Notifier epow_notifier; 69 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 70 71 /* Migration state */ 72 int htab_save_index; 73 bool htab_first_pass; 74 int htab_fd; 75 bool htab_fd_stale; 76 77 /* RTAS state */ 78 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list; 79 80 /*< public >*/ 81 char *kvm_type; 82 MemoryHotplugState hotplug_memory; 83 }; 84 85 #define H_SUCCESS 0 86 #define H_BUSY 1 /* Hardware busy -- retry later */ 87 #define H_CLOSED 2 /* Resource closed */ 88 #define H_NOT_AVAILABLE 3 89 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 90 #define H_PARTIAL 5 91 #define H_IN_PROGRESS 14 /* Kind of like busy */ 92 #define H_PAGE_REGISTERED 15 93 #define H_PARTIAL_STORE 16 94 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 95 #define H_CONTINUE 18 /* Returned from H_Join on success */ 96 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 97 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 98 is a good time to retry */ 99 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 100 is a good time to retry */ 101 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 102 is a good time to retry */ 103 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 104 is a good time to retry */ 105 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 106 is a good time to retry */ 107 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 108 is a good time to retry */ 109 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 110 #define H_HARDWARE -1 /* Hardware error */ 111 #define H_FUNCTION -2 /* Function not supported */ 112 #define H_PRIVILEGE -3 /* Caller not privileged */ 113 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 114 #define H_BAD_MODE -5 /* Illegal msr value */ 115 #define H_PTEG_FULL -6 /* PTEG is full */ 116 #define H_NOT_FOUND -7 /* PTE was not found" */ 117 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 118 #define H_NO_MEM -9 119 #define H_AUTHORITY -10 120 #define H_PERMISSION -11 121 #define H_DROPPED -12 122 #define H_SOURCE_PARM -13 123 #define H_DEST_PARM -14 124 #define H_REMOTE_PARM -15 125 #define H_RESOURCE -16 126 #define H_ADAPTER_PARM -17 127 #define H_RH_PARM -18 128 #define H_RCQ_PARM -19 129 #define H_SCQ_PARM -20 130 #define H_EQ_PARM -21 131 #define H_RT_PARM -22 132 #define H_ST_PARM -23 133 #define H_SIGT_PARM -24 134 #define H_TOKEN_PARM -25 135 #define H_MLENGTH_PARM -27 136 #define H_MEM_PARM -28 137 #define H_MEM_ACCESS_PARM -29 138 #define H_ATTR_PARM -30 139 #define H_PORT_PARM -31 140 #define H_MCG_PARM -32 141 #define H_VL_PARM -33 142 #define H_TSIZE_PARM -34 143 #define H_TRACE_PARM -35 144 145 #define H_MASK_PARM -37 146 #define H_MCG_FULL -38 147 #define H_ALIAS_EXIST -39 148 #define H_P_COUNTER -40 149 #define H_TABLE_FULL -41 150 #define H_ALT_TABLE -42 151 #define H_MR_CONDITION -43 152 #define H_NOT_ENOUGH_RESOURCES -44 153 #define H_R_STATE -45 154 #define H_RESCINDEND -46 155 #define H_P2 -55 156 #define H_P3 -56 157 #define H_P4 -57 158 #define H_P5 -58 159 #define H_P6 -59 160 #define H_P7 -60 161 #define H_P8 -61 162 #define H_P9 -62 163 #define H_UNSUPPORTED_FLAG -256 164 #define H_MULTI_THREADS_ACTIVE -9005 165 166 167 /* Long Busy is a condition that can be returned by the firmware 168 * when a call cannot be completed now, but the identical call 169 * should be retried later. This prevents calls blocking in the 170 * firmware for long periods of time. Annoyingly the firmware can return 171 * a range of return codes, hinting at how long we should wait before 172 * retrying. If you don't care for the hint, the macro below is a good 173 * way to check for the long_busy return codes 174 */ 175 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 176 && (x <= H_LONG_BUSY_END_RANGE)) 177 178 /* Flags */ 179 #define H_LARGE_PAGE (1ULL<<(63-16)) 180 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 181 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 182 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 183 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 184 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 185 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 186 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 187 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 188 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 189 #define H_ANDCOND (1ULL<<(63-33)) 190 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 191 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 192 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 193 #define H_COPY_PAGE (1ULL<<(63-49)) 194 #define H_N (1ULL<<(63-61)) 195 #define H_PP1 (1ULL<<(63-62)) 196 #define H_PP2 (1ULL<<(63-63)) 197 198 /* Values for 2nd argument to H_SET_MODE */ 199 #define H_SET_MODE_RESOURCE_SET_CIABR 1 200 #define H_SET_MODE_RESOURCE_SET_DAWR 2 201 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 202 #define H_SET_MODE_RESOURCE_LE 4 203 204 /* Flags for H_SET_MODE_RESOURCE_LE */ 205 #define H_SET_MODE_ENDIAN_BIG 0 206 #define H_SET_MODE_ENDIAN_LITTLE 1 207 208 /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ 209 #define H_SET_MODE_ADDR_TRANS_NONE 0 210 #define H_SET_MODE_ADDR_TRANS_0001_8000 2 211 #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 212 213 /* VASI States */ 214 #define H_VASI_INVALID 0 215 #define H_VASI_ENABLED 1 216 #define H_VASI_ABORTED 2 217 #define H_VASI_SUSPENDING 3 218 #define H_VASI_SUSPENDED 4 219 #define H_VASI_RESUMED 5 220 #define H_VASI_COMPLETED 6 221 222 /* DABRX flags */ 223 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 224 #define H_DABRX_KERNEL (1ULL<<(63-62)) 225 #define H_DABRX_USER (1ULL<<(63-63)) 226 227 /* Each control block has to be on a 4K boundary */ 228 #define H_CB_ALIGNMENT 4096 229 230 /* pSeries hypervisor opcodes */ 231 #define H_REMOVE 0x04 232 #define H_ENTER 0x08 233 #define H_READ 0x0c 234 #define H_CLEAR_MOD 0x10 235 #define H_CLEAR_REF 0x14 236 #define H_PROTECT 0x18 237 #define H_GET_TCE 0x1c 238 #define H_PUT_TCE 0x20 239 #define H_SET_SPRG0 0x24 240 #define H_SET_DABR 0x28 241 #define H_PAGE_INIT 0x2c 242 #define H_SET_ASR 0x30 243 #define H_ASR_ON 0x34 244 #define H_ASR_OFF 0x38 245 #define H_LOGICAL_CI_LOAD 0x3c 246 #define H_LOGICAL_CI_STORE 0x40 247 #define H_LOGICAL_CACHE_LOAD 0x44 248 #define H_LOGICAL_CACHE_STORE 0x48 249 #define H_LOGICAL_ICBI 0x4c 250 #define H_LOGICAL_DCBF 0x50 251 #define H_GET_TERM_CHAR 0x54 252 #define H_PUT_TERM_CHAR 0x58 253 #define H_REAL_TO_LOGICAL 0x5c 254 #define H_HYPERVISOR_DATA 0x60 255 #define H_EOI 0x64 256 #define H_CPPR 0x68 257 #define H_IPI 0x6c 258 #define H_IPOLL 0x70 259 #define H_XIRR 0x74 260 #define H_PERFMON 0x7c 261 #define H_MIGRATE_DMA 0x78 262 #define H_REGISTER_VPA 0xDC 263 #define H_CEDE 0xE0 264 #define H_CONFER 0xE4 265 #define H_PROD 0xE8 266 #define H_GET_PPP 0xEC 267 #define H_SET_PPP 0xF0 268 #define H_PURR 0xF4 269 #define H_PIC 0xF8 270 #define H_REG_CRQ 0xFC 271 #define H_FREE_CRQ 0x100 272 #define H_VIO_SIGNAL 0x104 273 #define H_SEND_CRQ 0x108 274 #define H_COPY_RDMA 0x110 275 #define H_REGISTER_LOGICAL_LAN 0x114 276 #define H_FREE_LOGICAL_LAN 0x118 277 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 278 #define H_SEND_LOGICAL_LAN 0x120 279 #define H_BULK_REMOVE 0x124 280 #define H_MULTICAST_CTRL 0x130 281 #define H_SET_XDABR 0x134 282 #define H_STUFF_TCE 0x138 283 #define H_PUT_TCE_INDIRECT 0x13C 284 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 285 #define H_VTERM_PARTNER_INFO 0x150 286 #define H_REGISTER_VTERM 0x154 287 #define H_FREE_VTERM 0x158 288 #define H_RESET_EVENTS 0x15C 289 #define H_ALLOC_RESOURCE 0x160 290 #define H_FREE_RESOURCE 0x164 291 #define H_MODIFY_QP 0x168 292 #define H_QUERY_QP 0x16C 293 #define H_REREGISTER_PMR 0x170 294 #define H_REGISTER_SMR 0x174 295 #define H_QUERY_MR 0x178 296 #define H_QUERY_MW 0x17C 297 #define H_QUERY_HCA 0x180 298 #define H_QUERY_PORT 0x184 299 #define H_MODIFY_PORT 0x188 300 #define H_DEFINE_AQP1 0x18C 301 #define H_GET_TRACE_BUFFER 0x190 302 #define H_DEFINE_AQP0 0x194 303 #define H_RESIZE_MR 0x198 304 #define H_ATTACH_MCQP 0x19C 305 #define H_DETACH_MCQP 0x1A0 306 #define H_CREATE_RPT 0x1A4 307 #define H_REMOVE_RPT 0x1A8 308 #define H_REGISTER_RPAGES 0x1AC 309 #define H_DISABLE_AND_GETC 0x1B0 310 #define H_ERROR_DATA 0x1B4 311 #define H_GET_HCA_INFO 0x1B8 312 #define H_GET_PERF_COUNT 0x1BC 313 #define H_MANAGE_TRACE 0x1C0 314 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 315 #define H_QUERY_INT_STATE 0x1E4 316 #define H_POLL_PENDING 0x1D8 317 #define H_ILLAN_ATTRIBUTES 0x244 318 #define H_MODIFY_HEA_QP 0x250 319 #define H_QUERY_HEA_QP 0x254 320 #define H_QUERY_HEA 0x258 321 #define H_QUERY_HEA_PORT 0x25C 322 #define H_MODIFY_HEA_PORT 0x260 323 #define H_REG_BCMC 0x264 324 #define H_DEREG_BCMC 0x268 325 #define H_REGISTER_HEA_RPAGES 0x26C 326 #define H_DISABLE_AND_GET_HEA 0x270 327 #define H_GET_HEA_INFO 0x274 328 #define H_ALLOC_HEA_RESOURCE 0x278 329 #define H_ADD_CONN 0x284 330 #define H_DEL_CONN 0x288 331 #define H_JOIN 0x298 332 #define H_VASI_STATE 0x2A4 333 #define H_ENABLE_CRQ 0x2B0 334 #define H_GET_EM_PARMS 0x2B8 335 #define H_SET_MPP 0x2D0 336 #define H_GET_MPP 0x2D4 337 #define H_XIRR_X 0x2FC 338 #define H_RANDOM 0x300 339 #define H_SET_MODE 0x31C 340 #define MAX_HCALL_OPCODE H_SET_MODE 341 342 /* The hcalls above are standardized in PAPR and implemented by pHyp 343 * as well. 344 * 345 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 346 * So far we just need one for H_RTAS, but in future we'll need more 347 * for extensions like virtio. We put those into the 0xf000-0xfffc 348 * range which is reserved by PAPR for "platform-specific" hcalls. 349 */ 350 #define KVMPPC_HCALL_BASE 0xf000 351 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 352 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 353 /* Client Architecture support */ 354 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 355 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 356 357 typedef struct sPAPRDeviceTreeUpdateHeader { 358 uint32_t version_id; 359 } sPAPRDeviceTreeUpdateHeader; 360 361 #define hcall_dprintf(fmt, ...) \ 362 do { \ 363 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 364 } while (0) 365 366 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 367 target_ulong opcode, 368 target_ulong *args); 369 370 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 371 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 372 target_ulong *args); 373 374 int spapr_allocate_irq(int hint, bool lsi); 375 int spapr_allocate_irq_block(int num, bool lsi, bool msi); 376 377 /* ibm,set-eeh-option */ 378 #define RTAS_EEH_DISABLE 0 379 #define RTAS_EEH_ENABLE 1 380 #define RTAS_EEH_THAW_IO 2 381 #define RTAS_EEH_THAW_DMA 3 382 383 /* ibm,get-config-addr-info2 */ 384 #define RTAS_GET_PE_ADDR 0 385 #define RTAS_GET_PE_MODE 1 386 #define RTAS_PE_MODE_NONE 0 387 #define RTAS_PE_MODE_NOT_SHARED 1 388 #define RTAS_PE_MODE_SHARED 2 389 390 /* ibm,read-slot-reset-state2 */ 391 #define RTAS_EEH_PE_STATE_NORMAL 0 392 #define RTAS_EEH_PE_STATE_RESET 1 393 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 394 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 395 #define RTAS_EEH_PE_STATE_UNAVAIL 5 396 #define RTAS_EEH_NOT_SUPPORT 0 397 #define RTAS_EEH_SUPPORT 1 398 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 399 #define RTAS_EEH_PE_RECOVER_INFO 0 400 401 /* ibm,set-slot-reset */ 402 #define RTAS_SLOT_RESET_DEACTIVATE 0 403 #define RTAS_SLOT_RESET_HOT 1 404 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 405 406 /* ibm,slot-error-detail */ 407 #define RTAS_SLOT_TEMP_ERR_LOG 1 408 #define RTAS_SLOT_PERM_ERR_LOG 2 409 410 /* RTAS return codes */ 411 #define RTAS_OUT_SUCCESS 0 412 #define RTAS_OUT_NO_ERRORS_FOUND 1 413 #define RTAS_OUT_HW_ERROR -1 414 #define RTAS_OUT_BUSY -2 415 #define RTAS_OUT_PARAM_ERROR -3 416 #define RTAS_OUT_NOT_SUPPORTED -3 417 #define RTAS_OUT_NO_SUCH_INDICATOR -3 418 #define RTAS_OUT_NOT_AUTHORIZED -9002 419 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 420 421 /* RTAS tokens */ 422 #define RTAS_TOKEN_BASE 0x2000 423 424 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 425 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 426 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 427 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 428 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 429 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 430 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 431 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 432 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 433 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 434 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 435 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 436 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 437 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 438 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 439 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 440 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 441 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 442 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 443 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 444 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 445 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 446 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 447 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 448 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 449 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 450 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 451 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 452 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 453 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 454 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 455 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 456 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 457 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 458 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 459 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 460 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 461 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 462 463 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x26) 464 465 /* RTAS ibm,get-system-parameter token values */ 466 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 467 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 468 #define RTAS_SYSPARM_UUID 48 469 470 /* RTAS indicator/sensor types 471 * 472 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 473 * 474 * NOTE: currently only DR-related sensors are implemented here 475 */ 476 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 477 #define RTAS_SENSOR_TYPE_DR 9002 478 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 479 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 480 481 /* Possible values for the platform-processor-diagnostics-run-mode parameter 482 * of the RTAS ibm,get-system-parameter call. 483 */ 484 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 485 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 486 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 487 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 488 489 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 490 { 491 return addr & ~0xF000000000000000ULL; 492 } 493 494 static inline uint32_t rtas_ld(target_ulong phys, int n) 495 { 496 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 497 } 498 499 static inline uint64_t rtas_ldq(target_ulong phys, int n) 500 { 501 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 502 } 503 504 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 505 { 506 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 507 } 508 509 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 510 uint32_t token, 511 uint32_t nargs, target_ulong args, 512 uint32_t nret, target_ulong rets); 513 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 514 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 515 uint32_t token, uint32_t nargs, target_ulong args, 516 uint32_t nret, target_ulong rets); 517 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 518 hwaddr rtas_size); 519 520 #define SPAPR_TCE_PAGE_SHIFT 12 521 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 522 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 523 524 #define SPAPR_VIO_BASE_LIOBN 0x00000000 525 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 526 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 527 (0x80000000 | ((phb_index) << 8) | (window_num)) 528 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 529 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 530 531 #define RTAS_ERROR_LOG_MAX 2048 532 533 #define RTAS_EVENT_SCAN_RATE 1 534 535 typedef struct sPAPRTCETable sPAPRTCETable; 536 537 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 538 #define SPAPR_TCE_TABLE(obj) \ 539 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 540 541 struct sPAPRTCETable { 542 DeviceState parent; 543 uint32_t liobn; 544 uint32_t nb_table; 545 uint64_t bus_offset; 546 uint32_t page_shift; 547 uint64_t *table; 548 bool bypass; 549 bool need_vfio; 550 int fd; 551 MemoryRegion iommu; 552 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 553 QLIST_ENTRY(sPAPRTCETable) list; 554 }; 555 556 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 557 558 struct sPAPREventLogEntry { 559 int log_type; 560 bool exception; 561 void *data; 562 QTAILQ_ENTRY(sPAPREventLogEntry) next; 563 }; 564 565 void spapr_events_init(sPAPRMachineState *sm); 566 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 567 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 568 target_ulong addr, target_ulong size, 569 bool cpu_update, bool memory_update); 570 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, 571 uint64_t bus_offset, 572 uint32_t page_shift, 573 uint32_t nb_table, 574 bool need_vfio); 575 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 576 577 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 578 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 579 uint32_t liobn, uint64_t window, uint32_t size); 580 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 581 sPAPRTCETable *tcet); 582 void spapr_pci_switch_vga(bool big_endian); 583 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 584 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 585 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 586 uint32_t count); 587 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 588 uint32_t count); 589 590 /* rtas-configure-connector state */ 591 struct sPAPRConfigureConnectorState { 592 uint32_t drc_index; 593 int fdt_offset; 594 int fdt_depth; 595 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next; 596 }; 597 598 void spapr_ccs_reset_hook(void *opaque); 599 600 #define TYPE_SPAPR_RTC "spapr-rtc" 601 #define TYPE_SPAPR_RNG "spapr-rng" 602 603 void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); 604 int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); 605 606 int spapr_rng_populate_dt(void *fdt); 607 608 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 609 610 /* 611 * This defines the maximum number of DIMM slots we can have for sPAPR 612 * guest. This is not defined by sPAPR but we are defining it to 32 slots 613 * based on default number of slots provided by PowerPC kernel. 614 */ 615 #define SPAPR_MAX_RAM_SLOTS 32 616 617 /* 1GB alignment for hotplug memory region */ 618 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 619 620 /* 621 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 622 * property under ibm,dynamic-reconfiguration-memory node. 623 */ 624 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 625 626 /* 627 * This flag value defines the LMB as assigned in ibm,dynamic-memory 628 * property under ibm,dynamic-reconfiguration-memory node. 629 */ 630 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 631 632 #endif /* !defined (__HW_SPAPR_H__) */ 633