1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 11 struct VIOsPAPRBus; 12 struct sPAPRPHBState; 13 struct sPAPRNVRAM; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 typedef struct sPAPREventSource sPAPREventSource; 16 typedef struct sPAPRPendingHPT sPAPRPendingHPT; 17 18 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 19 #define SPAPR_ENTRY_POINT 0x100 20 21 #define SPAPR_TIMEBASE_FREQ 512000000ULL 22 23 #define TYPE_SPAPR_RTC "spapr-rtc" 24 25 #define SPAPR_RTC(obj) \ 26 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 27 28 typedef struct sPAPRRTCState sPAPRRTCState; 29 struct sPAPRRTCState { 30 /*< private >*/ 31 DeviceState parent_obj; 32 int64_t ns_offset; 33 }; 34 35 typedef struct sPAPRDIMMState sPAPRDIMMState; 36 typedef struct sPAPRMachineClass sPAPRMachineClass; 37 38 #define TYPE_SPAPR_MACHINE "spapr-machine" 39 #define SPAPR_MACHINE(obj) \ 40 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 41 #define SPAPR_MACHINE_GET_CLASS(obj) \ 42 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 43 #define SPAPR_MACHINE_CLASS(klass) \ 44 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 45 46 typedef enum { 47 SPAPR_RESIZE_HPT_DEFAULT = 0, 48 SPAPR_RESIZE_HPT_DISABLED, 49 SPAPR_RESIZE_HPT_ENABLED, 50 SPAPR_RESIZE_HPT_REQUIRED, 51 } sPAPRResizeHPT; 52 53 /** 54 * sPAPRMachineClass: 55 */ 56 struct sPAPRMachineClass { 57 /*< private >*/ 58 MachineClass parent_class; 59 60 /*< public >*/ 61 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 62 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 63 const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */ 64 bool pre_2_10_has_unused_icps; 65 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 66 uint64_t *buid, hwaddr *pio, 67 hwaddr *mmio32, hwaddr *mmio64, 68 unsigned n_dma, uint32_t *liobns, Error **errp); 69 sPAPRResizeHPT resize_hpt_default; 70 }; 71 72 /** 73 * sPAPRMachineState: 74 */ 75 struct sPAPRMachineState { 76 /*< private >*/ 77 MachineState parent_obj; 78 79 struct VIOsPAPRBus *vio_bus; 80 QLIST_HEAD(, sPAPRPHBState) phbs; 81 struct sPAPRNVRAM *nvram; 82 ICSState *ics; 83 sPAPRRTCState rtc; 84 85 sPAPRResizeHPT resize_hpt; 86 void *htab; 87 uint32_t htab_shift; 88 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 89 sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 90 91 hwaddr rma_size; 92 int vrma_adjust; 93 ssize_t rtas_size; 94 void *rtas_blob; 95 long kernel_size; 96 bool kernel_le; 97 uint32_t initrd_base; 98 long initrd_size; 99 uint64_t rtc_offset; /* Now used only during incoming migration */ 100 struct PPCTimebase tb; 101 bool has_graphics; 102 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 103 104 Notifier epow_notifier; 105 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 106 bool use_hotplug_event_source; 107 sPAPREventSource *event_sources; 108 109 /* ibm,client-architecture-support option negotiation */ 110 bool cas_reboot; 111 bool cas_legacy_guest_workaround; 112 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 113 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 114 uint32_t max_compat_pvr; 115 116 /* Migration state */ 117 int htab_save_index; 118 bool htab_first_pass; 119 int htab_fd; 120 121 /* Pending DIMM unplug cache. It is populated when a LMB 122 * unplug starts. It can be regenerated if a migration 123 * occurs during the unplug process. */ 124 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 125 126 /*< public >*/ 127 char *kvm_type; 128 MemoryHotplugState hotplug_memory; 129 130 const char *icp_type; 131 }; 132 133 #define H_SUCCESS 0 134 #define H_BUSY 1 /* Hardware busy -- retry later */ 135 #define H_CLOSED 2 /* Resource closed */ 136 #define H_NOT_AVAILABLE 3 137 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 138 #define H_PARTIAL 5 139 #define H_IN_PROGRESS 14 /* Kind of like busy */ 140 #define H_PAGE_REGISTERED 15 141 #define H_PARTIAL_STORE 16 142 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 143 #define H_CONTINUE 18 /* Returned from H_Join on success */ 144 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 145 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 146 is a good time to retry */ 147 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 148 is a good time to retry */ 149 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 150 is a good time to retry */ 151 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 152 is a good time to retry */ 153 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 154 is a good time to retry */ 155 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 156 is a good time to retry */ 157 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 158 #define H_HARDWARE -1 /* Hardware error */ 159 #define H_FUNCTION -2 /* Function not supported */ 160 #define H_PRIVILEGE -3 /* Caller not privileged */ 161 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 162 #define H_BAD_MODE -5 /* Illegal msr value */ 163 #define H_PTEG_FULL -6 /* PTEG is full */ 164 #define H_NOT_FOUND -7 /* PTE was not found" */ 165 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 166 #define H_NO_MEM -9 167 #define H_AUTHORITY -10 168 #define H_PERMISSION -11 169 #define H_DROPPED -12 170 #define H_SOURCE_PARM -13 171 #define H_DEST_PARM -14 172 #define H_REMOTE_PARM -15 173 #define H_RESOURCE -16 174 #define H_ADAPTER_PARM -17 175 #define H_RH_PARM -18 176 #define H_RCQ_PARM -19 177 #define H_SCQ_PARM -20 178 #define H_EQ_PARM -21 179 #define H_RT_PARM -22 180 #define H_ST_PARM -23 181 #define H_SIGT_PARM -24 182 #define H_TOKEN_PARM -25 183 #define H_MLENGTH_PARM -27 184 #define H_MEM_PARM -28 185 #define H_MEM_ACCESS_PARM -29 186 #define H_ATTR_PARM -30 187 #define H_PORT_PARM -31 188 #define H_MCG_PARM -32 189 #define H_VL_PARM -33 190 #define H_TSIZE_PARM -34 191 #define H_TRACE_PARM -35 192 193 #define H_MASK_PARM -37 194 #define H_MCG_FULL -38 195 #define H_ALIAS_EXIST -39 196 #define H_P_COUNTER -40 197 #define H_TABLE_FULL -41 198 #define H_ALT_TABLE -42 199 #define H_MR_CONDITION -43 200 #define H_NOT_ENOUGH_RESOURCES -44 201 #define H_R_STATE -45 202 #define H_RESCINDEND -46 203 #define H_P2 -55 204 #define H_P3 -56 205 #define H_P4 -57 206 #define H_P5 -58 207 #define H_P6 -59 208 #define H_P7 -60 209 #define H_P8 -61 210 #define H_P9 -62 211 #define H_UNSUPPORTED_FLAG -256 212 #define H_MULTI_THREADS_ACTIVE -9005 213 214 215 /* Long Busy is a condition that can be returned by the firmware 216 * when a call cannot be completed now, but the identical call 217 * should be retried later. This prevents calls blocking in the 218 * firmware for long periods of time. Annoyingly the firmware can return 219 * a range of return codes, hinting at how long we should wait before 220 * retrying. If you don't care for the hint, the macro below is a good 221 * way to check for the long_busy return codes 222 */ 223 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 224 && (x <= H_LONG_BUSY_END_RANGE)) 225 226 /* Flags */ 227 #define H_LARGE_PAGE (1ULL<<(63-16)) 228 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 229 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 230 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 231 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 232 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 233 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 234 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 235 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 236 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 237 #define H_ANDCOND (1ULL<<(63-33)) 238 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 239 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 240 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 241 #define H_COPY_PAGE (1ULL<<(63-49)) 242 #define H_N (1ULL<<(63-61)) 243 #define H_PP1 (1ULL<<(63-62)) 244 #define H_PP2 (1ULL<<(63-63)) 245 246 /* Values for 2nd argument to H_SET_MODE */ 247 #define H_SET_MODE_RESOURCE_SET_CIABR 1 248 #define H_SET_MODE_RESOURCE_SET_DAWR 2 249 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 250 #define H_SET_MODE_RESOURCE_LE 4 251 252 /* Flags for H_SET_MODE_RESOURCE_LE */ 253 #define H_SET_MODE_ENDIAN_BIG 0 254 #define H_SET_MODE_ENDIAN_LITTLE 1 255 256 /* VASI States */ 257 #define H_VASI_INVALID 0 258 #define H_VASI_ENABLED 1 259 #define H_VASI_ABORTED 2 260 #define H_VASI_SUSPENDING 3 261 #define H_VASI_SUSPENDED 4 262 #define H_VASI_RESUMED 5 263 #define H_VASI_COMPLETED 6 264 265 /* DABRX flags */ 266 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 267 #define H_DABRX_KERNEL (1ULL<<(63-62)) 268 #define H_DABRX_USER (1ULL<<(63-63)) 269 270 /* Each control block has to be on a 4K boundary */ 271 #define H_CB_ALIGNMENT 4096 272 273 /* pSeries hypervisor opcodes */ 274 #define H_REMOVE 0x04 275 #define H_ENTER 0x08 276 #define H_READ 0x0c 277 #define H_CLEAR_MOD 0x10 278 #define H_CLEAR_REF 0x14 279 #define H_PROTECT 0x18 280 #define H_GET_TCE 0x1c 281 #define H_PUT_TCE 0x20 282 #define H_SET_SPRG0 0x24 283 #define H_SET_DABR 0x28 284 #define H_PAGE_INIT 0x2c 285 #define H_SET_ASR 0x30 286 #define H_ASR_ON 0x34 287 #define H_ASR_OFF 0x38 288 #define H_LOGICAL_CI_LOAD 0x3c 289 #define H_LOGICAL_CI_STORE 0x40 290 #define H_LOGICAL_CACHE_LOAD 0x44 291 #define H_LOGICAL_CACHE_STORE 0x48 292 #define H_LOGICAL_ICBI 0x4c 293 #define H_LOGICAL_DCBF 0x50 294 #define H_GET_TERM_CHAR 0x54 295 #define H_PUT_TERM_CHAR 0x58 296 #define H_REAL_TO_LOGICAL 0x5c 297 #define H_HYPERVISOR_DATA 0x60 298 #define H_EOI 0x64 299 #define H_CPPR 0x68 300 #define H_IPI 0x6c 301 #define H_IPOLL 0x70 302 #define H_XIRR 0x74 303 #define H_PERFMON 0x7c 304 #define H_MIGRATE_DMA 0x78 305 #define H_REGISTER_VPA 0xDC 306 #define H_CEDE 0xE0 307 #define H_CONFER 0xE4 308 #define H_PROD 0xE8 309 #define H_GET_PPP 0xEC 310 #define H_SET_PPP 0xF0 311 #define H_PURR 0xF4 312 #define H_PIC 0xF8 313 #define H_REG_CRQ 0xFC 314 #define H_FREE_CRQ 0x100 315 #define H_VIO_SIGNAL 0x104 316 #define H_SEND_CRQ 0x108 317 #define H_COPY_RDMA 0x110 318 #define H_REGISTER_LOGICAL_LAN 0x114 319 #define H_FREE_LOGICAL_LAN 0x118 320 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 321 #define H_SEND_LOGICAL_LAN 0x120 322 #define H_BULK_REMOVE 0x124 323 #define H_MULTICAST_CTRL 0x130 324 #define H_SET_XDABR 0x134 325 #define H_STUFF_TCE 0x138 326 #define H_PUT_TCE_INDIRECT 0x13C 327 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 328 #define H_VTERM_PARTNER_INFO 0x150 329 #define H_REGISTER_VTERM 0x154 330 #define H_FREE_VTERM 0x158 331 #define H_RESET_EVENTS 0x15C 332 #define H_ALLOC_RESOURCE 0x160 333 #define H_FREE_RESOURCE 0x164 334 #define H_MODIFY_QP 0x168 335 #define H_QUERY_QP 0x16C 336 #define H_REREGISTER_PMR 0x170 337 #define H_REGISTER_SMR 0x174 338 #define H_QUERY_MR 0x178 339 #define H_QUERY_MW 0x17C 340 #define H_QUERY_HCA 0x180 341 #define H_QUERY_PORT 0x184 342 #define H_MODIFY_PORT 0x188 343 #define H_DEFINE_AQP1 0x18C 344 #define H_GET_TRACE_BUFFER 0x190 345 #define H_DEFINE_AQP0 0x194 346 #define H_RESIZE_MR 0x198 347 #define H_ATTACH_MCQP 0x19C 348 #define H_DETACH_MCQP 0x1A0 349 #define H_CREATE_RPT 0x1A4 350 #define H_REMOVE_RPT 0x1A8 351 #define H_REGISTER_RPAGES 0x1AC 352 #define H_DISABLE_AND_GETC 0x1B0 353 #define H_ERROR_DATA 0x1B4 354 #define H_GET_HCA_INFO 0x1B8 355 #define H_GET_PERF_COUNT 0x1BC 356 #define H_MANAGE_TRACE 0x1C0 357 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 358 #define H_QUERY_INT_STATE 0x1E4 359 #define H_POLL_PENDING 0x1D8 360 #define H_ILLAN_ATTRIBUTES 0x244 361 #define H_MODIFY_HEA_QP 0x250 362 #define H_QUERY_HEA_QP 0x254 363 #define H_QUERY_HEA 0x258 364 #define H_QUERY_HEA_PORT 0x25C 365 #define H_MODIFY_HEA_PORT 0x260 366 #define H_REG_BCMC 0x264 367 #define H_DEREG_BCMC 0x268 368 #define H_REGISTER_HEA_RPAGES 0x26C 369 #define H_DISABLE_AND_GET_HEA 0x270 370 #define H_GET_HEA_INFO 0x274 371 #define H_ALLOC_HEA_RESOURCE 0x278 372 #define H_ADD_CONN 0x284 373 #define H_DEL_CONN 0x288 374 #define H_JOIN 0x298 375 #define H_VASI_STATE 0x2A4 376 #define H_ENABLE_CRQ 0x2B0 377 #define H_GET_EM_PARMS 0x2B8 378 #define H_SET_MPP 0x2D0 379 #define H_GET_MPP 0x2D4 380 #define H_XIRR_X 0x2FC 381 #define H_RANDOM 0x300 382 #define H_SET_MODE 0x31C 383 #define H_RESIZE_HPT_PREPARE 0x36C 384 #define H_RESIZE_HPT_COMMIT 0x370 385 #define H_CLEAN_SLB 0x374 386 #define H_INVALIDATE_PID 0x378 387 #define H_REGISTER_PROC_TBL 0x37C 388 #define H_SIGNAL_SYS_RESET 0x380 389 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET 390 391 /* The hcalls above are standardized in PAPR and implemented by pHyp 392 * as well. 393 * 394 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 395 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 396 * for "platform-specific" hcalls. 397 */ 398 #define KVMPPC_HCALL_BASE 0xf000 399 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 400 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 401 /* Client Architecture support */ 402 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 403 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 404 405 typedef struct sPAPRDeviceTreeUpdateHeader { 406 uint32_t version_id; 407 } sPAPRDeviceTreeUpdateHeader; 408 409 #define hcall_dprintf(fmt, ...) \ 410 do { \ 411 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 412 } while (0) 413 414 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 415 target_ulong opcode, 416 target_ulong *args); 417 418 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 419 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 420 target_ulong *args); 421 422 /* ibm,set-eeh-option */ 423 #define RTAS_EEH_DISABLE 0 424 #define RTAS_EEH_ENABLE 1 425 #define RTAS_EEH_THAW_IO 2 426 #define RTAS_EEH_THAW_DMA 3 427 428 /* ibm,get-config-addr-info2 */ 429 #define RTAS_GET_PE_ADDR 0 430 #define RTAS_GET_PE_MODE 1 431 #define RTAS_PE_MODE_NONE 0 432 #define RTAS_PE_MODE_NOT_SHARED 1 433 #define RTAS_PE_MODE_SHARED 2 434 435 /* ibm,read-slot-reset-state2 */ 436 #define RTAS_EEH_PE_STATE_NORMAL 0 437 #define RTAS_EEH_PE_STATE_RESET 1 438 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 439 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 440 #define RTAS_EEH_PE_STATE_UNAVAIL 5 441 #define RTAS_EEH_NOT_SUPPORT 0 442 #define RTAS_EEH_SUPPORT 1 443 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 444 #define RTAS_EEH_PE_RECOVER_INFO 0 445 446 /* ibm,set-slot-reset */ 447 #define RTAS_SLOT_RESET_DEACTIVATE 0 448 #define RTAS_SLOT_RESET_HOT 1 449 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 450 451 /* ibm,slot-error-detail */ 452 #define RTAS_SLOT_TEMP_ERR_LOG 1 453 #define RTAS_SLOT_PERM_ERR_LOG 2 454 455 /* RTAS return codes */ 456 #define RTAS_OUT_SUCCESS 0 457 #define RTAS_OUT_NO_ERRORS_FOUND 1 458 #define RTAS_OUT_HW_ERROR -1 459 #define RTAS_OUT_BUSY -2 460 #define RTAS_OUT_PARAM_ERROR -3 461 #define RTAS_OUT_NOT_SUPPORTED -3 462 #define RTAS_OUT_NO_SUCH_INDICATOR -3 463 #define RTAS_OUT_NOT_AUTHORIZED -9002 464 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 465 466 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 467 #define RTAS_DDW_PGSIZE_4K 0x01 468 #define RTAS_DDW_PGSIZE_64K 0x02 469 #define RTAS_DDW_PGSIZE_16M 0x04 470 #define RTAS_DDW_PGSIZE_32M 0x08 471 #define RTAS_DDW_PGSIZE_64M 0x10 472 #define RTAS_DDW_PGSIZE_128M 0x20 473 #define RTAS_DDW_PGSIZE_256M 0x40 474 #define RTAS_DDW_PGSIZE_16G 0x80 475 476 /* RTAS tokens */ 477 #define RTAS_TOKEN_BASE 0x2000 478 479 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 480 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 481 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 482 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 483 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 484 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 485 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 486 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 487 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 488 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 489 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 490 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 491 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 492 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 493 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 494 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 495 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 496 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 497 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 498 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 499 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 500 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 501 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 502 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 503 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 504 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 505 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 506 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 507 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 508 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 509 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 510 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 511 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 512 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 513 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 514 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 515 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 516 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 517 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 518 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 519 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 520 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 521 522 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 523 524 /* RTAS ibm,get-system-parameter token values */ 525 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 526 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 527 #define RTAS_SYSPARM_UUID 48 528 529 /* RTAS indicator/sensor types 530 * 531 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 532 * 533 * NOTE: currently only DR-related sensors are implemented here 534 */ 535 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 536 #define RTAS_SENSOR_TYPE_DR 9002 537 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 538 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 539 540 /* Possible values for the platform-processor-diagnostics-run-mode parameter 541 * of the RTAS ibm,get-system-parameter call. 542 */ 543 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 544 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 545 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 546 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 547 548 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 549 { 550 return addr & ~0xF000000000000000ULL; 551 } 552 553 static inline uint32_t rtas_ld(target_ulong phys, int n) 554 { 555 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 556 } 557 558 static inline uint64_t rtas_ldq(target_ulong phys, int n) 559 { 560 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 561 } 562 563 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 564 { 565 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 566 } 567 568 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 569 uint32_t token, 570 uint32_t nargs, target_ulong args, 571 uint32_t nret, target_ulong rets); 572 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 573 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 574 uint32_t token, uint32_t nargs, target_ulong args, 575 uint32_t nret, target_ulong rets); 576 void spapr_dt_rtas_tokens(void *fdt, int rtas); 577 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 578 579 #define SPAPR_TCE_PAGE_SHIFT 12 580 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 581 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 582 583 #define SPAPR_VIO_BASE_LIOBN 0x00000000 584 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 585 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 586 (0x80000000 | ((phb_index) << 8) | (window_num)) 587 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 588 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 589 590 #define RTAS_ERROR_LOG_MAX 2048 591 592 #define RTAS_EVENT_SCAN_RATE 1 593 594 typedef struct sPAPRTCETable sPAPRTCETable; 595 596 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 597 #define SPAPR_TCE_TABLE(obj) \ 598 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 599 600 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 601 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 602 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 603 604 struct sPAPRTCETable { 605 DeviceState parent; 606 uint32_t liobn; 607 uint32_t nb_table; 608 uint64_t bus_offset; 609 uint32_t page_shift; 610 uint64_t *table; 611 uint32_t mig_nb_table; 612 uint64_t *mig_table; 613 bool bypass; 614 bool need_vfio; 615 int fd; 616 MemoryRegion root; 617 IOMMUMemoryRegion iommu; 618 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 619 QLIST_ENTRY(sPAPRTCETable) list; 620 }; 621 622 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 623 624 struct sPAPREventLogEntry { 625 uint32_t summary; 626 uint32_t extended_length; 627 void *extended_log; 628 QTAILQ_ENTRY(sPAPREventLogEntry) next; 629 }; 630 631 void spapr_events_init(sPAPRMachineState *sm); 632 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 633 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 634 target_ulong addr, target_ulong size, 635 sPAPROptionVector *ov5_updates); 636 void close_htab_fd(sPAPRMachineState *spapr); 637 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 638 void spapr_free_hpt(sPAPRMachineState *spapr); 639 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 640 void spapr_tce_table_enable(sPAPRTCETable *tcet, 641 uint32_t page_shift, uint64_t bus_offset, 642 uint32_t nb_table); 643 void spapr_tce_table_disable(sPAPRTCETable *tcet); 644 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 645 646 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 647 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 648 uint32_t liobn, uint64_t window, uint32_t size); 649 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 650 sPAPRTCETable *tcet); 651 void spapr_pci_switch_vga(bool big_endian); 652 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 653 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 654 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 655 uint32_t count); 656 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 657 uint32_t count); 658 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 659 uint32_t count, uint32_t index); 660 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 661 uint32_t count, uint32_t index); 662 void spapr_cpu_parse_features(sPAPRMachineState *spapr); 663 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 664 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 665 Error **errp); 666 void spapr_clear_pending_events(sPAPRMachineState *spapr); 667 668 /* CPU and LMB DRC release callbacks. */ 669 void spapr_core_release(DeviceState *dev); 670 void spapr_lmb_release(DeviceState *dev); 671 672 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 673 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 674 675 #define TYPE_SPAPR_RNG "spapr-rng" 676 677 int spapr_rng_populate_dt(void *fdt); 678 679 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 680 681 /* 682 * This defines the maximum number of DIMM slots we can have for sPAPR 683 * guest. This is not defined by sPAPR but we are defining it to 32 slots 684 * based on default number of slots provided by PowerPC kernel. 685 */ 686 #define SPAPR_MAX_RAM_SLOTS 32 687 688 /* 1GB alignment for hotplug memory region */ 689 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 690 691 /* 692 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 693 * property under ibm,dynamic-reconfiguration-memory node. 694 */ 695 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 696 697 /* 698 * Defines for flag value in ibm,dynamic-memory property under 699 * ibm,dynamic-reconfiguration-memory node. 700 */ 701 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 702 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 703 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 704 705 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 706 707 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 708 709 int spapr_vcpu_id(PowerPCCPU *cpu); 710 PowerPCCPU *spapr_find_cpu(int vcpu_id); 711 712 #endif /* HW_SPAPR_H */ 713