1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "qom/object.h" 12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13 #include "hw/ppc/xics.h" /* For ICSState */ 14 #include "hw/ppc/spapr_tpm_proxy.h" 15 16 struct SpaprVioBus; 17 struct SpaprPhbState; 18 struct SpaprNvram; 19 20 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 21 typedef struct SpaprEventSource SpaprEventSource; 22 typedef struct SpaprPendingHpt SpaprPendingHpt; 23 24 typedef struct Vof Vof; 25 26 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 27 #define SPAPR_ENTRY_POINT 0x100 28 29 #define SPAPR_TIMEBASE_FREQ 512000000ULL 30 31 #define TYPE_SPAPR_RTC "spapr-rtc" 32 33 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 34 35 struct SpaprRtcState { 36 /*< private >*/ 37 DeviceState parent_obj; 38 int64_t ns_offset; 39 }; 40 41 typedef struct SpaprDimmState SpaprDimmState; 42 43 #define TYPE_SPAPR_MACHINE "spapr-machine" 44 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 45 46 typedef enum { 47 SPAPR_RESIZE_HPT_DEFAULT = 0, 48 SPAPR_RESIZE_HPT_DISABLED, 49 SPAPR_RESIZE_HPT_ENABLED, 50 SPAPR_RESIZE_HPT_REQUIRED, 51 } SpaprResizeHpt; 52 53 /** 54 * Capabilities 55 */ 56 57 /* Hardware Transactional Memory */ 58 #define SPAPR_CAP_HTM 0x00 59 /* Vector Scalar Extensions */ 60 #define SPAPR_CAP_VSX 0x01 61 /* Decimal Floating Point */ 62 #define SPAPR_CAP_DFP 0x02 63 /* Cache Flush on Privilege Change */ 64 #define SPAPR_CAP_CFPC 0x03 65 /* Speculation Barrier Bounds Checking */ 66 #define SPAPR_CAP_SBBC 0x04 67 /* Indirect Branch Serialisation */ 68 #define SPAPR_CAP_IBS 0x05 69 /* HPT Maximum Page Size (encoded as a shift) */ 70 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 71 /* Nested KVM-HV */ 72 #define SPAPR_CAP_NESTED_KVM_HV 0x07 73 /* Large Decrementer */ 74 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 75 /* Count Cache Flush Assist HW Instruction */ 76 #define SPAPR_CAP_CCF_ASSIST 0x09 77 /* Implements PAPR FWNMI option */ 78 #define SPAPR_CAP_FWNMI 0x0A 79 /* Support H_RPT_INVALIDATE */ 80 #define SPAPR_CAP_RPT_INVALIDATE 0x0B 81 /* Support for AIL modes */ 82 #define SPAPR_CAP_AIL_MODE_3 0x0C 83 /* Num Caps */ 84 #define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1) 85 86 /* 87 * Capability Values 88 */ 89 /* Bool Caps */ 90 #define SPAPR_CAP_OFF 0x00 91 #define SPAPR_CAP_ON 0x01 92 93 /* Custom Caps */ 94 95 /* Generic */ 96 #define SPAPR_CAP_BROKEN 0x00 97 #define SPAPR_CAP_WORKAROUND 0x01 98 #define SPAPR_CAP_FIXED 0x02 99 /* SPAPR_CAP_IBS (cap-ibs) */ 100 #define SPAPR_CAP_FIXED_IBS 0x02 101 #define SPAPR_CAP_FIXED_CCD 0x03 102 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 103 104 #define FDT_MAX_SIZE 0x200000 105 106 /* Max number of GPUs per system */ 107 #define NVGPU_MAX_NUM 6 108 109 /* Max number of NUMA nodes */ 110 #define NUMA_NODES_MAX_NUM (MAX_NODES + NVGPU_MAX_NUM) 111 112 /* 113 * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 114 * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 115 * kernel source. It represents the amount of associativity domains 116 * for non-CPU resources. 117 * 118 * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 119 * array for any non-CPU resource. 120 */ 121 #define FORM1_DIST_REF_POINTS 4 122 #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 123 124 /* 125 * FORM2 NUMA affinity has a single associativity domain, giving 126 * us a assoc size of 2. 127 */ 128 #define FORM2_DIST_REF_POINTS 1 129 #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 130 131 typedef struct SpaprCapabilities SpaprCapabilities; 132 struct SpaprCapabilities { 133 uint8_t caps[SPAPR_CAP_NUM]; 134 }; 135 136 /** 137 * SpaprMachineClass: 138 */ 139 struct SpaprMachineClass { 140 /*< private >*/ 141 MachineClass parent_class; 142 143 /*< public >*/ 144 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 145 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 146 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 147 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 148 bool pre_2_10_has_unused_icps; 149 bool legacy_irq_allocation; 150 uint32_t nr_xirqs; 151 bool broken_host_serial_model; /* present real host info to the guest */ 152 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 153 bool linux_pci_probe; 154 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 155 hwaddr rma_limit; /* clamp the RMA to this size */ 156 bool pre_5_1_assoc_refpoints; 157 bool pre_5_2_numa_associativity; 158 bool pre_6_2_numa_affinity; 159 160 bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 161 uint64_t *buid, hwaddr *pio, 162 hwaddr *mmio32, hwaddr *mmio64, 163 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 164 hwaddr *nv2atsd, Error **errp); 165 SpaprResizeHpt resize_hpt_default; 166 SpaprCapabilities default_caps; 167 SpaprIrq *irq; 168 }; 169 170 #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ 171 172 #define TYPE_SPAPR_WDT "spapr-wdt" 173 OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) 174 175 typedef struct SpaprWatchdog { 176 /*< private >*/ 177 DeviceState parent_obj; 178 /*< public >*/ 179 180 QEMUTimer timer; 181 uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ 182 uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ 183 } SpaprWatchdog; 184 185 /** 186 * SpaprMachineState: 187 */ 188 struct SpaprMachineState { 189 /*< private >*/ 190 MachineState parent_obj; 191 192 struct SpaprVioBus *vio_bus; 193 QLIST_HEAD(, SpaprPhbState) phbs; 194 struct SpaprNvram *nvram; 195 SpaprRtcState rtc; 196 197 SpaprResizeHpt resize_hpt; 198 void *htab; 199 uint32_t htab_shift; 200 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ 201 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 202 203 hwaddr rma_size; 204 uint32_t fdt_size; 205 uint32_t fdt_initial_size; 206 void *fdt_blob; 207 long kernel_size; 208 bool kernel_le; 209 uint64_t kernel_addr; 210 uint32_t initrd_base; 211 long initrd_size; 212 Vof *vof; 213 uint64_t rtc_offset; /* Now used only during incoming migration */ 214 struct PPCTimebase tb; 215 bool want_stdout_path; 216 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 217 218 /* Nested HV support (TCG only) */ 219 uint64_t nested_ptcr; 220 221 Notifier epow_notifier; 222 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 223 bool use_hotplug_event_source; 224 SpaprEventSource *event_sources; 225 226 /* ibm,client-architecture-support option negotiation */ 227 bool cas_pre_isa3_guest; 228 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 229 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 230 uint32_t max_compat_pvr; 231 232 /* Migration state */ 233 int htab_save_index; 234 bool htab_first_pass; 235 int htab_fd; 236 237 /* Pending DIMM unplug cache. It is populated when a LMB 238 * unplug starts. It can be regenerated if a migration 239 * occurs during the unplug process. */ 240 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 241 242 /* State related to FWNMI option */ 243 244 /* System Reset and Machine Check Notification Routine addresses 245 * registered by "ibm,nmi-register" RTAS call. 246 */ 247 target_ulong fwnmi_system_reset_addr; 248 target_ulong fwnmi_machine_check_addr; 249 250 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 251 * set to -1 if a FWNMI machine check is not in progress, else is set to 252 * the CPU that was delivered the machine check, and is set back to -1 253 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 254 * to synchronize other CPUs. 255 */ 256 int fwnmi_machine_check_interlock; 257 QemuCond fwnmi_machine_check_interlock_cond; 258 259 /* Set by -boot */ 260 char *boot_device; 261 262 /*< public >*/ 263 char *kvm_type; 264 char *host_model; 265 char *host_serial; 266 267 int32_t irq_map_nr; 268 unsigned long *irq_map; 269 SpaprIrq *irq; 270 qemu_irq *qirqs; 271 SpaprInterruptController *active_intc; 272 ICSState *ics; 273 SpaprXive *xive; 274 275 bool cmd_line_caps[SPAPR_CAP_NUM]; 276 SpaprCapabilities def, eff, mig; 277 278 unsigned gpu_numa_id; 279 SpaprTpmProxy *tpm_proxy; 280 281 uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 282 uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 283 284 Error *fwnmi_migration_blocker; 285 286 SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; 287 }; 288 289 #define H_SUCCESS 0 290 #define H_BUSY 1 /* Hardware busy -- retry later */ 291 #define H_CLOSED 2 /* Resource closed */ 292 #define H_NOT_AVAILABLE 3 293 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 294 #define H_PARTIAL 5 295 #define H_IN_PROGRESS 14 /* Kind of like busy */ 296 #define H_PAGE_REGISTERED 15 297 #define H_PARTIAL_STORE 16 298 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 299 #define H_CONTINUE 18 /* Returned from H_Join on success */ 300 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 301 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 302 is a good time to retry */ 303 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 304 is a good time to retry */ 305 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 306 is a good time to retry */ 307 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 308 is a good time to retry */ 309 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 310 is a good time to retry */ 311 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 312 is a good time to retry */ 313 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 314 #define H_HARDWARE -1 /* Hardware error */ 315 #define H_FUNCTION -2 /* Function not supported */ 316 #define H_PRIVILEGE -3 /* Caller not privileged */ 317 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 318 #define H_BAD_MODE -5 /* Illegal msr value */ 319 #define H_PTEG_FULL -6 /* PTEG is full */ 320 #define H_NOT_FOUND -7 /* PTE was not found" */ 321 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 322 #define H_NO_MEM -9 323 #define H_AUTHORITY -10 324 #define H_PERMISSION -11 325 #define H_DROPPED -12 326 #define H_SOURCE_PARM -13 327 #define H_DEST_PARM -14 328 #define H_REMOTE_PARM -15 329 #define H_RESOURCE -16 330 #define H_ADAPTER_PARM -17 331 #define H_RH_PARM -18 332 #define H_RCQ_PARM -19 333 #define H_SCQ_PARM -20 334 #define H_EQ_PARM -21 335 #define H_RT_PARM -22 336 #define H_ST_PARM -23 337 #define H_SIGT_PARM -24 338 #define H_TOKEN_PARM -25 339 #define H_MLENGTH_PARM -27 340 #define H_MEM_PARM -28 341 #define H_MEM_ACCESS_PARM -29 342 #define H_ATTR_PARM -30 343 #define H_PORT_PARM -31 344 #define H_MCG_PARM -32 345 #define H_VL_PARM -33 346 #define H_TSIZE_PARM -34 347 #define H_TRACE_PARM -35 348 349 #define H_MASK_PARM -37 350 #define H_MCG_FULL -38 351 #define H_ALIAS_EXIST -39 352 #define H_P_COUNTER -40 353 #define H_TABLE_FULL -41 354 #define H_ALT_TABLE -42 355 #define H_MR_CONDITION -43 356 #define H_NOT_ENOUGH_RESOURCES -44 357 #define H_R_STATE -45 358 #define H_RESCINDEND -46 359 #define H_P2 -55 360 #define H_P3 -56 361 #define H_P4 -57 362 #define H_P5 -58 363 #define H_P6 -59 364 #define H_P7 -60 365 #define H_P8 -61 366 #define H_P9 -62 367 #define H_NOOP -63 368 #define H_UNSUPPORTED -67 369 #define H_OVERLAP -68 370 #define H_UNSUPPORTED_FLAG -256 371 #define H_MULTI_THREADS_ACTIVE -9005 372 373 374 /* Long Busy is a condition that can be returned by the firmware 375 * when a call cannot be completed now, but the identical call 376 * should be retried later. This prevents calls blocking in the 377 * firmware for long periods of time. Annoyingly the firmware can return 378 * a range of return codes, hinting at how long we should wait before 379 * retrying. If you don't care for the hint, the macro below is a good 380 * way to check for the long_busy return codes 381 */ 382 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 383 && (x <= H_LONG_BUSY_END_RANGE)) 384 385 /* Flags */ 386 #define H_LARGE_PAGE (1ULL<<(63-16)) 387 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 388 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 389 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 390 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 391 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 392 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 393 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 394 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 395 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 396 #define H_ANDCOND (1ULL<<(63-33)) 397 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 398 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 399 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 400 #define H_COPY_PAGE (1ULL<<(63-49)) 401 #define H_N (1ULL<<(63-61)) 402 #define H_PP1 (1ULL<<(63-62)) 403 #define H_PP2 (1ULL<<(63-63)) 404 405 /* Values for 2nd argument to H_SET_MODE */ 406 #define H_SET_MODE_RESOURCE_SET_CIABR 1 407 #define H_SET_MODE_RESOURCE_SET_DAWR0 2 408 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 409 #define H_SET_MODE_RESOURCE_LE 4 410 411 /* Flags for H_SET_MODE_RESOURCE_LE */ 412 #define H_SET_MODE_ENDIAN_BIG 0 413 #define H_SET_MODE_ENDIAN_LITTLE 1 414 415 /* VASI States */ 416 #define H_VASI_INVALID 0 417 #define H_VASI_ENABLED 1 418 #define H_VASI_ABORTED 2 419 #define H_VASI_SUSPENDING 3 420 #define H_VASI_SUSPENDED 4 421 #define H_VASI_RESUMED 5 422 #define H_VASI_COMPLETED 6 423 424 /* DABRX flags */ 425 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 426 #define H_DABRX_KERNEL (1ULL<<(63-62)) 427 #define H_DABRX_USER (1ULL<<(63-63)) 428 429 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 430 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 431 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 432 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 433 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 434 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 435 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 436 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 437 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 438 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 439 440 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 441 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 442 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 443 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 444 #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 445 #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 446 447 /* Each control block has to be on a 4K boundary */ 448 #define H_CB_ALIGNMENT 4096 449 450 /* pSeries hypervisor opcodes */ 451 #define H_REMOVE 0x04 452 #define H_ENTER 0x08 453 #define H_READ 0x0c 454 #define H_CLEAR_MOD 0x10 455 #define H_CLEAR_REF 0x14 456 #define H_PROTECT 0x18 457 #define H_GET_TCE 0x1c 458 #define H_PUT_TCE 0x20 459 #define H_SET_SPRG0 0x24 460 #define H_SET_DABR 0x28 461 #define H_PAGE_INIT 0x2c 462 #define H_SET_ASR 0x30 463 #define H_ASR_ON 0x34 464 #define H_ASR_OFF 0x38 465 #define H_LOGICAL_CI_LOAD 0x3c 466 #define H_LOGICAL_CI_STORE 0x40 467 #define H_LOGICAL_CACHE_LOAD 0x44 468 #define H_LOGICAL_CACHE_STORE 0x48 469 #define H_LOGICAL_ICBI 0x4c 470 #define H_LOGICAL_DCBF 0x50 471 #define H_GET_TERM_CHAR 0x54 472 #define H_PUT_TERM_CHAR 0x58 473 #define H_REAL_TO_LOGICAL 0x5c 474 #define H_HYPERVISOR_DATA 0x60 475 #define H_EOI 0x64 476 #define H_CPPR 0x68 477 #define H_IPI 0x6c 478 #define H_IPOLL 0x70 479 #define H_XIRR 0x74 480 #define H_PERFMON 0x7c 481 #define H_MIGRATE_DMA 0x78 482 #define H_REGISTER_VPA 0xDC 483 #define H_CEDE 0xE0 484 #define H_CONFER 0xE4 485 #define H_PROD 0xE8 486 #define H_GET_PPP 0xEC 487 #define H_SET_PPP 0xF0 488 #define H_PURR 0xF4 489 #define H_PIC 0xF8 490 #define H_REG_CRQ 0xFC 491 #define H_FREE_CRQ 0x100 492 #define H_VIO_SIGNAL 0x104 493 #define H_SEND_CRQ 0x108 494 #define H_COPY_RDMA 0x110 495 #define H_REGISTER_LOGICAL_LAN 0x114 496 #define H_FREE_LOGICAL_LAN 0x118 497 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 498 #define H_SEND_LOGICAL_LAN 0x120 499 #define H_BULK_REMOVE 0x124 500 #define H_MULTICAST_CTRL 0x130 501 #define H_SET_XDABR 0x134 502 #define H_STUFF_TCE 0x138 503 #define H_PUT_TCE_INDIRECT 0x13C 504 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 505 #define H_VTERM_PARTNER_INFO 0x150 506 #define H_REGISTER_VTERM 0x154 507 #define H_FREE_VTERM 0x158 508 #define H_RESET_EVENTS 0x15C 509 #define H_ALLOC_RESOURCE 0x160 510 #define H_FREE_RESOURCE 0x164 511 #define H_MODIFY_QP 0x168 512 #define H_QUERY_QP 0x16C 513 #define H_REREGISTER_PMR 0x170 514 #define H_REGISTER_SMR 0x174 515 #define H_QUERY_MR 0x178 516 #define H_QUERY_MW 0x17C 517 #define H_QUERY_HCA 0x180 518 #define H_QUERY_PORT 0x184 519 #define H_MODIFY_PORT 0x188 520 #define H_DEFINE_AQP1 0x18C 521 #define H_GET_TRACE_BUFFER 0x190 522 #define H_DEFINE_AQP0 0x194 523 #define H_RESIZE_MR 0x198 524 #define H_ATTACH_MCQP 0x19C 525 #define H_DETACH_MCQP 0x1A0 526 #define H_CREATE_RPT 0x1A4 527 #define H_REMOVE_RPT 0x1A8 528 #define H_REGISTER_RPAGES 0x1AC 529 #define H_DISABLE_AND_GETC 0x1B0 530 #define H_ERROR_DATA 0x1B4 531 #define H_GET_HCA_INFO 0x1B8 532 #define H_GET_PERF_COUNT 0x1BC 533 #define H_MANAGE_TRACE 0x1C0 534 #define H_GET_CPU_CHARACTERISTICS 0x1C8 535 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 536 #define H_QUERY_INT_STATE 0x1E4 537 #define H_POLL_PENDING 0x1D8 538 #define H_ILLAN_ATTRIBUTES 0x244 539 #define H_MODIFY_HEA_QP 0x250 540 #define H_QUERY_HEA_QP 0x254 541 #define H_QUERY_HEA 0x258 542 #define H_QUERY_HEA_PORT 0x25C 543 #define H_MODIFY_HEA_PORT 0x260 544 #define H_REG_BCMC 0x264 545 #define H_DEREG_BCMC 0x268 546 #define H_REGISTER_HEA_RPAGES 0x26C 547 #define H_DISABLE_AND_GET_HEA 0x270 548 #define H_GET_HEA_INFO 0x274 549 #define H_ALLOC_HEA_RESOURCE 0x278 550 #define H_ADD_CONN 0x284 551 #define H_DEL_CONN 0x288 552 #define H_JOIN 0x298 553 #define H_VASI_STATE 0x2A4 554 #define H_ENABLE_CRQ 0x2B0 555 #define H_GET_EM_PARMS 0x2B8 556 #define H_SET_MPP 0x2D0 557 #define H_GET_MPP 0x2D4 558 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 559 #define H_XIRR_X 0x2FC 560 #define H_RANDOM 0x300 561 #define H_SET_MODE 0x31C 562 #define H_RESIZE_HPT_PREPARE 0x36C 563 #define H_RESIZE_HPT_COMMIT 0x370 564 #define H_CLEAN_SLB 0x374 565 #define H_INVALIDATE_PID 0x378 566 #define H_REGISTER_PROC_TBL 0x37C 567 #define H_SIGNAL_SYS_RESET 0x380 568 569 #define H_INT_GET_SOURCE_INFO 0x3A8 570 #define H_INT_SET_SOURCE_CONFIG 0x3AC 571 #define H_INT_GET_SOURCE_CONFIG 0x3B0 572 #define H_INT_GET_QUEUE_INFO 0x3B4 573 #define H_INT_SET_QUEUE_CONFIG 0x3B8 574 #define H_INT_GET_QUEUE_CONFIG 0x3BC 575 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 576 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 577 #define H_INT_ESB 0x3C8 578 #define H_INT_SYNC 0x3CC 579 #define H_INT_RESET 0x3D0 580 #define H_SCM_READ_METADATA 0x3E4 581 #define H_SCM_WRITE_METADATA 0x3E8 582 #define H_SCM_BIND_MEM 0x3EC 583 #define H_SCM_UNBIND_MEM 0x3F0 584 #define H_SCM_UNBIND_ALL 0x3FC 585 #define H_SCM_HEALTH 0x400 586 #define H_RPT_INVALIDATE 0x448 587 #define H_SCM_FLUSH 0x44C 588 #define H_WATCHDOG 0x45C 589 590 #define MAX_HCALL_OPCODE H_WATCHDOG 591 592 /* The hcalls above are standardized in PAPR and implemented by pHyp 593 * as well. 594 * 595 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 596 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 597 * for "platform-specific" hcalls. 598 */ 599 #define KVMPPC_HCALL_BASE 0xf000 600 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 601 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 602 /* Client Architecture support */ 603 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 604 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 605 /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 606 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 607 608 /* Platform-specific hcalls used for nested HV KVM */ 609 #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) 610 #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) 611 #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) 612 #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) 613 614 #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST 615 616 /* 617 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 618 * Secure VM mode via an Ultravisor / Protected Execution Facility 619 */ 620 #define SVM_HCALL_BASE 0xEF00 621 #define SVM_H_TPM_COMM 0xEF10 622 #define SVM_HCALL_MAX SVM_H_TPM_COMM 623 624 /* 625 * Register state for entering a nested guest with H_ENTER_NESTED. 626 * New member must be added at the end. 627 */ 628 struct kvmppc_hv_guest_state { 629 uint64_t version; /* version of this structure layout, must be first */ 630 uint32_t lpid; 631 uint32_t vcpu_token; 632 /* These registers are hypervisor privileged (at least for writing) */ 633 uint64_t lpcr; 634 uint64_t pcr; 635 uint64_t amor; 636 uint64_t dpdes; 637 uint64_t hfscr; 638 int64_t tb_offset; 639 uint64_t dawr0; 640 uint64_t dawrx0; 641 uint64_t ciabr; 642 uint64_t hdec_expiry; 643 uint64_t purr; 644 uint64_t spurr; 645 uint64_t ic; 646 uint64_t vtb; 647 uint64_t hdar; 648 uint64_t hdsisr; 649 uint64_t heir; 650 uint64_t asdr; 651 /* These are OS privileged but need to be set late in guest entry */ 652 uint64_t srr0; 653 uint64_t srr1; 654 uint64_t sprg[4]; 655 uint64_t pidr; 656 uint64_t cfar; 657 uint64_t ppr; 658 /* Version 1 ends here */ 659 uint64_t dawr1; 660 uint64_t dawrx1; 661 /* Version 2 ends here */ 662 }; 663 664 /* Latest version of hv_guest_state structure */ 665 #define HV_GUEST_STATE_VERSION 2 666 667 /* Linux 64-bit powerpc pt_regs struct, used by nested HV */ 668 struct kvmppc_pt_regs { 669 uint64_t gpr[32]; 670 uint64_t nip; 671 uint64_t msr; 672 uint64_t orig_gpr3; /* Used for restarting system calls */ 673 uint64_t ctr; 674 uint64_t link; 675 uint64_t xer; 676 uint64_t ccr; 677 uint64_t softe; /* Soft enabled/disabled */ 678 uint64_t trap; /* Reason for being here */ 679 uint64_t dar; /* Fault registers */ 680 uint64_t dsisr; /* on 4xx/Book-E used for ESR */ 681 uint64_t result; /* Result of a system call */ 682 }; 683 684 typedef struct SpaprDeviceTreeUpdateHeader { 685 uint32_t version_id; 686 } SpaprDeviceTreeUpdateHeader; 687 688 #define hcall_dprintf(fmt, ...) \ 689 do { \ 690 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 691 } while (0) 692 693 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 694 target_ulong opcode, 695 target_ulong *args); 696 697 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 698 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 699 target_ulong *args); 700 701 void spapr_exit_nested(PowerPCCPU *cpu, int excp); 702 703 target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, 704 target_ulong shift); 705 target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, 706 target_ulong flags, target_ulong shift); 707 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 708 void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 709 710 /* Virtual Processor Area structure constants */ 711 #define VPA_MIN_SIZE 640 712 #define VPA_SIZE_OFFSET 0x4 713 #define VPA_SHARED_PROC_OFFSET 0x9 714 #define VPA_SHARED_PROC_VAL 0x2 715 #define VPA_DISPATCH_COUNTER 0x100 716 717 /* ibm,set-eeh-option */ 718 #define RTAS_EEH_DISABLE 0 719 #define RTAS_EEH_ENABLE 1 720 #define RTAS_EEH_THAW_IO 2 721 #define RTAS_EEH_THAW_DMA 3 722 723 /* ibm,get-config-addr-info2 */ 724 #define RTAS_GET_PE_ADDR 0 725 #define RTAS_GET_PE_MODE 1 726 #define RTAS_PE_MODE_NONE 0 727 #define RTAS_PE_MODE_NOT_SHARED 1 728 #define RTAS_PE_MODE_SHARED 2 729 730 /* ibm,read-slot-reset-state2 */ 731 #define RTAS_EEH_PE_STATE_NORMAL 0 732 #define RTAS_EEH_PE_STATE_RESET 1 733 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 734 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 735 #define RTAS_EEH_PE_STATE_UNAVAIL 5 736 #define RTAS_EEH_NOT_SUPPORT 0 737 #define RTAS_EEH_SUPPORT 1 738 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 739 #define RTAS_EEH_PE_RECOVER_INFO 0 740 741 /* ibm,set-slot-reset */ 742 #define RTAS_SLOT_RESET_DEACTIVATE 0 743 #define RTAS_SLOT_RESET_HOT 1 744 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 745 746 /* ibm,slot-error-detail */ 747 #define RTAS_SLOT_TEMP_ERR_LOG 1 748 #define RTAS_SLOT_PERM_ERR_LOG 2 749 750 /* RTAS return codes */ 751 #define RTAS_OUT_SUCCESS 0 752 #define RTAS_OUT_NO_ERRORS_FOUND 1 753 #define RTAS_OUT_HW_ERROR -1 754 #define RTAS_OUT_BUSY -2 755 #define RTAS_OUT_PARAM_ERROR -3 756 #define RTAS_OUT_NOT_SUPPORTED -3 757 #define RTAS_OUT_NO_SUCH_INDICATOR -3 758 #define RTAS_OUT_NOT_AUTHORIZED -9002 759 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 760 761 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 762 #define RTAS_DDW_PGSIZE_4K 0x01 763 #define RTAS_DDW_PGSIZE_64K 0x02 764 #define RTAS_DDW_PGSIZE_16M 0x04 765 #define RTAS_DDW_PGSIZE_32M 0x08 766 #define RTAS_DDW_PGSIZE_64M 0x10 767 #define RTAS_DDW_PGSIZE_128M 0x20 768 #define RTAS_DDW_PGSIZE_256M 0x40 769 #define RTAS_DDW_PGSIZE_16G 0x80 770 #define RTAS_DDW_PGSIZE_2M 0x100 771 772 /* RTAS tokens */ 773 #define RTAS_TOKEN_BASE 0x2000 774 775 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 776 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 777 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 778 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 779 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 780 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 781 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 782 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 783 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 784 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 785 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 786 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 787 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 788 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 789 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 790 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 791 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 792 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 793 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 794 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 795 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 796 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 797 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 798 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 799 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 800 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 801 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 802 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 803 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 804 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 805 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 806 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 807 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 808 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 809 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 810 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 811 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 812 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 813 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 814 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 815 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 816 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 817 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 818 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 819 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 820 821 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 822 823 /* RTAS ibm,get-system-parameter token values */ 824 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 825 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 826 #define RTAS_SYSPARM_UUID 48 827 828 /* RTAS indicator/sensor types 829 * 830 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 831 * 832 * NOTE: currently only DR-related sensors are implemented here 833 */ 834 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 835 #define RTAS_SENSOR_TYPE_DR 9002 836 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 837 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 838 839 /* Possible values for the platform-processor-diagnostics-run-mode parameter 840 * of the RTAS ibm,get-system-parameter call. 841 */ 842 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 843 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 844 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 845 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 846 847 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 848 { 849 return addr & ~0xF000000000000000ULL; 850 } 851 852 static inline uint32_t rtas_ld(target_ulong phys, int n) 853 { 854 return ldl_be_phys(&address_space_memory, 855 ppc64_phys_to_real(phys + 4 * n)); 856 } 857 858 static inline uint64_t rtas_ldq(target_ulong phys, int n) 859 { 860 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 861 } 862 863 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 864 { 865 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val); 866 } 867 868 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 869 uint32_t token, 870 uint32_t nargs, target_ulong args, 871 uint32_t nret, target_ulong rets); 872 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 873 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 874 uint32_t token, uint32_t nargs, target_ulong args, 875 uint32_t nret, target_ulong rets); 876 void spapr_dt_rtas_tokens(void *fdt, int rtas); 877 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 878 879 #define SPAPR_TCE_PAGE_SHIFT 12 880 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 881 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 882 883 #define SPAPR_VIO_BASE_LIOBN 0x00000000 884 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 885 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 886 (0x80000000 | ((phb_index) << 8) | (window_num)) 887 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 888 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 889 890 #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 891 #define RTAS_ERROR_LOG_MAX 2048 892 893 /* Offset from rtas-base where error log is placed */ 894 #define RTAS_ERROR_LOG_OFFSET 0x30 895 896 #define RTAS_EVENT_SCAN_RATE 1 897 898 /* This helper should be used to encode interrupt specifiers when the related 899 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 900 * VIO devices, RTAS event sources and PHBs). 901 */ 902 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 903 { 904 intspec[0] = cpu_to_be32(irq); 905 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 906 } 907 908 909 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 910 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 911 912 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 913 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 914 TYPE_SPAPR_IOMMU_MEMORY_REGION) 915 916 struct SpaprTceTable { 917 DeviceState parent; 918 uint32_t liobn; 919 uint32_t nb_table; 920 uint64_t bus_offset; 921 uint32_t page_shift; 922 uint64_t *table; 923 uint32_t mig_nb_table; 924 uint64_t *mig_table; 925 bool bypass; 926 bool need_vfio; 927 bool skipping_replay; 928 bool def_win; 929 int fd; 930 MemoryRegion root; 931 IOMMUMemoryRegion iommu; 932 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 933 QLIST_ENTRY(SpaprTceTable) list; 934 }; 935 936 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 937 938 struct SpaprEventLogEntry { 939 uint32_t summary; 940 uint32_t extended_length; 941 void *extended_log; 942 QTAILQ_ENTRY(SpaprEventLogEntry) next; 943 }; 944 945 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 946 void spapr_events_init(SpaprMachineState *sm); 947 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 948 void close_htab_fd(SpaprMachineState *spapr); 949 void spapr_setup_hpt(SpaprMachineState *spapr); 950 void spapr_free_hpt(SpaprMachineState *spapr); 951 void spapr_check_mmu_mode(bool guest_radix); 952 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 953 void spapr_tce_table_enable(SpaprTceTable *tcet, 954 uint32_t page_shift, uint64_t bus_offset, 955 uint32_t nb_table); 956 void spapr_tce_table_disable(SpaprTceTable *tcet); 957 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 958 959 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 960 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 961 uint32_t liobn, uint64_t window, uint32_t size); 962 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 963 SpaprTceTable *tcet); 964 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 965 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 966 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 967 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 968 uint32_t count); 969 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 970 uint32_t count); 971 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 972 uint32_t count, uint32_t index); 973 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 974 uint32_t count, uint32_t index); 975 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 976 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 977 void spapr_clear_pending_events(SpaprMachineState *spapr); 978 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 979 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 980 int spapr_max_server_number(SpaprMachineState *spapr); 981 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 982 uint64_t pte0, uint64_t pte1); 983 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 984 985 /* DRC callbacks. */ 986 void spapr_core_release(DeviceState *dev); 987 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 988 void *fdt, int *fdt_start_offset, Error **errp); 989 void spapr_lmb_release(DeviceState *dev); 990 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 991 void *fdt, int *fdt_start_offset, Error **errp); 992 void spapr_phb_release(DeviceState *dev); 993 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 994 void *fdt, int *fdt_start_offset, Error **errp); 995 996 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 997 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 998 999 #define TYPE_SPAPR_RNG "spapr-rng" 1000 1001 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 1002 1003 /* 1004 * This defines the maximum number of DIMM slots we can have for sPAPR 1005 * guest. This is not defined by sPAPR but we are defining it to 32 slots 1006 * based on default number of slots provided by PowerPC kernel. 1007 */ 1008 #define SPAPR_MAX_RAM_SLOTS 32 1009 1010 /* 1GB alignment for hotplug memory region */ 1011 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 1012 1013 /* 1014 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 1015 * property under ibm,dynamic-reconfiguration-memory node. 1016 */ 1017 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 1018 1019 /* 1020 * Defines for flag value in ibm,dynamic-memory property under 1021 * ibm,dynamic-reconfiguration-memory node. 1022 */ 1023 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 1024 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 1025 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 1026 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 1027 1028 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 1029 1030 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 1031 1032 int spapr_get_vcpu_id(PowerPCCPU *cpu); 1033 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 1034 PowerPCCPU *spapr_find_cpu(int vcpu_id); 1035 1036 int spapr_caps_pre_load(void *opaque); 1037 int spapr_caps_pre_save(void *opaque); 1038 1039 /* 1040 * Handling of optional capabilities 1041 */ 1042 extern const VMStateDescription vmstate_spapr_cap_htm; 1043 extern const VMStateDescription vmstate_spapr_cap_vsx; 1044 extern const VMStateDescription vmstate_spapr_cap_dfp; 1045 extern const VMStateDescription vmstate_spapr_cap_cfpc; 1046 extern const VMStateDescription vmstate_spapr_cap_sbbc; 1047 extern const VMStateDescription vmstate_spapr_cap_ibs; 1048 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 1049 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 1050 extern const VMStateDescription vmstate_spapr_cap_large_decr; 1051 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 1052 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 1053 extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 1054 extern const VMStateDescription vmstate_spapr_wdt; 1055 1056 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 1057 { 1058 return spapr->eff.caps[cap]; 1059 } 1060 1061 void spapr_caps_init(SpaprMachineState *spapr); 1062 void spapr_caps_apply(SpaprMachineState *spapr); 1063 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 1064 void spapr_caps_add_properties(SpaprMachineClass *smc); 1065 int spapr_caps_post_migration(SpaprMachineState *spapr); 1066 1067 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 1068 Error **errp); 1069 /* 1070 * XIVE definitions 1071 */ 1072 #define SPAPR_OV5_XIVE_LEGACY 0x0 1073 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 1074 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 1075 1076 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 1077 hwaddr spapr_get_rtas_addr(void); 1078 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 1079 1080 void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 1081 void spapr_vof_quiesce(MachineState *ms); 1082 bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 1083 void *val, int vallen); 1084 target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 1085 target_ulong opcode, target_ulong *args); 1086 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1087 CPUState *cs, 1088 target_ulong ovec_addr); 1089 void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 1090 1091 /* H_WATCHDOG */ 1092 void spapr_watchdog_init(SpaprMachineState *spapr); 1093 1094 #endif /* HW_SPAPR_H */ 1095