1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "qom/object.h" 12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13 #include "hw/ppc/xics.h" /* For ICSState */ 14 #include "hw/ppc/spapr_tpm_proxy.h" 15 #include "hw/ppc/spapr_nested.h" /* For SpaprMachineStateNested */ 16 17 struct SpaprVioBus; 18 struct SpaprPhbState; 19 struct SpaprNvram; 20 21 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 22 typedef struct SpaprEventSource SpaprEventSource; 23 typedef struct SpaprPendingHpt SpaprPendingHpt; 24 25 typedef struct Vof Vof; 26 27 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 28 #define SPAPR_ENTRY_POINT 0x100 29 30 #define SPAPR_TIMEBASE_FREQ 512000000ULL 31 32 #define TYPE_SPAPR_RTC "spapr-rtc" 33 34 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 35 36 struct SpaprRtcState { 37 /*< private >*/ 38 DeviceState parent_obj; 39 int64_t ns_offset; 40 }; 41 42 typedef struct SpaprDimmState SpaprDimmState; 43 44 #define TYPE_SPAPR_MACHINE "spapr-machine" 45 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 46 47 typedef enum { 48 SPAPR_RESIZE_HPT_DEFAULT = 0, 49 SPAPR_RESIZE_HPT_DISABLED, 50 SPAPR_RESIZE_HPT_ENABLED, 51 SPAPR_RESIZE_HPT_REQUIRED, 52 } SpaprResizeHpt; 53 54 /** 55 * Capabilities 56 */ 57 58 /* Hardware Transactional Memory */ 59 #define SPAPR_CAP_HTM 0x00 60 /* Vector Scalar Extensions */ 61 #define SPAPR_CAP_VSX 0x01 62 /* Decimal Floating Point */ 63 #define SPAPR_CAP_DFP 0x02 64 /* Cache Flush on Privilege Change */ 65 #define SPAPR_CAP_CFPC 0x03 66 /* Speculation Barrier Bounds Checking */ 67 #define SPAPR_CAP_SBBC 0x04 68 /* Indirect Branch Serialisation */ 69 #define SPAPR_CAP_IBS 0x05 70 /* HPT Maximum Page Size (encoded as a shift) */ 71 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 72 /* Nested KVM-HV */ 73 #define SPAPR_CAP_NESTED_KVM_HV 0x07 74 /* Large Decrementer */ 75 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 76 /* Count Cache Flush Assist HW Instruction */ 77 #define SPAPR_CAP_CCF_ASSIST 0x09 78 /* Implements PAPR FWNMI option */ 79 #define SPAPR_CAP_FWNMI 0x0A 80 /* Support H_RPT_INVALIDATE */ 81 #define SPAPR_CAP_RPT_INVALIDATE 0x0B 82 /* Support for AIL modes */ 83 #define SPAPR_CAP_AIL_MODE_3 0x0C 84 /* Nested PAPR */ 85 #define SPAPR_CAP_NESTED_PAPR 0x0D 86 /* Num Caps */ 87 #define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_PAPR + 1) 88 89 /* 90 * Capability Values 91 */ 92 /* Bool Caps */ 93 #define SPAPR_CAP_OFF 0x00 94 #define SPAPR_CAP_ON 0x01 95 96 /* Custom Caps */ 97 98 /* Generic */ 99 #define SPAPR_CAP_BROKEN 0x00 100 #define SPAPR_CAP_WORKAROUND 0x01 101 #define SPAPR_CAP_FIXED 0x02 102 /* SPAPR_CAP_IBS (cap-ibs) */ 103 #define SPAPR_CAP_FIXED_IBS 0x02 104 #define SPAPR_CAP_FIXED_CCD 0x03 105 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 106 107 #define FDT_MAX_SIZE 0x200000 108 109 /* Max number of NUMA nodes */ 110 #define NUMA_NODES_MAX_NUM (MAX_NODES) 111 112 /* 113 * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 114 * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 115 * kernel source. It represents the amount of associativity domains 116 * for non-CPU resources. 117 * 118 * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 119 * array for any non-CPU resource. 120 */ 121 #define FORM1_DIST_REF_POINTS 4 122 #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 123 124 /* 125 * FORM2 NUMA affinity has a single associativity domain, giving 126 * us a assoc size of 2. 127 */ 128 #define FORM2_DIST_REF_POINTS 1 129 #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 130 131 typedef struct SpaprCapabilities SpaprCapabilities; 132 struct SpaprCapabilities { 133 uint8_t caps[SPAPR_CAP_NUM]; 134 }; 135 136 /** 137 * SpaprMachineClass: 138 */ 139 struct SpaprMachineClass { 140 /*< private >*/ 141 MachineClass parent_class; 142 143 /*< public >*/ 144 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 145 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 146 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 147 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 148 bool pre_2_10_has_unused_icps; 149 bool legacy_irq_allocation; 150 uint32_t nr_xirqs; 151 bool broken_host_serial_model; /* present real host info to the guest */ 152 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 153 bool linux_pci_probe; 154 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 155 hwaddr rma_limit; /* clamp the RMA to this size */ 156 bool pre_5_1_assoc_refpoints; 157 bool pre_5_2_numa_associativity; 158 bool pre_6_2_numa_affinity; 159 160 bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 161 uint64_t *buid, hwaddr *pio, 162 hwaddr *mmio32, hwaddr *mmio64, 163 unsigned n_dma, uint32_t *liobns, Error **errp); 164 SpaprResizeHpt resize_hpt_default; 165 SpaprCapabilities default_caps; 166 SpaprIrq *irq; 167 }; 168 169 #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ 170 171 #define TYPE_SPAPR_WDT "spapr-wdt" 172 OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) 173 174 typedef struct SpaprWatchdog { 175 /*< private >*/ 176 DeviceState parent_obj; 177 /*< public >*/ 178 179 QEMUTimer timer; 180 uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ 181 uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ 182 } SpaprWatchdog; 183 184 /** 185 * SpaprMachineState: 186 */ 187 struct SpaprMachineState { 188 /*< private >*/ 189 MachineState parent_obj; 190 191 struct SpaprVioBus *vio_bus; 192 QLIST_HEAD(, SpaprPhbState) phbs; 193 struct SpaprNvram *nvram; 194 SpaprRtcState rtc; 195 196 SpaprResizeHpt resize_hpt; 197 void *htab; 198 uint32_t htab_shift; 199 uint64_t patb_entry; /* Process tbl registered in H_REGISTER_PROC_TBL */ 200 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 201 202 hwaddr rma_size; 203 uint32_t fdt_size; 204 uint32_t fdt_initial_size; 205 void *fdt_blob; 206 uint8_t fdt_rng_seed[32]; 207 long kernel_size; 208 bool kernel_le; 209 uint64_t kernel_addr; 210 uint32_t initrd_base; 211 long initrd_size; 212 Vof *vof; 213 uint64_t rtc_offset; /* Now used only during incoming migration */ 214 struct PPCTimebase tb; 215 bool want_stdout_path; 216 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 217 218 /* Nested HV support (TCG only) */ 219 SpaprMachineStateNested nested; 220 221 Notifier epow_notifier; 222 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 223 bool use_hotplug_event_source; 224 SpaprEventSource *event_sources; 225 226 /* ibm,client-architecture-support option negotiation */ 227 bool cas_pre_isa3_guest; 228 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 229 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 230 uint32_t max_compat_pvr; 231 232 /* Migration state */ 233 int htab_save_index; 234 bool htab_first_pass; 235 int htab_fd; 236 237 /* Pending DIMM unplug cache. It is populated when a LMB 238 * unplug starts. It can be regenerated if a migration 239 * occurs during the unplug process. */ 240 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 241 242 /* State related to FWNMI option */ 243 244 /* System Reset and Machine Check Notification Routine addresses 245 * registered by "ibm,nmi-register" RTAS call. 246 */ 247 target_ulong fwnmi_system_reset_addr; 248 target_ulong fwnmi_machine_check_addr; 249 250 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 251 * set to -1 if a FWNMI machine check is not in progress, else is set to 252 * the CPU that was delivered the machine check, and is set back to -1 253 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 254 * to synchronize other CPUs. 255 */ 256 int fwnmi_machine_check_interlock; 257 QemuCond fwnmi_machine_check_interlock_cond; 258 259 /* Set by -boot */ 260 char *boot_device; 261 262 /*< public >*/ 263 char *kvm_type; 264 char *host_model; 265 char *host_serial; 266 267 int32_t irq_map_nr; 268 unsigned long *irq_map; 269 SpaprIrq *irq; 270 qemu_irq *qirqs; 271 SpaprInterruptController *active_intc; 272 ICSState *ics; 273 SpaprXive *xive; 274 275 bool cmd_line_caps[SPAPR_CAP_NUM]; 276 SpaprCapabilities def, eff, mig; 277 278 SpaprTpmProxy *tpm_proxy; 279 280 uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 281 uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 282 283 Error *fwnmi_migration_blocker; 284 285 SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; 286 }; 287 288 #define H_SUCCESS 0 289 #define H_BUSY 1 /* Hardware busy -- retry later */ 290 #define H_CLOSED 2 /* Resource closed */ 291 #define H_NOT_AVAILABLE 3 292 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 293 #define H_PARTIAL 5 294 #define H_IN_PROGRESS 14 /* Kind of like busy */ 295 #define H_PAGE_REGISTERED 15 296 #define H_PARTIAL_STORE 16 297 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 298 #define H_CONTINUE 18 /* Returned from H_Join on success */ 299 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 300 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 301 is a good time to retry */ 302 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 303 is a good time to retry */ 304 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 305 is a good time to retry */ 306 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 307 is a good time to retry */ 308 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 309 is a good time to retry */ 310 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 311 is a good time to retry */ 312 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 313 #define H_HARDWARE -1 /* Hardware error */ 314 #define H_FUNCTION -2 /* Function not supported */ 315 #define H_PRIVILEGE -3 /* Caller not privileged */ 316 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 317 #define H_BAD_MODE -5 /* Illegal msr value */ 318 #define H_PTEG_FULL -6 /* PTEG is full */ 319 #define H_NOT_FOUND -7 /* PTE was not found" */ 320 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 321 #define H_NO_MEM -9 322 #define H_AUTHORITY -10 323 #define H_PERMISSION -11 324 #define H_DROPPED -12 325 #define H_SOURCE_PARM -13 326 #define H_DEST_PARM -14 327 #define H_REMOTE_PARM -15 328 #define H_RESOURCE -16 329 #define H_ADAPTER_PARM -17 330 #define H_RH_PARM -18 331 #define H_RCQ_PARM -19 332 #define H_SCQ_PARM -20 333 #define H_EQ_PARM -21 334 #define H_RT_PARM -22 335 #define H_ST_PARM -23 336 #define H_SIGT_PARM -24 337 #define H_TOKEN_PARM -25 338 #define H_MLENGTH_PARM -27 339 #define H_MEM_PARM -28 340 #define H_MEM_ACCESS_PARM -29 341 #define H_ATTR_PARM -30 342 #define H_PORT_PARM -31 343 #define H_MCG_PARM -32 344 #define H_VL_PARM -33 345 #define H_TSIZE_PARM -34 346 #define H_TRACE_PARM -35 347 348 #define H_MASK_PARM -37 349 #define H_MCG_FULL -38 350 #define H_ALIAS_EXIST -39 351 #define H_P_COUNTER -40 352 #define H_TABLE_FULL -41 353 #define H_ALT_TABLE -42 354 #define H_MR_CONDITION -43 355 #define H_NOT_ENOUGH_RESOURCES -44 356 #define H_R_STATE -45 357 #define H_RESCINDEND -46 358 #define H_P2 -55 359 #define H_P3 -56 360 #define H_P4 -57 361 #define H_P5 -58 362 #define H_P6 -59 363 #define H_P7 -60 364 #define H_P8 -61 365 #define H_P9 -62 366 #define H_NOOP -63 367 #define H_UNSUPPORTED -67 368 #define H_OVERLAP -68 369 #define H_STATE -75 370 #define H_IN_USE -77 371 #define H_INVALID_ELEMENT_VALUE -81 372 #define H_UNSUPPORTED_FLAG -256 373 #define H_MULTI_THREADS_ACTIVE -9005 374 375 376 /* Long Busy is a condition that can be returned by the firmware 377 * when a call cannot be completed now, but the identical call 378 * should be retried later. This prevents calls blocking in the 379 * firmware for long periods of time. Annoyingly the firmware can return 380 * a range of return codes, hinting at how long we should wait before 381 * retrying. If you don't care for the hint, the macro below is a good 382 * way to check for the long_busy return codes 383 */ 384 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 385 && (x <= H_LONG_BUSY_END_RANGE)) 386 387 /* Flags */ 388 #define H_LARGE_PAGE (1ULL<<(63-16)) 389 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 390 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 391 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 392 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 393 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 394 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 395 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 396 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 397 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 398 #define H_ANDCOND (1ULL<<(63-33)) 399 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 400 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 401 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 402 #define H_COPY_PAGE (1ULL<<(63-49)) 403 #define H_N (1ULL<<(63-61)) 404 #define H_PP1 (1ULL<<(63-62)) 405 #define H_PP2 (1ULL<<(63-63)) 406 407 /* Values for 2nd argument to H_SET_MODE */ 408 #define H_SET_MODE_RESOURCE_SET_CIABR 1 409 #define H_SET_MODE_RESOURCE_SET_DAWR0 2 410 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 411 #define H_SET_MODE_RESOURCE_LE 4 412 413 /* Flags for H_SET_MODE_RESOURCE_LE */ 414 #define H_SET_MODE_ENDIAN_BIG 0 415 #define H_SET_MODE_ENDIAN_LITTLE 1 416 417 /* VASI States */ 418 #define H_VASI_INVALID 0 419 #define H_VASI_ENABLED 1 420 #define H_VASI_ABORTED 2 421 #define H_VASI_SUSPENDING 3 422 #define H_VASI_SUSPENDED 4 423 #define H_VASI_RESUMED 5 424 #define H_VASI_COMPLETED 6 425 426 /* DABRX flags */ 427 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 428 #define H_DABRX_KERNEL (1ULL<<(63-62)) 429 #define H_DABRX_USER (1ULL<<(63-63)) 430 431 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 432 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 433 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 434 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 435 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 436 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 437 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 438 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 439 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 440 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 441 442 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 443 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 444 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 445 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 446 #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 447 #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 448 449 /* Each control block has to be on a 4K boundary */ 450 #define H_CB_ALIGNMENT 4096 451 452 /* pSeries hypervisor opcodes */ 453 #define H_REMOVE 0x04 454 #define H_ENTER 0x08 455 #define H_READ 0x0c 456 #define H_CLEAR_MOD 0x10 457 #define H_CLEAR_REF 0x14 458 #define H_PROTECT 0x18 459 #define H_GET_TCE 0x1c 460 #define H_PUT_TCE 0x20 461 #define H_SET_SPRG0 0x24 462 #define H_SET_DABR 0x28 463 #define H_PAGE_INIT 0x2c 464 #define H_SET_ASR 0x30 465 #define H_ASR_ON 0x34 466 #define H_ASR_OFF 0x38 467 #define H_LOGICAL_CI_LOAD 0x3c 468 #define H_LOGICAL_CI_STORE 0x40 469 #define H_LOGICAL_CACHE_LOAD 0x44 470 #define H_LOGICAL_CACHE_STORE 0x48 471 #define H_LOGICAL_ICBI 0x4c 472 #define H_LOGICAL_DCBF 0x50 473 #define H_GET_TERM_CHAR 0x54 474 #define H_PUT_TERM_CHAR 0x58 475 #define H_REAL_TO_LOGICAL 0x5c 476 #define H_HYPERVISOR_DATA 0x60 477 #define H_EOI 0x64 478 #define H_CPPR 0x68 479 #define H_IPI 0x6c 480 #define H_IPOLL 0x70 481 #define H_XIRR 0x74 482 #define H_PERFMON 0x7c 483 #define H_MIGRATE_DMA 0x78 484 #define H_REGISTER_VPA 0xDC 485 #define H_CEDE 0xE0 486 #define H_CONFER 0xE4 487 #define H_PROD 0xE8 488 #define H_GET_PPP 0xEC 489 #define H_SET_PPP 0xF0 490 #define H_PURR 0xF4 491 #define H_PIC 0xF8 492 #define H_REG_CRQ 0xFC 493 #define H_FREE_CRQ 0x100 494 #define H_VIO_SIGNAL 0x104 495 #define H_SEND_CRQ 0x108 496 #define H_COPY_RDMA 0x110 497 #define H_REGISTER_LOGICAL_LAN 0x114 498 #define H_FREE_LOGICAL_LAN 0x118 499 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 500 #define H_SEND_LOGICAL_LAN 0x120 501 #define H_BULK_REMOVE 0x124 502 #define H_MULTICAST_CTRL 0x130 503 #define H_SET_XDABR 0x134 504 #define H_STUFF_TCE 0x138 505 #define H_PUT_TCE_INDIRECT 0x13C 506 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 507 #define H_VTERM_PARTNER_INFO 0x150 508 #define H_REGISTER_VTERM 0x154 509 #define H_FREE_VTERM 0x158 510 #define H_RESET_EVENTS 0x15C 511 #define H_ALLOC_RESOURCE 0x160 512 #define H_FREE_RESOURCE 0x164 513 #define H_MODIFY_QP 0x168 514 #define H_QUERY_QP 0x16C 515 #define H_REREGISTER_PMR 0x170 516 #define H_REGISTER_SMR 0x174 517 #define H_QUERY_MR 0x178 518 #define H_QUERY_MW 0x17C 519 #define H_QUERY_HCA 0x180 520 #define H_QUERY_PORT 0x184 521 #define H_MODIFY_PORT 0x188 522 #define H_DEFINE_AQP1 0x18C 523 #define H_GET_TRACE_BUFFER 0x190 524 #define H_DEFINE_AQP0 0x194 525 #define H_RESIZE_MR 0x198 526 #define H_ATTACH_MCQP 0x19C 527 #define H_DETACH_MCQP 0x1A0 528 #define H_CREATE_RPT 0x1A4 529 #define H_REMOVE_RPT 0x1A8 530 #define H_REGISTER_RPAGES 0x1AC 531 #define H_DISABLE_AND_GETC 0x1B0 532 #define H_ERROR_DATA 0x1B4 533 #define H_GET_HCA_INFO 0x1B8 534 #define H_GET_PERF_COUNT 0x1BC 535 #define H_MANAGE_TRACE 0x1C0 536 #define H_GET_CPU_CHARACTERISTICS 0x1C8 537 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 538 #define H_QUERY_INT_STATE 0x1E4 539 #define H_POLL_PENDING 0x1D8 540 #define H_ILLAN_ATTRIBUTES 0x244 541 #define H_MODIFY_HEA_QP 0x250 542 #define H_QUERY_HEA_QP 0x254 543 #define H_QUERY_HEA 0x258 544 #define H_QUERY_HEA_PORT 0x25C 545 #define H_MODIFY_HEA_PORT 0x260 546 #define H_REG_BCMC 0x264 547 #define H_DEREG_BCMC 0x268 548 #define H_REGISTER_HEA_RPAGES 0x26C 549 #define H_DISABLE_AND_GET_HEA 0x270 550 #define H_GET_HEA_INFO 0x274 551 #define H_ALLOC_HEA_RESOURCE 0x278 552 #define H_ADD_CONN 0x284 553 #define H_DEL_CONN 0x288 554 #define H_JOIN 0x298 555 #define H_VASI_STATE 0x2A4 556 #define H_ENABLE_CRQ 0x2B0 557 #define H_GET_EM_PARMS 0x2B8 558 #define H_SET_MPP 0x2D0 559 #define H_GET_MPP 0x2D4 560 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 561 #define H_XIRR_X 0x2FC 562 #define H_RANDOM 0x300 563 #define H_SET_MODE 0x31C 564 #define H_RESIZE_HPT_PREPARE 0x36C 565 #define H_RESIZE_HPT_COMMIT 0x370 566 #define H_CLEAN_SLB 0x374 567 #define H_INVALIDATE_PID 0x378 568 #define H_REGISTER_PROC_TBL 0x37C 569 #define H_SIGNAL_SYS_RESET 0x380 570 571 #define H_INT_GET_SOURCE_INFO 0x3A8 572 #define H_INT_SET_SOURCE_CONFIG 0x3AC 573 #define H_INT_GET_SOURCE_CONFIG 0x3B0 574 #define H_INT_GET_QUEUE_INFO 0x3B4 575 #define H_INT_SET_QUEUE_CONFIG 0x3B8 576 #define H_INT_GET_QUEUE_CONFIG 0x3BC 577 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 578 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 579 #define H_INT_ESB 0x3C8 580 #define H_INT_SYNC 0x3CC 581 #define H_INT_RESET 0x3D0 582 #define H_SCM_READ_METADATA 0x3E4 583 #define H_SCM_WRITE_METADATA 0x3E8 584 #define H_SCM_BIND_MEM 0x3EC 585 #define H_SCM_UNBIND_MEM 0x3F0 586 #define H_SCM_UNBIND_ALL 0x3FC 587 #define H_SCM_HEALTH 0x400 588 #define H_RPT_INVALIDATE 0x448 589 #define H_SCM_FLUSH 0x44C 590 #define H_WATCHDOG 0x45C 591 #define H_GUEST_GET_CAPABILITIES 0x460 592 #define H_GUEST_SET_CAPABILITIES 0x464 593 #define H_GUEST_CREATE 0x470 594 #define H_GUEST_CREATE_VCPU 0x474 595 #define H_GUEST_GET_STATE 0x478 596 #define H_GUEST_SET_STATE 0x47C 597 #define H_GUEST_RUN_VCPU 0x480 598 #define H_GUEST_DELETE 0x488 599 600 #define MAX_HCALL_OPCODE H_GUEST_DELETE 601 602 /* The hcalls above are standardized in PAPR and implemented by pHyp 603 * as well. 604 * 605 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 606 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 607 * for "platform-specific" hcalls. 608 */ 609 #define KVMPPC_HCALL_BASE 0xf000 610 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 611 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 612 /* Client Architecture support */ 613 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 614 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 615 /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 616 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 617 618 /* Platform-specific hcalls used for nested HV KVM */ 619 #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) 620 #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) 621 #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) 622 #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) 623 624 #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST 625 626 /* 627 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 628 * Secure VM mode via an Ultravisor / Protected Execution Facility 629 */ 630 #define SVM_HCALL_BASE 0xEF00 631 #define SVM_H_TPM_COMM 0xEF10 632 #define SVM_HCALL_MAX SVM_H_TPM_COMM 633 634 typedef struct SpaprDeviceTreeUpdateHeader { 635 uint32_t version_id; 636 } SpaprDeviceTreeUpdateHeader; 637 638 #define hcall_dprintf(fmt, ...) \ 639 do { \ 640 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 641 } while (0) 642 643 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 644 target_ulong opcode, 645 target_ulong *args); 646 647 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 648 void spapr_unregister_hypercall(target_ulong opcode); 649 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 650 target_ulong *args); 651 652 target_ulong vhyp_mmu_resize_hpt_prepare(PowerPCCPU *cpu, 653 SpaprMachineState *spapr, 654 target_ulong shift); 655 target_ulong vhyp_mmu_resize_hpt_commit(PowerPCCPU *cpu, 656 SpaprMachineState *spapr, 657 target_ulong flags, 658 target_ulong shift); 659 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 660 void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 661 662 /* Virtual Processor Area structure constants */ 663 #define VPA_MIN_SIZE 640 664 #define VPA_SIZE_OFFSET 0x4 665 #define VPA_SHARED_PROC_OFFSET 0x9 666 #define VPA_SHARED_PROC_VAL 0x2 667 #define VPA_DISPATCH_COUNTER 0x100 668 669 /* ibm,set-eeh-option */ 670 #define RTAS_EEH_DISABLE 0 671 #define RTAS_EEH_ENABLE 1 672 #define RTAS_EEH_THAW_IO 2 673 #define RTAS_EEH_THAW_DMA 3 674 675 /* ibm,get-config-addr-info2 */ 676 #define RTAS_GET_PE_ADDR 0 677 #define RTAS_GET_PE_MODE 1 678 #define RTAS_PE_MODE_NONE 0 679 #define RTAS_PE_MODE_NOT_SHARED 1 680 #define RTAS_PE_MODE_SHARED 2 681 682 /* ibm,read-slot-reset-state2 */ 683 #define RTAS_EEH_PE_STATE_NORMAL 0 684 #define RTAS_EEH_PE_STATE_RESET 1 685 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 686 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 687 #define RTAS_EEH_PE_STATE_UNAVAIL 5 688 #define RTAS_EEH_NOT_SUPPORT 0 689 #define RTAS_EEH_SUPPORT 1 690 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 691 #define RTAS_EEH_PE_RECOVER_INFO 0 692 693 /* ibm,set-slot-reset */ 694 #define RTAS_SLOT_RESET_DEACTIVATE 0 695 #define RTAS_SLOT_RESET_HOT 1 696 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 697 698 /* ibm,slot-error-detail */ 699 #define RTAS_SLOT_TEMP_ERR_LOG 1 700 #define RTAS_SLOT_PERM_ERR_LOG 2 701 702 /* RTAS return codes */ 703 #define RTAS_OUT_SUCCESS 0 704 #define RTAS_OUT_NO_ERRORS_FOUND 1 705 #define RTAS_OUT_HW_ERROR -1 706 #define RTAS_OUT_BUSY -2 707 #define RTAS_OUT_PARAM_ERROR -3 708 #define RTAS_OUT_NOT_SUPPORTED -3 709 #define RTAS_OUT_NO_SUCH_INDICATOR -3 710 #define RTAS_OUT_NOT_AUTHORIZED -9002 711 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 712 713 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 714 #define RTAS_DDW_PGSIZE_4K 0x01 715 #define RTAS_DDW_PGSIZE_64K 0x02 716 #define RTAS_DDW_PGSIZE_16M 0x04 717 #define RTAS_DDW_PGSIZE_32M 0x08 718 #define RTAS_DDW_PGSIZE_64M 0x10 719 #define RTAS_DDW_PGSIZE_128M 0x20 720 #define RTAS_DDW_PGSIZE_256M 0x40 721 #define RTAS_DDW_PGSIZE_16G 0x80 722 #define RTAS_DDW_PGSIZE_2M 0x100 723 724 /* RTAS tokens */ 725 #define RTAS_TOKEN_BASE 0x2000 726 727 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 728 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 729 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 730 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 731 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 732 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 733 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 734 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 735 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 736 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 737 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 738 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 739 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 740 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 741 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 742 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 743 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 744 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 745 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 746 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 747 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 748 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 749 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 750 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 751 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 752 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 753 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 754 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 755 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 756 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 757 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 758 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 759 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 760 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 761 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 762 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 763 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 764 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 765 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 766 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 767 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 768 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 769 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 770 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 771 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 772 773 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 774 775 /* RTAS ibm,get-system-parameter token values */ 776 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 777 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 778 #define RTAS_SYSPARM_UUID 48 779 780 /* RTAS indicator/sensor types 781 * 782 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 783 * 784 * NOTE: currently only DR-related sensors are implemented here 785 */ 786 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 787 #define RTAS_SENSOR_TYPE_DR 9002 788 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 789 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 790 791 /* Possible values for the platform-processor-diagnostics-run-mode parameter 792 * of the RTAS ibm,get-system-parameter call. 793 */ 794 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 795 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 796 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 797 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 798 799 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 800 { 801 return addr & ~0xF000000000000000ULL; 802 } 803 804 static inline uint32_t rtas_ld(target_ulong phys, int n) 805 { 806 return ldl_be_phys(&address_space_memory, 807 ppc64_phys_to_real(phys + 4 * n)); 808 } 809 810 static inline uint64_t rtas_ldq(target_ulong phys, int n) 811 { 812 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 813 } 814 815 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 816 { 817 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val); 818 } 819 820 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 821 uint32_t token, 822 uint32_t nargs, target_ulong args, 823 uint32_t nret, target_ulong rets); 824 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 825 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 826 uint32_t token, uint32_t nargs, target_ulong args, 827 uint32_t nret, target_ulong rets); 828 void spapr_dt_rtas_tokens(void *fdt, int rtas); 829 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 830 831 #define SPAPR_TCE_PAGE_SHIFT 12 832 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 833 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 834 835 #define SPAPR_VIO_BASE_LIOBN 0x00000000 836 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 837 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 838 (0x80000000 | ((phb_index) << 8) | (window_num)) 839 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 840 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 841 842 #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 843 #define RTAS_ERROR_LOG_MAX 2048 844 845 /* Offset from rtas-base where error log is placed */ 846 #define RTAS_ERROR_LOG_OFFSET 0x30 847 848 #define RTAS_EVENT_SCAN_RATE 1 849 850 /* This helper should be used to encode interrupt specifiers when the related 851 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 852 * VIO devices, RTAS event sources and PHBs). 853 */ 854 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 855 { 856 intspec[0] = cpu_to_be32(irq); 857 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 858 } 859 860 861 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 862 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 863 864 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 865 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 866 TYPE_SPAPR_IOMMU_MEMORY_REGION) 867 868 struct SpaprTceTable { 869 DeviceState parent; 870 uint32_t liobn; 871 uint32_t nb_table; 872 uint64_t bus_offset; 873 uint32_t page_shift; 874 uint64_t *table; 875 uint32_t mig_nb_table; 876 uint64_t *mig_table; 877 bool bypass; 878 bool need_vfio; 879 bool skipping_replay; 880 bool def_win; 881 int fd; 882 MemoryRegion root; 883 IOMMUMemoryRegion iommu; 884 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 885 QLIST_ENTRY(SpaprTceTable) list; 886 }; 887 888 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 889 890 struct SpaprEventLogEntry { 891 uint32_t summary; 892 uint32_t extended_length; 893 void *extended_log; 894 QTAILQ_ENTRY(SpaprEventLogEntry) next; 895 }; 896 897 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 898 void spapr_events_init(SpaprMachineState *sm); 899 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 900 void close_htab_fd(SpaprMachineState *spapr); 901 void spapr_setup_hpt(SpaprMachineState *spapr); 902 void spapr_free_hpt(SpaprMachineState *spapr); 903 void spapr_check_mmu_mode(bool guest_radix); 904 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 905 void spapr_tce_table_enable(SpaprTceTable *tcet, 906 uint32_t page_shift, uint64_t bus_offset, 907 uint32_t nb_table); 908 void spapr_tce_table_disable(SpaprTceTable *tcet); 909 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 910 911 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 912 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 913 uint32_t liobn, uint64_t window, uint32_t size); 914 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 915 SpaprTceTable *tcet); 916 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 917 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 918 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 919 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 920 uint32_t count); 921 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 922 uint32_t count); 923 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 924 uint32_t count, uint32_t index); 925 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 926 uint32_t count, uint32_t index); 927 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 928 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 929 void spapr_clear_pending_events(SpaprMachineState *spapr); 930 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 931 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 932 int spapr_max_server_number(SpaprMachineState *spapr); 933 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 934 uint64_t pte0, uint64_t pte1); 935 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 936 937 /* DRC callbacks. */ 938 void spapr_core_release(DeviceState *dev); 939 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 940 void *fdt, int *fdt_start_offset, Error **errp); 941 void spapr_lmb_release(DeviceState *dev); 942 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 943 void *fdt, int *fdt_start_offset, Error **errp); 944 void spapr_phb_release(DeviceState *dev); 945 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 946 void *fdt, int *fdt_start_offset, Error **errp); 947 948 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 949 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 950 951 #define TYPE_SPAPR_RNG "spapr-rng" 952 953 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 954 955 /* 956 * This defines the maximum number of DIMM slots we can have for sPAPR 957 * guest. This is not defined by sPAPR but we are defining it to 32 slots 958 * based on default number of slots provided by PowerPC kernel. 959 */ 960 #define SPAPR_MAX_RAM_SLOTS 32 961 962 /* 1GB alignment for hotplug memory region */ 963 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 964 965 /* 966 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 967 * property under ibm,dynamic-reconfiguration-memory node. 968 */ 969 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 970 971 /* 972 * Defines for flag value in ibm,dynamic-memory property under 973 * ibm,dynamic-reconfiguration-memory node. 974 */ 975 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 976 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 977 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 978 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 979 980 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 981 982 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 983 984 int spapr_get_vcpu_id(PowerPCCPU *cpu); 985 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 986 PowerPCCPU *spapr_find_cpu(int vcpu_id); 987 988 int spapr_caps_pre_load(void *opaque); 989 int spapr_caps_pre_save(void *opaque); 990 991 /* 992 * Handling of optional capabilities 993 */ 994 extern const VMStateDescription vmstate_spapr_cap_htm; 995 extern const VMStateDescription vmstate_spapr_cap_vsx; 996 extern const VMStateDescription vmstate_spapr_cap_dfp; 997 extern const VMStateDescription vmstate_spapr_cap_cfpc; 998 extern const VMStateDescription vmstate_spapr_cap_sbbc; 999 extern const VMStateDescription vmstate_spapr_cap_ibs; 1000 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 1001 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 1002 extern const VMStateDescription vmstate_spapr_cap_nested_papr; 1003 extern const VMStateDescription vmstate_spapr_cap_large_decr; 1004 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 1005 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 1006 extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 1007 extern const VMStateDescription vmstate_spapr_wdt; 1008 1009 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 1010 { 1011 return spapr->eff.caps[cap]; 1012 } 1013 1014 void spapr_caps_init(SpaprMachineState *spapr); 1015 void spapr_caps_apply(SpaprMachineState *spapr); 1016 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 1017 void spapr_caps_add_properties(SpaprMachineClass *smc); 1018 int spapr_caps_post_migration(SpaprMachineState *spapr); 1019 1020 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 1021 Error **errp); 1022 /* 1023 * XIVE definitions 1024 */ 1025 #define SPAPR_OV5_XIVE_LEGACY 0x0 1026 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 1027 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 1028 1029 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 1030 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask); 1031 hwaddr spapr_get_rtas_addr(void); 1032 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 1033 1034 void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 1035 void spapr_vof_quiesce(MachineState *ms); 1036 bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 1037 void *val, int vallen); 1038 target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 1039 target_ulong opcode, target_ulong *args); 1040 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1041 CPUState *cs, 1042 target_ulong ovec_addr); 1043 void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 1044 1045 /* H_WATCHDOG */ 1046 void spapr_watchdog_init(SpaprMachineState *spapr); 1047 void spapr_register_nested_hv(void); 1048 void spapr_unregister_nested_hv(void); 1049 void spapr_nested_reset(SpaprMachineState *spapr); 1050 void spapr_register_nested_papr(void); 1051 void spapr_unregister_nested_papr(void); 1052 1053 #endif /* HW_SPAPR_H */ 1054