xref: /openbmc/qemu/include/hw/ppc/spapr.h (revision 7562f907)
1 #ifndef HW_SPAPR_H
2 #define HW_SPAPR_H
3 
4 #include "sysemu/dma.h"
5 #include "hw/boards.h"
6 #include "hw/ppc/xics.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
10 
11 struct VIOsPAPRBus;
12 struct sPAPRPHBState;
13 struct sPAPRNVRAM;
14 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState;
15 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
16 typedef struct sPAPREventSource sPAPREventSource;
17 
18 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
19 #define SPAPR_ENTRY_POINT       0x100
20 
21 #define SPAPR_TIMEBASE_FREQ     512000000ULL
22 
23 typedef struct sPAPRMachineClass sPAPRMachineClass;
24 typedef struct sPAPRMachineState sPAPRMachineState;
25 
26 #define TYPE_SPAPR_MACHINE      "spapr-machine"
27 #define SPAPR_MACHINE(obj) \
28     OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
29 #define SPAPR_MACHINE_GET_CLASS(obj) \
30     OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
31 #define SPAPR_MACHINE_CLASS(klass) \
32     OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
33 
34 /**
35  * sPAPRMachineClass:
36  */
37 struct sPAPRMachineClass {
38     /*< private >*/
39     MachineClass parent_class;
40 
41     /*< public >*/
42     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
43     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
44     const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */
45     void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
46                           uint64_t *buid, hwaddr *pio,
47                           hwaddr *mmio32, hwaddr *mmio64,
48                           unsigned n_dma, uint32_t *liobns, Error **errp);
49 };
50 
51 /**
52  * sPAPRMachineState:
53  */
54 struct sPAPRMachineState {
55     /*< private >*/
56     MachineState parent_obj;
57 
58     struct VIOsPAPRBus *vio_bus;
59     QLIST_HEAD(, sPAPRPHBState) phbs;
60     struct sPAPRNVRAM *nvram;
61     XICSState *xics;
62     DeviceState *rtc;
63 
64     void *htab;
65     uint32_t htab_shift;
66     hwaddr rma_size;
67     int vrma_adjust;
68     ssize_t rtas_size;
69     void *rtas_blob;
70     long kernel_size;
71     bool kernel_le;
72     uint32_t initrd_base;
73     long initrd_size;
74     uint64_t rtc_offset; /* Now used only during incoming migration */
75     struct PPCTimebase tb;
76     bool has_graphics;
77     sPAPROptionVector *ov5;         /* QEMU-supported option vectors */
78     sPAPROptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
79     bool cas_reboot;
80 
81     Notifier epow_notifier;
82     QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
83     bool use_hotplug_event_source;
84     sPAPREventSource *event_sources;
85 
86     /* Migration state */
87     int htab_save_index;
88     bool htab_first_pass;
89     int htab_fd;
90 
91     /* RTAS state */
92     QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list;
93 
94     /*< public >*/
95     char *kvm_type;
96     MemoryHotplugState hotplug_memory;
97 };
98 
99 #define H_SUCCESS         0
100 #define H_BUSY            1        /* Hardware busy -- retry later */
101 #define H_CLOSED          2        /* Resource closed */
102 #define H_NOT_AVAILABLE   3
103 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
104 #define H_PARTIAL         5
105 #define H_IN_PROGRESS     14       /* Kind of like busy */
106 #define H_PAGE_REGISTERED 15
107 #define H_PARTIAL_STORE   16
108 #define H_PENDING         17       /* returned from H_POLL_PENDING */
109 #define H_CONTINUE        18       /* Returned from H_Join on success */
110 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
111 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
112                                                  is a good time to retry */
113 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
114                                                  is a good time to retry */
115 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
116                                                  is a good time to retry */
117 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
118                                                  is a good time to retry */
119 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
120                                                  is a good time to retry */
121 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
122                                                  is a good time to retry */
123 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
124 #define H_HARDWARE        -1       /* Hardware error */
125 #define H_FUNCTION        -2       /* Function not supported */
126 #define H_PRIVILEGE       -3       /* Caller not privileged */
127 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
128 #define H_BAD_MODE        -5       /* Illegal msr value */
129 #define H_PTEG_FULL       -6       /* PTEG is full */
130 #define H_NOT_FOUND       -7       /* PTE was not found" */
131 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
132 #define H_NO_MEM          -9
133 #define H_AUTHORITY       -10
134 #define H_PERMISSION      -11
135 #define H_DROPPED         -12
136 #define H_SOURCE_PARM     -13
137 #define H_DEST_PARM       -14
138 #define H_REMOTE_PARM     -15
139 #define H_RESOURCE        -16
140 #define H_ADAPTER_PARM    -17
141 #define H_RH_PARM         -18
142 #define H_RCQ_PARM        -19
143 #define H_SCQ_PARM        -20
144 #define H_EQ_PARM         -21
145 #define H_RT_PARM         -22
146 #define H_ST_PARM         -23
147 #define H_SIGT_PARM       -24
148 #define H_TOKEN_PARM      -25
149 #define H_MLENGTH_PARM    -27
150 #define H_MEM_PARM        -28
151 #define H_MEM_ACCESS_PARM -29
152 #define H_ATTR_PARM       -30
153 #define H_PORT_PARM       -31
154 #define H_MCG_PARM        -32
155 #define H_VL_PARM         -33
156 #define H_TSIZE_PARM      -34
157 #define H_TRACE_PARM      -35
158 
159 #define H_MASK_PARM       -37
160 #define H_MCG_FULL        -38
161 #define H_ALIAS_EXIST     -39
162 #define H_P_COUNTER       -40
163 #define H_TABLE_FULL      -41
164 #define H_ALT_TABLE       -42
165 #define H_MR_CONDITION    -43
166 #define H_NOT_ENOUGH_RESOURCES -44
167 #define H_R_STATE         -45
168 #define H_RESCINDEND      -46
169 #define H_P2              -55
170 #define H_P3              -56
171 #define H_P4              -57
172 #define H_P5              -58
173 #define H_P6              -59
174 #define H_P7              -60
175 #define H_P8              -61
176 #define H_P9              -62
177 #define H_UNSUPPORTED_FLAG -256
178 #define H_MULTI_THREADS_ACTIVE -9005
179 
180 
181 /* Long Busy is a condition that can be returned by the firmware
182  * when a call cannot be completed now, but the identical call
183  * should be retried later.  This prevents calls blocking in the
184  * firmware for long periods of time.  Annoyingly the firmware can return
185  * a range of return codes, hinting at how long we should wait before
186  * retrying.  If you don't care for the hint, the macro below is a good
187  * way to check for the long_busy return codes
188  */
189 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
190                             && (x <= H_LONG_BUSY_END_RANGE))
191 
192 /* Flags */
193 #define H_LARGE_PAGE      (1ULL<<(63-16))
194 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
195 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
196 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
197 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
198 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
199 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
200 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
201 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
202 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
203 #define H_ANDCOND         (1ULL<<(63-33))
204 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
205 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
206 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
207 #define H_COPY_PAGE       (1ULL<<(63-49))
208 #define H_N               (1ULL<<(63-61))
209 #define H_PP1             (1ULL<<(63-62))
210 #define H_PP2             (1ULL<<(63-63))
211 
212 /* Values for 2nd argument to H_SET_MODE */
213 #define H_SET_MODE_RESOURCE_SET_CIABR           1
214 #define H_SET_MODE_RESOURCE_SET_DAWR            2
215 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
216 #define H_SET_MODE_RESOURCE_LE                  4
217 
218 /* Flags for H_SET_MODE_RESOURCE_LE */
219 #define H_SET_MODE_ENDIAN_BIG    0
220 #define H_SET_MODE_ENDIAN_LITTLE 1
221 
222 /* VASI States */
223 #define H_VASI_INVALID    0
224 #define H_VASI_ENABLED    1
225 #define H_VASI_ABORTED    2
226 #define H_VASI_SUSPENDING 3
227 #define H_VASI_SUSPENDED  4
228 #define H_VASI_RESUMED    5
229 #define H_VASI_COMPLETED  6
230 
231 /* DABRX flags */
232 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
233 #define H_DABRX_KERNEL     (1ULL<<(63-62))
234 #define H_DABRX_USER       (1ULL<<(63-63))
235 
236 /* Each control block has to be on a 4K boundary */
237 #define H_CB_ALIGNMENT     4096
238 
239 /* pSeries hypervisor opcodes */
240 #define H_REMOVE                0x04
241 #define H_ENTER                 0x08
242 #define H_READ                  0x0c
243 #define H_CLEAR_MOD             0x10
244 #define H_CLEAR_REF             0x14
245 #define H_PROTECT               0x18
246 #define H_GET_TCE               0x1c
247 #define H_PUT_TCE               0x20
248 #define H_SET_SPRG0             0x24
249 #define H_SET_DABR              0x28
250 #define H_PAGE_INIT             0x2c
251 #define H_SET_ASR               0x30
252 #define H_ASR_ON                0x34
253 #define H_ASR_OFF               0x38
254 #define H_LOGICAL_CI_LOAD       0x3c
255 #define H_LOGICAL_CI_STORE      0x40
256 #define H_LOGICAL_CACHE_LOAD    0x44
257 #define H_LOGICAL_CACHE_STORE   0x48
258 #define H_LOGICAL_ICBI          0x4c
259 #define H_LOGICAL_DCBF          0x50
260 #define H_GET_TERM_CHAR         0x54
261 #define H_PUT_TERM_CHAR         0x58
262 #define H_REAL_TO_LOGICAL       0x5c
263 #define H_HYPERVISOR_DATA       0x60
264 #define H_EOI                   0x64
265 #define H_CPPR                  0x68
266 #define H_IPI                   0x6c
267 #define H_IPOLL                 0x70
268 #define H_XIRR                  0x74
269 #define H_PERFMON               0x7c
270 #define H_MIGRATE_DMA           0x78
271 #define H_REGISTER_VPA          0xDC
272 #define H_CEDE                  0xE0
273 #define H_CONFER                0xE4
274 #define H_PROD                  0xE8
275 #define H_GET_PPP               0xEC
276 #define H_SET_PPP               0xF0
277 #define H_PURR                  0xF4
278 #define H_PIC                   0xF8
279 #define H_REG_CRQ               0xFC
280 #define H_FREE_CRQ              0x100
281 #define H_VIO_SIGNAL            0x104
282 #define H_SEND_CRQ              0x108
283 #define H_COPY_RDMA             0x110
284 #define H_REGISTER_LOGICAL_LAN  0x114
285 #define H_FREE_LOGICAL_LAN      0x118
286 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
287 #define H_SEND_LOGICAL_LAN      0x120
288 #define H_BULK_REMOVE           0x124
289 #define H_MULTICAST_CTRL        0x130
290 #define H_SET_XDABR             0x134
291 #define H_STUFF_TCE             0x138
292 #define H_PUT_TCE_INDIRECT      0x13C
293 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
294 #define H_VTERM_PARTNER_INFO    0x150
295 #define H_REGISTER_VTERM        0x154
296 #define H_FREE_VTERM            0x158
297 #define H_RESET_EVENTS          0x15C
298 #define H_ALLOC_RESOURCE        0x160
299 #define H_FREE_RESOURCE         0x164
300 #define H_MODIFY_QP             0x168
301 #define H_QUERY_QP              0x16C
302 #define H_REREGISTER_PMR        0x170
303 #define H_REGISTER_SMR          0x174
304 #define H_QUERY_MR              0x178
305 #define H_QUERY_MW              0x17C
306 #define H_QUERY_HCA             0x180
307 #define H_QUERY_PORT            0x184
308 #define H_MODIFY_PORT           0x188
309 #define H_DEFINE_AQP1           0x18C
310 #define H_GET_TRACE_BUFFER      0x190
311 #define H_DEFINE_AQP0           0x194
312 #define H_RESIZE_MR             0x198
313 #define H_ATTACH_MCQP           0x19C
314 #define H_DETACH_MCQP           0x1A0
315 #define H_CREATE_RPT            0x1A4
316 #define H_REMOVE_RPT            0x1A8
317 #define H_REGISTER_RPAGES       0x1AC
318 #define H_DISABLE_AND_GETC      0x1B0
319 #define H_ERROR_DATA            0x1B4
320 #define H_GET_HCA_INFO          0x1B8
321 #define H_GET_PERF_COUNT        0x1BC
322 #define H_MANAGE_TRACE          0x1C0
323 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
324 #define H_QUERY_INT_STATE       0x1E4
325 #define H_POLL_PENDING          0x1D8
326 #define H_ILLAN_ATTRIBUTES      0x244
327 #define H_MODIFY_HEA_QP         0x250
328 #define H_QUERY_HEA_QP          0x254
329 #define H_QUERY_HEA             0x258
330 #define H_QUERY_HEA_PORT        0x25C
331 #define H_MODIFY_HEA_PORT       0x260
332 #define H_REG_BCMC              0x264
333 #define H_DEREG_BCMC            0x268
334 #define H_REGISTER_HEA_RPAGES   0x26C
335 #define H_DISABLE_AND_GET_HEA   0x270
336 #define H_GET_HEA_INFO          0x274
337 #define H_ALLOC_HEA_RESOURCE    0x278
338 #define H_ADD_CONN              0x284
339 #define H_DEL_CONN              0x288
340 #define H_JOIN                  0x298
341 #define H_VASI_STATE            0x2A4
342 #define H_ENABLE_CRQ            0x2B0
343 #define H_GET_EM_PARMS          0x2B8
344 #define H_SET_MPP               0x2D0
345 #define H_GET_MPP               0x2D4
346 #define H_XIRR_X                0x2FC
347 #define H_RANDOM                0x300
348 #define H_SET_MODE              0x31C
349 #define H_SIGNAL_SYS_RESET      0x380
350 #define MAX_HCALL_OPCODE        H_SIGNAL_SYS_RESET
351 
352 /* The hcalls above are standardized in PAPR and implemented by pHyp
353  * as well.
354  *
355  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
356  * So far we just need one for H_RTAS, but in future we'll need more
357  * for extensions like virtio.  We put those into the 0xf000-0xfffc
358  * range which is reserved by PAPR for "platform-specific" hcalls.
359  */
360 #define KVMPPC_HCALL_BASE       0xf000
361 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
362 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
363 /* Client Architecture support */
364 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
365 #define KVMPPC_HCALL_MAX        KVMPPC_H_CAS
366 
367 typedef struct sPAPRDeviceTreeUpdateHeader {
368     uint32_t version_id;
369 } sPAPRDeviceTreeUpdateHeader;
370 
371 #define hcall_dprintf(fmt, ...) \
372     do { \
373         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
374     } while (0)
375 
376 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
377                                        target_ulong opcode,
378                                        target_ulong *args);
379 
380 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
381 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
382                              target_ulong *args);
383 
384 /* ibm,set-eeh-option */
385 #define RTAS_EEH_DISABLE                 0
386 #define RTAS_EEH_ENABLE                  1
387 #define RTAS_EEH_THAW_IO                 2
388 #define RTAS_EEH_THAW_DMA                3
389 
390 /* ibm,get-config-addr-info2 */
391 #define RTAS_GET_PE_ADDR                 0
392 #define RTAS_GET_PE_MODE                 1
393 #define RTAS_PE_MODE_NONE                0
394 #define RTAS_PE_MODE_NOT_SHARED          1
395 #define RTAS_PE_MODE_SHARED              2
396 
397 /* ibm,read-slot-reset-state2 */
398 #define RTAS_EEH_PE_STATE_NORMAL         0
399 #define RTAS_EEH_PE_STATE_RESET          1
400 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
401 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
402 #define RTAS_EEH_PE_STATE_UNAVAIL        5
403 #define RTAS_EEH_NOT_SUPPORT             0
404 #define RTAS_EEH_SUPPORT                 1
405 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
406 #define RTAS_EEH_PE_RECOVER_INFO         0
407 
408 /* ibm,set-slot-reset */
409 #define RTAS_SLOT_RESET_DEACTIVATE       0
410 #define RTAS_SLOT_RESET_HOT              1
411 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
412 
413 /* ibm,slot-error-detail */
414 #define RTAS_SLOT_TEMP_ERR_LOG           1
415 #define RTAS_SLOT_PERM_ERR_LOG           2
416 
417 /* RTAS return codes */
418 #define RTAS_OUT_SUCCESS                        0
419 #define RTAS_OUT_NO_ERRORS_FOUND                1
420 #define RTAS_OUT_HW_ERROR                       -1
421 #define RTAS_OUT_BUSY                           -2
422 #define RTAS_OUT_PARAM_ERROR                    -3
423 #define RTAS_OUT_NOT_SUPPORTED                  -3
424 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
425 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
426 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
427 
428 /* DDW pagesize mask values from ibm,query-pe-dma-window */
429 #define RTAS_DDW_PGSIZE_4K       0x01
430 #define RTAS_DDW_PGSIZE_64K      0x02
431 #define RTAS_DDW_PGSIZE_16M      0x04
432 #define RTAS_DDW_PGSIZE_32M      0x08
433 #define RTAS_DDW_PGSIZE_64M      0x10
434 #define RTAS_DDW_PGSIZE_128M     0x20
435 #define RTAS_DDW_PGSIZE_256M     0x40
436 #define RTAS_DDW_PGSIZE_16G      0x80
437 
438 /* RTAS tokens */
439 #define RTAS_TOKEN_BASE      0x2000
440 
441 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
442 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
443 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
444 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
445 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
446 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
447 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
448 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
449 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
450 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
451 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
452 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
453 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
454 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
455 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
456 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
457 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
458 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
459 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
460 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
461 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
462 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
463 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
464 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
465 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
466 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
467 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
468 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
469 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
470 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
471 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
472 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
473 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
474 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
475 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
476 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
477 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
478 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
479 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
480 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
481 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
482 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
483 
484 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2A)
485 
486 /* RTAS ibm,get-system-parameter token values */
487 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
488 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
489 #define RTAS_SYSPARM_UUID                        48
490 
491 /* RTAS indicator/sensor types
492  *
493  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
494  *
495  * NOTE: currently only DR-related sensors are implemented here
496  */
497 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
498 #define RTAS_SENSOR_TYPE_DR                     9002
499 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
500 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
501 
502 /* Possible values for the platform-processor-diagnostics-run-mode parameter
503  * of the RTAS ibm,get-system-parameter call.
504  */
505 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
506 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
507 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
508 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
509 
510 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
511 {
512     return addr & ~0xF000000000000000ULL;
513 }
514 
515 static inline uint32_t rtas_ld(target_ulong phys, int n)
516 {
517     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
518 }
519 
520 static inline uint64_t rtas_ldq(target_ulong phys, int n)
521 {
522     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
523 }
524 
525 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
526 {
527     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
528 }
529 
530 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
531                               uint32_t token,
532                               uint32_t nargs, target_ulong args,
533                               uint32_t nret, target_ulong rets);
534 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
535 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
536                              uint32_t token, uint32_t nargs, target_ulong args,
537                              uint32_t nret, target_ulong rets);
538 void spapr_dt_rtas_tokens(void *fdt, int rtas);
539 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
540 
541 #define SPAPR_TCE_PAGE_SHIFT   12
542 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
543 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
544 
545 #define SPAPR_VIO_BASE_LIOBN    0x00000000
546 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
547 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
548     (0x80000000 | ((phb_index) << 8) | (window_num))
549 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
550 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
551 
552 #define RTAS_ERROR_LOG_MAX      2048
553 
554 #define RTAS_EVENT_SCAN_RATE    1
555 
556 typedef struct sPAPRTCETable sPAPRTCETable;
557 
558 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
559 #define SPAPR_TCE_TABLE(obj) \
560     OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
561 
562 struct sPAPRTCETable {
563     DeviceState parent;
564     uint32_t liobn;
565     uint32_t nb_table;
566     uint64_t bus_offset;
567     uint32_t page_shift;
568     uint64_t *table;
569     uint32_t mig_nb_table;
570     uint64_t *mig_table;
571     bool bypass;
572     bool need_vfio;
573     int fd;
574     MemoryRegion root, iommu;
575     struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
576     QLIST_ENTRY(sPAPRTCETable) list;
577 };
578 
579 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
580 
581 struct sPAPREventLogEntry {
582     int log_type;
583     bool exception;
584     void *data;
585     QTAILQ_ENTRY(sPAPREventLogEntry) next;
586 };
587 
588 void spapr_events_init(sPAPRMachineState *sm);
589 void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
590 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
591                                  target_ulong addr, target_ulong size,
592                                  sPAPROptionVector *ov5_updates);
593 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
594 void spapr_tce_table_enable(sPAPRTCETable *tcet,
595                             uint32_t page_shift, uint64_t bus_offset,
596                             uint32_t nb_table);
597 void spapr_tce_table_disable(sPAPRTCETable *tcet);
598 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
599 
600 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
601 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
602                  uint32_t liobn, uint64_t window, uint32_t size);
603 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
604                       sPAPRTCETable *tcet);
605 void spapr_pci_switch_vga(bool big_endian);
606 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
607 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
608 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
609                                        uint32_t count);
610 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
611                                           uint32_t count);
612 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
613                                             uint32_t count, uint32_t index);
614 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
615                                                uint32_t count, uint32_t index);
616 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
617                                     sPAPRMachineState *spapr);
618 
619 /* rtas-configure-connector state */
620 struct sPAPRConfigureConnectorState {
621     uint32_t drc_index;
622     int fdt_offset;
623     int fdt_depth;
624     QTAILQ_ENTRY(sPAPRConfigureConnectorState) next;
625 };
626 
627 void spapr_ccs_reset_hook(void *opaque);
628 
629 #define TYPE_SPAPR_RTC "spapr-rtc"
630 #define TYPE_SPAPR_RNG "spapr-rng"
631 
632 void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns);
633 int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset);
634 
635 int spapr_rng_populate_dt(void *fdt);
636 
637 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
638 
639 /*
640  * This defines the maximum number of DIMM slots we can have for sPAPR
641  * guest. This is not defined by sPAPR but we are defining it to 32 slots
642  * based on default number of slots provided by PowerPC kernel.
643  */
644 #define SPAPR_MAX_RAM_SLOTS     32
645 
646 /* 1GB alignment for hotplug memory region */
647 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
648 
649 /*
650  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
651  * property under ibm,dynamic-reconfiguration-memory node.
652  */
653 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
654 
655 /*
656  * Defines for flag value in ibm,dynamic-memory property under
657  * ibm,dynamic-reconfiguration-memory node.
658  */
659 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
660 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
661 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
662 
663 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
664 
665 #endif /* HW_SPAPR_H */
666