xref: /openbmc/qemu/include/hw/ppc/spapr.h (revision 709395f8)
1 #ifndef HW_SPAPR_H
2 #define HW_SPAPR_H
3 
4 #include "qemu/units.h"
5 #include "sysemu/dma.h"
6 #include "hw/boards.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
10 #include "hw/ppc/spapr_irq.h"
11 #include "hw/ppc/spapr_xive.h"  /* For sPAPRXive */
12 #include "hw/ppc/xics.h"        /* For ICSState */
13 
14 struct VIOsPAPRBus;
15 struct sPAPRPHBState;
16 struct sPAPRNVRAM;
17 
18 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
19 typedef struct sPAPREventSource sPAPREventSource;
20 typedef struct sPAPRPendingHPT sPAPRPendingHPT;
21 
22 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
23 #define SPAPR_ENTRY_POINT       0x100
24 
25 #define SPAPR_TIMEBASE_FREQ     512000000ULL
26 
27 #define TYPE_SPAPR_RTC "spapr-rtc"
28 
29 #define SPAPR_RTC(obj)                                  \
30     OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
31 
32 typedef struct sPAPRRTCState sPAPRRTCState;
33 struct sPAPRRTCState {
34     /*< private >*/
35     DeviceState parent_obj;
36     int64_t ns_offset;
37 };
38 
39 typedef struct sPAPRDIMMState sPAPRDIMMState;
40 typedef struct sPAPRMachineClass sPAPRMachineClass;
41 
42 #define TYPE_SPAPR_MACHINE      "spapr-machine"
43 #define SPAPR_MACHINE(obj) \
44     OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
45 #define SPAPR_MACHINE_GET_CLASS(obj) \
46     OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
47 #define SPAPR_MACHINE_CLASS(klass) \
48     OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
49 
50 typedef enum {
51     SPAPR_RESIZE_HPT_DEFAULT = 0,
52     SPAPR_RESIZE_HPT_DISABLED,
53     SPAPR_RESIZE_HPT_ENABLED,
54     SPAPR_RESIZE_HPT_REQUIRED,
55 } sPAPRResizeHPT;
56 
57 /**
58  * Capabilities
59  */
60 
61 /* Hardware Transactional Memory */
62 #define SPAPR_CAP_HTM                   0x00
63 /* Vector Scalar Extensions */
64 #define SPAPR_CAP_VSX                   0x01
65 /* Decimal Floating Point */
66 #define SPAPR_CAP_DFP                   0x02
67 /* Cache Flush on Privilege Change */
68 #define SPAPR_CAP_CFPC                  0x03
69 /* Speculation Barrier Bounds Checking */
70 #define SPAPR_CAP_SBBC                  0x04
71 /* Indirect Branch Serialisation */
72 #define SPAPR_CAP_IBS                   0x05
73 /* HPT Maximum Page Size (encoded as a shift) */
74 #define SPAPR_CAP_HPT_MAXPAGESIZE       0x06
75 /* Nested KVM-HV */
76 #define SPAPR_CAP_NESTED_KVM_HV         0x07
77 /* Num Caps */
78 #define SPAPR_CAP_NUM                   (SPAPR_CAP_NESTED_KVM_HV + 1)
79 
80 /*
81  * Capability Values
82  */
83 /* Bool Caps */
84 #define SPAPR_CAP_OFF                   0x00
85 #define SPAPR_CAP_ON                    0x01
86 /* Custom Caps */
87 #define SPAPR_CAP_BROKEN                0x00
88 #define SPAPR_CAP_WORKAROUND            0x01
89 #define SPAPR_CAP_FIXED                 0x02
90 #define SPAPR_CAP_FIXED_IBS             0x02
91 #define SPAPR_CAP_FIXED_CCD             0x03
92 
93 typedef struct sPAPRCapabilities sPAPRCapabilities;
94 struct sPAPRCapabilities {
95     uint8_t caps[SPAPR_CAP_NUM];
96 };
97 
98 /**
99  * sPAPRMachineClass:
100  */
101 struct sPAPRMachineClass {
102     /*< private >*/
103     MachineClass parent_class;
104 
105     /*< public >*/
106     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
107     bool dr_phb_enabled;       /* enable dynamic-reconfig/hotplug of PHBs */
108     bool update_dt_enabled;    /* enable KVMPPC_H_UPDATE_DT */
109     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
110     bool pre_2_10_has_unused_icps;
111     bool legacy_irq_allocation;
112 
113     void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
114                           uint64_t *buid, hwaddr *pio,
115                           hwaddr *mmio32, hwaddr *mmio64,
116                           unsigned n_dma, uint32_t *liobns, Error **errp);
117     sPAPRResizeHPT resize_hpt_default;
118     sPAPRCapabilities default_caps;
119     sPAPRIrq *irq;
120 };
121 
122 /**
123  * sPAPRMachineState:
124  */
125 struct sPAPRMachineState {
126     /*< private >*/
127     MachineState parent_obj;
128 
129     struct VIOsPAPRBus *vio_bus;
130     QLIST_HEAD(, sPAPRPHBState) phbs;
131     struct sPAPRNVRAM *nvram;
132     ICSState *ics;
133     sPAPRRTCState rtc;
134 
135     sPAPRResizeHPT resize_hpt;
136     void *htab;
137     uint32_t htab_shift;
138     uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
139     sPAPRPendingHPT *pending_hpt; /* in-progress resize */
140 
141     hwaddr rma_size;
142     int vrma_adjust;
143     ssize_t rtas_size;
144     void *rtas_blob;
145     uint32_t fdt_size;
146     uint32_t fdt_initial_size;
147     void *fdt_blob;
148     long kernel_size;
149     bool kernel_le;
150     uint32_t initrd_base;
151     long initrd_size;
152     uint64_t rtc_offset; /* Now used only during incoming migration */
153     struct PPCTimebase tb;
154     bool has_graphics;
155     uint32_t vsmt;       /* Virtual SMT mode (KVM's "core stride") */
156 
157     Notifier epow_notifier;
158     QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
159     bool use_hotplug_event_source;
160     sPAPREventSource *event_sources;
161 
162     /* ibm,client-architecture-support option negotiation */
163     bool cas_reboot;
164     bool cas_legacy_guest_workaround;
165     sPAPROptionVector *ov5;         /* QEMU-supported option vectors */
166     sPAPROptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
167     uint32_t max_compat_pvr;
168 
169     /* Migration state */
170     int htab_save_index;
171     bool htab_first_pass;
172     int htab_fd;
173 
174     /* Pending DIMM unplug cache. It is populated when a LMB
175      * unplug starts. It can be regenerated if a migration
176      * occurs during the unplug process. */
177     QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs;
178 
179     /*< public >*/
180     char *kvm_type;
181     char *host_model;
182     char *host_serial;
183 
184     int32_t irq_map_nr;
185     unsigned long *irq_map;
186     sPAPRXive  *xive;
187     sPAPRIrq *irq;
188     qemu_irq *qirqs;
189 
190     bool cmd_line_caps[SPAPR_CAP_NUM];
191     sPAPRCapabilities def, eff, mig;
192 };
193 
194 #define H_SUCCESS         0
195 #define H_BUSY            1        /* Hardware busy -- retry later */
196 #define H_CLOSED          2        /* Resource closed */
197 #define H_NOT_AVAILABLE   3
198 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
199 #define H_PARTIAL         5
200 #define H_IN_PROGRESS     14       /* Kind of like busy */
201 #define H_PAGE_REGISTERED 15
202 #define H_PARTIAL_STORE   16
203 #define H_PENDING         17       /* returned from H_POLL_PENDING */
204 #define H_CONTINUE        18       /* Returned from H_Join on success */
205 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
206 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
207                                                  is a good time to retry */
208 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
209                                                  is a good time to retry */
210 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
211                                                  is a good time to retry */
212 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
213                                                  is a good time to retry */
214 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
215                                                  is a good time to retry */
216 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
217                                                  is a good time to retry */
218 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
219 #define H_HARDWARE        -1       /* Hardware error */
220 #define H_FUNCTION        -2       /* Function not supported */
221 #define H_PRIVILEGE       -3       /* Caller not privileged */
222 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
223 #define H_BAD_MODE        -5       /* Illegal msr value */
224 #define H_PTEG_FULL       -6       /* PTEG is full */
225 #define H_NOT_FOUND       -7       /* PTE was not found" */
226 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
227 #define H_NO_MEM          -9
228 #define H_AUTHORITY       -10
229 #define H_PERMISSION      -11
230 #define H_DROPPED         -12
231 #define H_SOURCE_PARM     -13
232 #define H_DEST_PARM       -14
233 #define H_REMOTE_PARM     -15
234 #define H_RESOURCE        -16
235 #define H_ADAPTER_PARM    -17
236 #define H_RH_PARM         -18
237 #define H_RCQ_PARM        -19
238 #define H_SCQ_PARM        -20
239 #define H_EQ_PARM         -21
240 #define H_RT_PARM         -22
241 #define H_ST_PARM         -23
242 #define H_SIGT_PARM       -24
243 #define H_TOKEN_PARM      -25
244 #define H_MLENGTH_PARM    -27
245 #define H_MEM_PARM        -28
246 #define H_MEM_ACCESS_PARM -29
247 #define H_ATTR_PARM       -30
248 #define H_PORT_PARM       -31
249 #define H_MCG_PARM        -32
250 #define H_VL_PARM         -33
251 #define H_TSIZE_PARM      -34
252 #define H_TRACE_PARM      -35
253 
254 #define H_MASK_PARM       -37
255 #define H_MCG_FULL        -38
256 #define H_ALIAS_EXIST     -39
257 #define H_P_COUNTER       -40
258 #define H_TABLE_FULL      -41
259 #define H_ALT_TABLE       -42
260 #define H_MR_CONDITION    -43
261 #define H_NOT_ENOUGH_RESOURCES -44
262 #define H_R_STATE         -45
263 #define H_RESCINDEND      -46
264 #define H_P2              -55
265 #define H_P3              -56
266 #define H_P4              -57
267 #define H_P5              -58
268 #define H_P6              -59
269 #define H_P7              -60
270 #define H_P8              -61
271 #define H_P9              -62
272 #define H_UNSUPPORTED_FLAG -256
273 #define H_MULTI_THREADS_ACTIVE -9005
274 
275 
276 /* Long Busy is a condition that can be returned by the firmware
277  * when a call cannot be completed now, but the identical call
278  * should be retried later.  This prevents calls blocking in the
279  * firmware for long periods of time.  Annoyingly the firmware can return
280  * a range of return codes, hinting at how long we should wait before
281  * retrying.  If you don't care for the hint, the macro below is a good
282  * way to check for the long_busy return codes
283  */
284 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
285                             && (x <= H_LONG_BUSY_END_RANGE))
286 
287 /* Flags */
288 #define H_LARGE_PAGE      (1ULL<<(63-16))
289 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
290 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
291 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
292 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
293 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
294 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
295 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
296 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
297 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
298 #define H_ANDCOND         (1ULL<<(63-33))
299 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
300 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
301 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
302 #define H_COPY_PAGE       (1ULL<<(63-49))
303 #define H_N               (1ULL<<(63-61))
304 #define H_PP1             (1ULL<<(63-62))
305 #define H_PP2             (1ULL<<(63-63))
306 
307 /* Values for 2nd argument to H_SET_MODE */
308 #define H_SET_MODE_RESOURCE_SET_CIABR           1
309 #define H_SET_MODE_RESOURCE_SET_DAWR            2
310 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
311 #define H_SET_MODE_RESOURCE_LE                  4
312 
313 /* Flags for H_SET_MODE_RESOURCE_LE */
314 #define H_SET_MODE_ENDIAN_BIG    0
315 #define H_SET_MODE_ENDIAN_LITTLE 1
316 
317 /* VASI States */
318 #define H_VASI_INVALID    0
319 #define H_VASI_ENABLED    1
320 #define H_VASI_ABORTED    2
321 #define H_VASI_SUSPENDING 3
322 #define H_VASI_SUSPENDED  4
323 #define H_VASI_RESUMED    5
324 #define H_VASI_COMPLETED  6
325 
326 /* DABRX flags */
327 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
328 #define H_DABRX_KERNEL     (1ULL<<(63-62))
329 #define H_DABRX_USER       (1ULL<<(63-63))
330 
331 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
332 #define H_CPU_CHAR_SPEC_BAR_ORI31               PPC_BIT(0)
333 #define H_CPU_CHAR_BCCTRL_SERIALISED            PPC_BIT(1)
334 #define H_CPU_CHAR_L1D_FLUSH_ORI30              PPC_BIT(2)
335 #define H_CPU_CHAR_L1D_FLUSH_TRIG2              PPC_BIT(3)
336 #define H_CPU_CHAR_L1D_THREAD_PRIV              PPC_BIT(4)
337 #define H_CPU_CHAR_HON_BRANCH_HINTS             PPC_BIT(5)
338 #define H_CPU_CHAR_THR_RECONF_TRIG              PPC_BIT(6)
339 #define H_CPU_CHAR_CACHE_COUNT_DIS              PPC_BIT(7)
340 #define H_CPU_BEHAV_FAVOUR_SECURITY             PPC_BIT(0)
341 #define H_CPU_BEHAV_L1D_FLUSH_PR                PPC_BIT(1)
342 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR           PPC_BIT(2)
343 
344 /* Each control block has to be on a 4K boundary */
345 #define H_CB_ALIGNMENT     4096
346 
347 /* pSeries hypervisor opcodes */
348 #define H_REMOVE                0x04
349 #define H_ENTER                 0x08
350 #define H_READ                  0x0c
351 #define H_CLEAR_MOD             0x10
352 #define H_CLEAR_REF             0x14
353 #define H_PROTECT               0x18
354 #define H_GET_TCE               0x1c
355 #define H_PUT_TCE               0x20
356 #define H_SET_SPRG0             0x24
357 #define H_SET_DABR              0x28
358 #define H_PAGE_INIT             0x2c
359 #define H_SET_ASR               0x30
360 #define H_ASR_ON                0x34
361 #define H_ASR_OFF               0x38
362 #define H_LOGICAL_CI_LOAD       0x3c
363 #define H_LOGICAL_CI_STORE      0x40
364 #define H_LOGICAL_CACHE_LOAD    0x44
365 #define H_LOGICAL_CACHE_STORE   0x48
366 #define H_LOGICAL_ICBI          0x4c
367 #define H_LOGICAL_DCBF          0x50
368 #define H_GET_TERM_CHAR         0x54
369 #define H_PUT_TERM_CHAR         0x58
370 #define H_REAL_TO_LOGICAL       0x5c
371 #define H_HYPERVISOR_DATA       0x60
372 #define H_EOI                   0x64
373 #define H_CPPR                  0x68
374 #define H_IPI                   0x6c
375 #define H_IPOLL                 0x70
376 #define H_XIRR                  0x74
377 #define H_PERFMON               0x7c
378 #define H_MIGRATE_DMA           0x78
379 #define H_REGISTER_VPA          0xDC
380 #define H_CEDE                  0xE0
381 #define H_CONFER                0xE4
382 #define H_PROD                  0xE8
383 #define H_GET_PPP               0xEC
384 #define H_SET_PPP               0xF0
385 #define H_PURR                  0xF4
386 #define H_PIC                   0xF8
387 #define H_REG_CRQ               0xFC
388 #define H_FREE_CRQ              0x100
389 #define H_VIO_SIGNAL            0x104
390 #define H_SEND_CRQ              0x108
391 #define H_COPY_RDMA             0x110
392 #define H_REGISTER_LOGICAL_LAN  0x114
393 #define H_FREE_LOGICAL_LAN      0x118
394 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
395 #define H_SEND_LOGICAL_LAN      0x120
396 #define H_BULK_REMOVE           0x124
397 #define H_MULTICAST_CTRL        0x130
398 #define H_SET_XDABR             0x134
399 #define H_STUFF_TCE             0x138
400 #define H_PUT_TCE_INDIRECT      0x13C
401 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
402 #define H_VTERM_PARTNER_INFO    0x150
403 #define H_REGISTER_VTERM        0x154
404 #define H_FREE_VTERM            0x158
405 #define H_RESET_EVENTS          0x15C
406 #define H_ALLOC_RESOURCE        0x160
407 #define H_FREE_RESOURCE         0x164
408 #define H_MODIFY_QP             0x168
409 #define H_QUERY_QP              0x16C
410 #define H_REREGISTER_PMR        0x170
411 #define H_REGISTER_SMR          0x174
412 #define H_QUERY_MR              0x178
413 #define H_QUERY_MW              0x17C
414 #define H_QUERY_HCA             0x180
415 #define H_QUERY_PORT            0x184
416 #define H_MODIFY_PORT           0x188
417 #define H_DEFINE_AQP1           0x18C
418 #define H_GET_TRACE_BUFFER      0x190
419 #define H_DEFINE_AQP0           0x194
420 #define H_RESIZE_MR             0x198
421 #define H_ATTACH_MCQP           0x19C
422 #define H_DETACH_MCQP           0x1A0
423 #define H_CREATE_RPT            0x1A4
424 #define H_REMOVE_RPT            0x1A8
425 #define H_REGISTER_RPAGES       0x1AC
426 #define H_DISABLE_AND_GETC      0x1B0
427 #define H_ERROR_DATA            0x1B4
428 #define H_GET_HCA_INFO          0x1B8
429 #define H_GET_PERF_COUNT        0x1BC
430 #define H_MANAGE_TRACE          0x1C0
431 #define H_GET_CPU_CHARACTERISTICS 0x1C8
432 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
433 #define H_QUERY_INT_STATE       0x1E4
434 #define H_POLL_PENDING          0x1D8
435 #define H_ILLAN_ATTRIBUTES      0x244
436 #define H_MODIFY_HEA_QP         0x250
437 #define H_QUERY_HEA_QP          0x254
438 #define H_QUERY_HEA             0x258
439 #define H_QUERY_HEA_PORT        0x25C
440 #define H_MODIFY_HEA_PORT       0x260
441 #define H_REG_BCMC              0x264
442 #define H_DEREG_BCMC            0x268
443 #define H_REGISTER_HEA_RPAGES   0x26C
444 #define H_DISABLE_AND_GET_HEA   0x270
445 #define H_GET_HEA_INFO          0x274
446 #define H_ALLOC_HEA_RESOURCE    0x278
447 #define H_ADD_CONN              0x284
448 #define H_DEL_CONN              0x288
449 #define H_JOIN                  0x298
450 #define H_VASI_STATE            0x2A4
451 #define H_ENABLE_CRQ            0x2B0
452 #define H_GET_EM_PARMS          0x2B8
453 #define H_SET_MPP               0x2D0
454 #define H_GET_MPP               0x2D4
455 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
456 #define H_XIRR_X                0x2FC
457 #define H_RANDOM                0x300
458 #define H_SET_MODE              0x31C
459 #define H_RESIZE_HPT_PREPARE    0x36C
460 #define H_RESIZE_HPT_COMMIT     0x370
461 #define H_CLEAN_SLB             0x374
462 #define H_INVALIDATE_PID        0x378
463 #define H_REGISTER_PROC_TBL     0x37C
464 #define H_SIGNAL_SYS_RESET      0x380
465 
466 #define H_INT_GET_SOURCE_INFO   0x3A8
467 #define H_INT_SET_SOURCE_CONFIG 0x3AC
468 #define H_INT_GET_SOURCE_CONFIG 0x3B0
469 #define H_INT_GET_QUEUE_INFO    0x3B4
470 #define H_INT_SET_QUEUE_CONFIG  0x3B8
471 #define H_INT_GET_QUEUE_CONFIG  0x3BC
472 #define H_INT_SET_OS_REPORTING_LINE 0x3C0
473 #define H_INT_GET_OS_REPORTING_LINE 0x3C4
474 #define H_INT_ESB               0x3C8
475 #define H_INT_SYNC              0x3CC
476 #define H_INT_RESET             0x3D0
477 
478 #define MAX_HCALL_OPCODE        H_INT_RESET
479 
480 /* The hcalls above are standardized in PAPR and implemented by pHyp
481  * as well.
482  *
483  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
484  * We put those into the 0xf000-0xfffc range which is reserved by PAPR
485  * for "platform-specific" hcalls.
486  */
487 #define KVMPPC_HCALL_BASE       0xf000
488 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
489 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
490 /* Client Architecture support */
491 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
492 #define KVMPPC_H_UPDATE_DT      (KVMPPC_HCALL_BASE + 0x3)
493 #define KVMPPC_HCALL_MAX        KVMPPC_H_UPDATE_DT
494 
495 typedef struct sPAPRDeviceTreeUpdateHeader {
496     uint32_t version_id;
497 } sPAPRDeviceTreeUpdateHeader;
498 
499 #define hcall_dprintf(fmt, ...) \
500     do { \
501         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
502     } while (0)
503 
504 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
505                                        target_ulong opcode,
506                                        target_ulong *args);
507 
508 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
509 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
510                              target_ulong *args);
511 
512 /* ibm,set-eeh-option */
513 #define RTAS_EEH_DISABLE                 0
514 #define RTAS_EEH_ENABLE                  1
515 #define RTAS_EEH_THAW_IO                 2
516 #define RTAS_EEH_THAW_DMA                3
517 
518 /* ibm,get-config-addr-info2 */
519 #define RTAS_GET_PE_ADDR                 0
520 #define RTAS_GET_PE_MODE                 1
521 #define RTAS_PE_MODE_NONE                0
522 #define RTAS_PE_MODE_NOT_SHARED          1
523 #define RTAS_PE_MODE_SHARED              2
524 
525 /* ibm,read-slot-reset-state2 */
526 #define RTAS_EEH_PE_STATE_NORMAL         0
527 #define RTAS_EEH_PE_STATE_RESET          1
528 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
529 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
530 #define RTAS_EEH_PE_STATE_UNAVAIL        5
531 #define RTAS_EEH_NOT_SUPPORT             0
532 #define RTAS_EEH_SUPPORT                 1
533 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
534 #define RTAS_EEH_PE_RECOVER_INFO         0
535 
536 /* ibm,set-slot-reset */
537 #define RTAS_SLOT_RESET_DEACTIVATE       0
538 #define RTAS_SLOT_RESET_HOT              1
539 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
540 
541 /* ibm,slot-error-detail */
542 #define RTAS_SLOT_TEMP_ERR_LOG           1
543 #define RTAS_SLOT_PERM_ERR_LOG           2
544 
545 /* RTAS return codes */
546 #define RTAS_OUT_SUCCESS                        0
547 #define RTAS_OUT_NO_ERRORS_FOUND                1
548 #define RTAS_OUT_HW_ERROR                       -1
549 #define RTAS_OUT_BUSY                           -2
550 #define RTAS_OUT_PARAM_ERROR                    -3
551 #define RTAS_OUT_NOT_SUPPORTED                  -3
552 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
553 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
554 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
555 
556 /* DDW pagesize mask values from ibm,query-pe-dma-window */
557 #define RTAS_DDW_PGSIZE_4K       0x01
558 #define RTAS_DDW_PGSIZE_64K      0x02
559 #define RTAS_DDW_PGSIZE_16M      0x04
560 #define RTAS_DDW_PGSIZE_32M      0x08
561 #define RTAS_DDW_PGSIZE_64M      0x10
562 #define RTAS_DDW_PGSIZE_128M     0x20
563 #define RTAS_DDW_PGSIZE_256M     0x40
564 #define RTAS_DDW_PGSIZE_16G      0x80
565 
566 /* RTAS tokens */
567 #define RTAS_TOKEN_BASE      0x2000
568 
569 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
570 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
571 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
572 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
573 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
574 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
575 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
576 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
577 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
578 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
579 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
580 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
581 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
582 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
583 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
584 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
585 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
586 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
587 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
588 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
589 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
590 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
591 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
592 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
593 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
594 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
595 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
596 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
597 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
598 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
599 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
600 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
601 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
602 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
603 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
604 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
605 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
606 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
607 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
608 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
609 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
610 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
611 
612 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2A)
613 
614 /* RTAS ibm,get-system-parameter token values */
615 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
616 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
617 #define RTAS_SYSPARM_UUID                        48
618 
619 /* RTAS indicator/sensor types
620  *
621  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
622  *
623  * NOTE: currently only DR-related sensors are implemented here
624  */
625 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
626 #define RTAS_SENSOR_TYPE_DR                     9002
627 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
628 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
629 
630 /* Possible values for the platform-processor-diagnostics-run-mode parameter
631  * of the RTAS ibm,get-system-parameter call.
632  */
633 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
634 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
635 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
636 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
637 
638 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
639 {
640     return addr & ~0xF000000000000000ULL;
641 }
642 
643 static inline uint32_t rtas_ld(target_ulong phys, int n)
644 {
645     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
646 }
647 
648 static inline uint64_t rtas_ldq(target_ulong phys, int n)
649 {
650     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
651 }
652 
653 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
654 {
655     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
656 }
657 
658 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
659                               uint32_t token,
660                               uint32_t nargs, target_ulong args,
661                               uint32_t nret, target_ulong rets);
662 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
663 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
664                              uint32_t token, uint32_t nargs, target_ulong args,
665                              uint32_t nret, target_ulong rets);
666 void spapr_dt_rtas_tokens(void *fdt, int rtas);
667 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
668 
669 #define SPAPR_TCE_PAGE_SHIFT   12
670 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
671 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
672 
673 #define SPAPR_VIO_BASE_LIOBN    0x00000000
674 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
675 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
676     (0x80000000 | ((phb_index) << 8) | (window_num))
677 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
678 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
679 
680 #define RTAS_ERROR_LOG_MAX      2048
681 
682 #define RTAS_EVENT_SCAN_RATE    1
683 
684 /* This helper should be used to encode interrupt specifiers when the related
685  * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
686  * VIO devices, RTAS event sources and PHBs).
687  */
688 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
689 {
690     intspec[0] = cpu_to_be32(irq);
691     intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
692 }
693 
694 typedef struct sPAPRTCETable sPAPRTCETable;
695 
696 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
697 #define SPAPR_TCE_TABLE(obj) \
698     OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
699 
700 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
701 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
702         OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
703 
704 struct sPAPRTCETable {
705     DeviceState parent;
706     uint32_t liobn;
707     uint32_t nb_table;
708     uint64_t bus_offset;
709     uint32_t page_shift;
710     uint64_t *table;
711     uint32_t mig_nb_table;
712     uint64_t *mig_table;
713     bool bypass;
714     bool need_vfio;
715     int fd;
716     MemoryRegion root;
717     IOMMUMemoryRegion iommu;
718     struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
719     QLIST_ENTRY(sPAPRTCETable) list;
720 };
721 
722 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
723 
724 struct sPAPREventLogEntry {
725     uint32_t summary;
726     uint32_t extended_length;
727     void *extended_log;
728     QTAILQ_ENTRY(sPAPREventLogEntry) next;
729 };
730 
731 void spapr_events_init(sPAPRMachineState *sm);
732 void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
733 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
734                                  target_ulong addr, target_ulong size,
735                                  sPAPROptionVector *ov5_updates);
736 void close_htab_fd(sPAPRMachineState *spapr);
737 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr);
738 void spapr_free_hpt(sPAPRMachineState *spapr);
739 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
740 void spapr_tce_table_enable(sPAPRTCETable *tcet,
741                             uint32_t page_shift, uint64_t bus_offset,
742                             uint32_t nb_table);
743 void spapr_tce_table_disable(sPAPRTCETable *tcet);
744 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
745 
746 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
747 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
748                  uint32_t liobn, uint64_t window, uint32_t size);
749 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
750                       sPAPRTCETable *tcet);
751 void spapr_pci_switch_vga(bool big_endian);
752 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
753 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
754 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
755                                        uint32_t count);
756 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
757                                           uint32_t count);
758 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
759                                             uint32_t count, uint32_t index);
760 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
761                                                uint32_t count, uint32_t index);
762 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
763 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
764                           Error **errp);
765 void spapr_clear_pending_events(sPAPRMachineState *spapr);
766 int spapr_max_server_number(sPAPRMachineState *spapr);
767 
768 /* DRC callbacks. */
769 void spapr_core_release(DeviceState *dev);
770 int spapr_core_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr,
771                            void *fdt, int *fdt_start_offset, Error **errp);
772 void spapr_lmb_release(DeviceState *dev);
773 int spapr_lmb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr,
774                           void *fdt, int *fdt_start_offset, Error **errp);
775 void spapr_phb_release(DeviceState *dev);
776 int spapr_phb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr,
777                           void *fdt, int *fdt_start_offset, Error **errp);
778 
779 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns);
780 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
781 
782 #define TYPE_SPAPR_RNG "spapr-rng"
783 
784 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
785 
786 /*
787  * This defines the maximum number of DIMM slots we can have for sPAPR
788  * guest. This is not defined by sPAPR but we are defining it to 32 slots
789  * based on default number of slots provided by PowerPC kernel.
790  */
791 #define SPAPR_MAX_RAM_SLOTS     32
792 
793 /* 1GB alignment for hotplug memory region */
794 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
795 
796 /*
797  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
798  * property under ibm,dynamic-reconfiguration-memory node.
799  */
800 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
801 
802 /*
803  * Defines for flag value in ibm,dynamic-memory property under
804  * ibm,dynamic-reconfiguration-memory node.
805  */
806 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
807 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
808 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
809 
810 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
811 
812 #define HTAB_SIZE(spapr)        (1ULL << ((spapr)->htab_shift))
813 
814 int spapr_get_vcpu_id(PowerPCCPU *cpu);
815 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
816 PowerPCCPU *spapr_find_cpu(int vcpu_id);
817 
818 int spapr_caps_pre_load(void *opaque);
819 int spapr_caps_pre_save(void *opaque);
820 
821 /*
822  * Handling of optional capabilities
823  */
824 extern const VMStateDescription vmstate_spapr_cap_htm;
825 extern const VMStateDescription vmstate_spapr_cap_vsx;
826 extern const VMStateDescription vmstate_spapr_cap_dfp;
827 extern const VMStateDescription vmstate_spapr_cap_cfpc;
828 extern const VMStateDescription vmstate_spapr_cap_sbbc;
829 extern const VMStateDescription vmstate_spapr_cap_ibs;
830 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
831 
832 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap)
833 {
834     return spapr->eff.caps[cap];
835 }
836 
837 void spapr_caps_init(sPAPRMachineState *spapr);
838 void spapr_caps_apply(sPAPRMachineState *spapr);
839 void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu);
840 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp);
841 int spapr_caps_post_migration(sPAPRMachineState *spapr);
842 
843 void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize,
844                           Error **errp);
845 /*
846  * XIVE definitions
847  */
848 #define SPAPR_OV5_XIVE_LEGACY   0x0
849 #define SPAPR_OV5_XIVE_EXPLOIT  0x40
850 #define SPAPR_OV5_XIVE_BOTH     0x80 /* Only to advertise on the platform */
851 
852 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
853 #endif /* HW_SPAPR_H */
854