1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 12 #include "hw/ppc/xics.h" /* For ICSState */ 13 #include "hw/ppc/spapr_tpm_proxy.h" 14 15 struct SpaprVioBus; 16 struct SpaprPhbState; 17 struct SpaprNvram; 18 19 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 20 typedef struct SpaprEventSource SpaprEventSource; 21 typedef struct SpaprPendingHpt SpaprPendingHpt; 22 23 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 24 #define SPAPR_ENTRY_POINT 0x100 25 26 #define SPAPR_TIMEBASE_FREQ 512000000ULL 27 28 #define TYPE_SPAPR_RTC "spapr-rtc" 29 30 #define SPAPR_RTC(obj) \ 31 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 32 33 typedef struct SpaprRtcState SpaprRtcState; 34 struct SpaprRtcState { 35 /*< private >*/ 36 DeviceState parent_obj; 37 int64_t ns_offset; 38 }; 39 40 typedef struct SpaprDimmState SpaprDimmState; 41 typedef struct SpaprMachineClass SpaprMachineClass; 42 43 #define TYPE_SPAPR_MACHINE "spapr-machine" 44 #define SPAPR_MACHINE(obj) \ 45 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 46 #define SPAPR_MACHINE_GET_CLASS(obj) \ 47 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 48 #define SPAPR_MACHINE_CLASS(klass) \ 49 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 50 51 typedef enum { 52 SPAPR_RESIZE_HPT_DEFAULT = 0, 53 SPAPR_RESIZE_HPT_DISABLED, 54 SPAPR_RESIZE_HPT_ENABLED, 55 SPAPR_RESIZE_HPT_REQUIRED, 56 } SpaprResizeHpt; 57 58 /** 59 * Capabilities 60 */ 61 62 /* Hardware Transactional Memory */ 63 #define SPAPR_CAP_HTM 0x00 64 /* Vector Scalar Extensions */ 65 #define SPAPR_CAP_VSX 0x01 66 /* Decimal Floating Point */ 67 #define SPAPR_CAP_DFP 0x02 68 /* Cache Flush on Privilege Change */ 69 #define SPAPR_CAP_CFPC 0x03 70 /* Speculation Barrier Bounds Checking */ 71 #define SPAPR_CAP_SBBC 0x04 72 /* Indirect Branch Serialisation */ 73 #define SPAPR_CAP_IBS 0x05 74 /* HPT Maximum Page Size (encoded as a shift) */ 75 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 76 /* Nested KVM-HV */ 77 #define SPAPR_CAP_NESTED_KVM_HV 0x07 78 /* Large Decrementer */ 79 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 80 /* Count Cache Flush Assist HW Instruction */ 81 #define SPAPR_CAP_CCF_ASSIST 0x09 82 /* FWNMI machine check handling */ 83 #define SPAPR_CAP_FWNMI_MCE 0x0A 84 /* Num Caps */ 85 #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1) 86 87 /* 88 * Capability Values 89 */ 90 /* Bool Caps */ 91 #define SPAPR_CAP_OFF 0x00 92 #define SPAPR_CAP_ON 0x01 93 94 /* Custom Caps */ 95 96 /* Generic */ 97 #define SPAPR_CAP_BROKEN 0x00 98 #define SPAPR_CAP_WORKAROUND 0x01 99 #define SPAPR_CAP_FIXED 0x02 100 /* SPAPR_CAP_IBS (cap-ibs) */ 101 #define SPAPR_CAP_FIXED_IBS 0x02 102 #define SPAPR_CAP_FIXED_CCD 0x03 103 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 104 105 typedef struct SpaprCapabilities SpaprCapabilities; 106 struct SpaprCapabilities { 107 uint8_t caps[SPAPR_CAP_NUM]; 108 }; 109 110 /** 111 * SpaprMachineClass: 112 */ 113 struct SpaprMachineClass { 114 /*< private >*/ 115 MachineClass parent_class; 116 117 /*< public >*/ 118 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 119 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 120 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 121 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 122 bool pre_2_10_has_unused_icps; 123 bool legacy_irq_allocation; 124 uint32_t nr_xirqs; 125 bool broken_host_serial_model; /* present real host info to the guest */ 126 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 127 bool linux_pci_probe; 128 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 129 130 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 131 uint64_t *buid, hwaddr *pio, 132 hwaddr *mmio32, hwaddr *mmio64, 133 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 134 hwaddr *nv2atsd, Error **errp); 135 SpaprResizeHpt resize_hpt_default; 136 SpaprCapabilities default_caps; 137 SpaprIrq *irq; 138 }; 139 140 /** 141 * SpaprMachineState: 142 */ 143 struct SpaprMachineState { 144 /*< private >*/ 145 MachineState parent_obj; 146 147 struct SpaprVioBus *vio_bus; 148 QLIST_HEAD(, SpaprPhbState) phbs; 149 struct SpaprNvram *nvram; 150 SpaprRtcState rtc; 151 152 SpaprResizeHpt resize_hpt; 153 void *htab; 154 uint32_t htab_shift; 155 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 156 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 157 158 hwaddr rma_size; 159 int vrma_adjust; 160 uint32_t fdt_size; 161 uint32_t fdt_initial_size; 162 void *fdt_blob; 163 long kernel_size; 164 bool kernel_le; 165 uint64_t kernel_addr; 166 uint32_t initrd_base; 167 long initrd_size; 168 uint64_t rtc_offset; /* Now used only during incoming migration */ 169 struct PPCTimebase tb; 170 bool has_graphics; 171 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 172 173 Notifier epow_notifier; 174 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 175 bool use_hotplug_event_source; 176 SpaprEventSource *event_sources; 177 178 /* ibm,client-architecture-support option negotiation */ 179 bool cas_reboot; 180 bool cas_pre_isa3_guest; 181 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 182 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 183 uint32_t max_compat_pvr; 184 185 /* Migration state */ 186 int htab_save_index; 187 bool htab_first_pass; 188 int htab_fd; 189 190 /* Pending DIMM unplug cache. It is populated when a LMB 191 * unplug starts. It can be regenerated if a migration 192 * occurs during the unplug process. */ 193 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 194 195 /* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */ 196 target_ulong guest_machine_check_addr; 197 /* 198 * mc_status is set to -1 if mc is not in progress, else is set to the CPU 199 * handling the mc. 200 */ 201 int mc_status; 202 QemuCond mc_delivery_cond; 203 204 /*< public >*/ 205 char *kvm_type; 206 char *host_model; 207 char *host_serial; 208 209 int32_t irq_map_nr; 210 unsigned long *irq_map; 211 SpaprIrq *irq; 212 qemu_irq *qirqs; 213 SpaprInterruptController *active_intc; 214 ICSState *ics; 215 SpaprXive *xive; 216 217 bool cmd_line_caps[SPAPR_CAP_NUM]; 218 SpaprCapabilities def, eff, mig; 219 220 unsigned gpu_numa_id; 221 SpaprTpmProxy *tpm_proxy; 222 223 Error *fwnmi_migration_blocker; 224 }; 225 226 #define H_SUCCESS 0 227 #define H_BUSY 1 /* Hardware busy -- retry later */ 228 #define H_CLOSED 2 /* Resource closed */ 229 #define H_NOT_AVAILABLE 3 230 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 231 #define H_PARTIAL 5 232 #define H_IN_PROGRESS 14 /* Kind of like busy */ 233 #define H_PAGE_REGISTERED 15 234 #define H_PARTIAL_STORE 16 235 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 236 #define H_CONTINUE 18 /* Returned from H_Join on success */ 237 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 238 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 239 is a good time to retry */ 240 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 241 is a good time to retry */ 242 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 243 is a good time to retry */ 244 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 245 is a good time to retry */ 246 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 247 is a good time to retry */ 248 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 249 is a good time to retry */ 250 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 251 #define H_HARDWARE -1 /* Hardware error */ 252 #define H_FUNCTION -2 /* Function not supported */ 253 #define H_PRIVILEGE -3 /* Caller not privileged */ 254 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 255 #define H_BAD_MODE -5 /* Illegal msr value */ 256 #define H_PTEG_FULL -6 /* PTEG is full */ 257 #define H_NOT_FOUND -7 /* PTE was not found" */ 258 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 259 #define H_NO_MEM -9 260 #define H_AUTHORITY -10 261 #define H_PERMISSION -11 262 #define H_DROPPED -12 263 #define H_SOURCE_PARM -13 264 #define H_DEST_PARM -14 265 #define H_REMOTE_PARM -15 266 #define H_RESOURCE -16 267 #define H_ADAPTER_PARM -17 268 #define H_RH_PARM -18 269 #define H_RCQ_PARM -19 270 #define H_SCQ_PARM -20 271 #define H_EQ_PARM -21 272 #define H_RT_PARM -22 273 #define H_ST_PARM -23 274 #define H_SIGT_PARM -24 275 #define H_TOKEN_PARM -25 276 #define H_MLENGTH_PARM -27 277 #define H_MEM_PARM -28 278 #define H_MEM_ACCESS_PARM -29 279 #define H_ATTR_PARM -30 280 #define H_PORT_PARM -31 281 #define H_MCG_PARM -32 282 #define H_VL_PARM -33 283 #define H_TSIZE_PARM -34 284 #define H_TRACE_PARM -35 285 286 #define H_MASK_PARM -37 287 #define H_MCG_FULL -38 288 #define H_ALIAS_EXIST -39 289 #define H_P_COUNTER -40 290 #define H_TABLE_FULL -41 291 #define H_ALT_TABLE -42 292 #define H_MR_CONDITION -43 293 #define H_NOT_ENOUGH_RESOURCES -44 294 #define H_R_STATE -45 295 #define H_RESCINDEND -46 296 #define H_P2 -55 297 #define H_P3 -56 298 #define H_P4 -57 299 #define H_P5 -58 300 #define H_P6 -59 301 #define H_P7 -60 302 #define H_P8 -61 303 #define H_P9 -62 304 #define H_OVERLAP -68 305 #define H_UNSUPPORTED_FLAG -256 306 #define H_MULTI_THREADS_ACTIVE -9005 307 308 309 /* Long Busy is a condition that can be returned by the firmware 310 * when a call cannot be completed now, but the identical call 311 * should be retried later. This prevents calls blocking in the 312 * firmware for long periods of time. Annoyingly the firmware can return 313 * a range of return codes, hinting at how long we should wait before 314 * retrying. If you don't care for the hint, the macro below is a good 315 * way to check for the long_busy return codes 316 */ 317 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 318 && (x <= H_LONG_BUSY_END_RANGE)) 319 320 /* Flags */ 321 #define H_LARGE_PAGE (1ULL<<(63-16)) 322 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 323 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 324 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 325 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 326 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 327 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 328 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 329 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 330 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 331 #define H_ANDCOND (1ULL<<(63-33)) 332 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 333 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 334 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 335 #define H_COPY_PAGE (1ULL<<(63-49)) 336 #define H_N (1ULL<<(63-61)) 337 #define H_PP1 (1ULL<<(63-62)) 338 #define H_PP2 (1ULL<<(63-63)) 339 340 /* Values for 2nd argument to H_SET_MODE */ 341 #define H_SET_MODE_RESOURCE_SET_CIABR 1 342 #define H_SET_MODE_RESOURCE_SET_DAWR 2 343 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 344 #define H_SET_MODE_RESOURCE_LE 4 345 346 /* Flags for H_SET_MODE_RESOURCE_LE */ 347 #define H_SET_MODE_ENDIAN_BIG 0 348 #define H_SET_MODE_ENDIAN_LITTLE 1 349 350 /* VASI States */ 351 #define H_VASI_INVALID 0 352 #define H_VASI_ENABLED 1 353 #define H_VASI_ABORTED 2 354 #define H_VASI_SUSPENDING 3 355 #define H_VASI_SUSPENDED 4 356 #define H_VASI_RESUMED 5 357 #define H_VASI_COMPLETED 6 358 359 /* DABRX flags */ 360 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 361 #define H_DABRX_KERNEL (1ULL<<(63-62)) 362 #define H_DABRX_USER (1ULL<<(63-63)) 363 364 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 365 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 366 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 367 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 368 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 369 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 370 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 371 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 372 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 373 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 374 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 375 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 376 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 377 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 378 379 /* Each control block has to be on a 4K boundary */ 380 #define H_CB_ALIGNMENT 4096 381 382 /* pSeries hypervisor opcodes */ 383 #define H_REMOVE 0x04 384 #define H_ENTER 0x08 385 #define H_READ 0x0c 386 #define H_CLEAR_MOD 0x10 387 #define H_CLEAR_REF 0x14 388 #define H_PROTECT 0x18 389 #define H_GET_TCE 0x1c 390 #define H_PUT_TCE 0x20 391 #define H_SET_SPRG0 0x24 392 #define H_SET_DABR 0x28 393 #define H_PAGE_INIT 0x2c 394 #define H_SET_ASR 0x30 395 #define H_ASR_ON 0x34 396 #define H_ASR_OFF 0x38 397 #define H_LOGICAL_CI_LOAD 0x3c 398 #define H_LOGICAL_CI_STORE 0x40 399 #define H_LOGICAL_CACHE_LOAD 0x44 400 #define H_LOGICAL_CACHE_STORE 0x48 401 #define H_LOGICAL_ICBI 0x4c 402 #define H_LOGICAL_DCBF 0x50 403 #define H_GET_TERM_CHAR 0x54 404 #define H_PUT_TERM_CHAR 0x58 405 #define H_REAL_TO_LOGICAL 0x5c 406 #define H_HYPERVISOR_DATA 0x60 407 #define H_EOI 0x64 408 #define H_CPPR 0x68 409 #define H_IPI 0x6c 410 #define H_IPOLL 0x70 411 #define H_XIRR 0x74 412 #define H_PERFMON 0x7c 413 #define H_MIGRATE_DMA 0x78 414 #define H_REGISTER_VPA 0xDC 415 #define H_CEDE 0xE0 416 #define H_CONFER 0xE4 417 #define H_PROD 0xE8 418 #define H_GET_PPP 0xEC 419 #define H_SET_PPP 0xF0 420 #define H_PURR 0xF4 421 #define H_PIC 0xF8 422 #define H_REG_CRQ 0xFC 423 #define H_FREE_CRQ 0x100 424 #define H_VIO_SIGNAL 0x104 425 #define H_SEND_CRQ 0x108 426 #define H_COPY_RDMA 0x110 427 #define H_REGISTER_LOGICAL_LAN 0x114 428 #define H_FREE_LOGICAL_LAN 0x118 429 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 430 #define H_SEND_LOGICAL_LAN 0x120 431 #define H_BULK_REMOVE 0x124 432 #define H_MULTICAST_CTRL 0x130 433 #define H_SET_XDABR 0x134 434 #define H_STUFF_TCE 0x138 435 #define H_PUT_TCE_INDIRECT 0x13C 436 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 437 #define H_VTERM_PARTNER_INFO 0x150 438 #define H_REGISTER_VTERM 0x154 439 #define H_FREE_VTERM 0x158 440 #define H_RESET_EVENTS 0x15C 441 #define H_ALLOC_RESOURCE 0x160 442 #define H_FREE_RESOURCE 0x164 443 #define H_MODIFY_QP 0x168 444 #define H_QUERY_QP 0x16C 445 #define H_REREGISTER_PMR 0x170 446 #define H_REGISTER_SMR 0x174 447 #define H_QUERY_MR 0x178 448 #define H_QUERY_MW 0x17C 449 #define H_QUERY_HCA 0x180 450 #define H_QUERY_PORT 0x184 451 #define H_MODIFY_PORT 0x188 452 #define H_DEFINE_AQP1 0x18C 453 #define H_GET_TRACE_BUFFER 0x190 454 #define H_DEFINE_AQP0 0x194 455 #define H_RESIZE_MR 0x198 456 #define H_ATTACH_MCQP 0x19C 457 #define H_DETACH_MCQP 0x1A0 458 #define H_CREATE_RPT 0x1A4 459 #define H_REMOVE_RPT 0x1A8 460 #define H_REGISTER_RPAGES 0x1AC 461 #define H_DISABLE_AND_GETC 0x1B0 462 #define H_ERROR_DATA 0x1B4 463 #define H_GET_HCA_INFO 0x1B8 464 #define H_GET_PERF_COUNT 0x1BC 465 #define H_MANAGE_TRACE 0x1C0 466 #define H_GET_CPU_CHARACTERISTICS 0x1C8 467 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 468 #define H_QUERY_INT_STATE 0x1E4 469 #define H_POLL_PENDING 0x1D8 470 #define H_ILLAN_ATTRIBUTES 0x244 471 #define H_MODIFY_HEA_QP 0x250 472 #define H_QUERY_HEA_QP 0x254 473 #define H_QUERY_HEA 0x258 474 #define H_QUERY_HEA_PORT 0x25C 475 #define H_MODIFY_HEA_PORT 0x260 476 #define H_REG_BCMC 0x264 477 #define H_DEREG_BCMC 0x268 478 #define H_REGISTER_HEA_RPAGES 0x26C 479 #define H_DISABLE_AND_GET_HEA 0x270 480 #define H_GET_HEA_INFO 0x274 481 #define H_ALLOC_HEA_RESOURCE 0x278 482 #define H_ADD_CONN 0x284 483 #define H_DEL_CONN 0x288 484 #define H_JOIN 0x298 485 #define H_VASI_STATE 0x2A4 486 #define H_ENABLE_CRQ 0x2B0 487 #define H_GET_EM_PARMS 0x2B8 488 #define H_SET_MPP 0x2D0 489 #define H_GET_MPP 0x2D4 490 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 491 #define H_XIRR_X 0x2FC 492 #define H_RANDOM 0x300 493 #define H_SET_MODE 0x31C 494 #define H_RESIZE_HPT_PREPARE 0x36C 495 #define H_RESIZE_HPT_COMMIT 0x370 496 #define H_CLEAN_SLB 0x374 497 #define H_INVALIDATE_PID 0x378 498 #define H_REGISTER_PROC_TBL 0x37C 499 #define H_SIGNAL_SYS_RESET 0x380 500 501 #define H_INT_GET_SOURCE_INFO 0x3A8 502 #define H_INT_SET_SOURCE_CONFIG 0x3AC 503 #define H_INT_GET_SOURCE_CONFIG 0x3B0 504 #define H_INT_GET_QUEUE_INFO 0x3B4 505 #define H_INT_SET_QUEUE_CONFIG 0x3B8 506 #define H_INT_GET_QUEUE_CONFIG 0x3BC 507 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 508 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 509 #define H_INT_ESB 0x3C8 510 #define H_INT_SYNC 0x3CC 511 #define H_INT_RESET 0x3D0 512 #define H_SCM_READ_METADATA 0x3E4 513 #define H_SCM_WRITE_METADATA 0x3E8 514 #define H_SCM_BIND_MEM 0x3EC 515 #define H_SCM_UNBIND_MEM 0x3F0 516 #define H_SCM_UNBIND_ALL 0x3FC 517 518 #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL 519 520 /* The hcalls above are standardized in PAPR and implemented by pHyp 521 * as well. 522 * 523 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 524 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 525 * for "platform-specific" hcalls. 526 */ 527 #define KVMPPC_HCALL_BASE 0xf000 528 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 529 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 530 /* Client Architecture support */ 531 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 532 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 533 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 534 535 /* 536 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 537 * Secure VM mode via an Ultravisor / Protected Execution Facility 538 */ 539 #define SVM_HCALL_BASE 0xEF00 540 #define SVM_H_TPM_COMM 0xEF10 541 #define SVM_HCALL_MAX SVM_H_TPM_COMM 542 543 544 typedef struct SpaprDeviceTreeUpdateHeader { 545 uint32_t version_id; 546 } SpaprDeviceTreeUpdateHeader; 547 548 #define hcall_dprintf(fmt, ...) \ 549 do { \ 550 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 551 } while (0) 552 553 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 554 target_ulong opcode, 555 target_ulong *args); 556 557 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 558 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 559 target_ulong *args); 560 561 /* Virtual Processor Area structure constants */ 562 #define VPA_MIN_SIZE 640 563 #define VPA_SIZE_OFFSET 0x4 564 #define VPA_SHARED_PROC_OFFSET 0x9 565 #define VPA_SHARED_PROC_VAL 0x2 566 #define VPA_DISPATCH_COUNTER 0x100 567 568 /* ibm,set-eeh-option */ 569 #define RTAS_EEH_DISABLE 0 570 #define RTAS_EEH_ENABLE 1 571 #define RTAS_EEH_THAW_IO 2 572 #define RTAS_EEH_THAW_DMA 3 573 574 /* ibm,get-config-addr-info2 */ 575 #define RTAS_GET_PE_ADDR 0 576 #define RTAS_GET_PE_MODE 1 577 #define RTAS_PE_MODE_NONE 0 578 #define RTAS_PE_MODE_NOT_SHARED 1 579 #define RTAS_PE_MODE_SHARED 2 580 581 /* ibm,read-slot-reset-state2 */ 582 #define RTAS_EEH_PE_STATE_NORMAL 0 583 #define RTAS_EEH_PE_STATE_RESET 1 584 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 585 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 586 #define RTAS_EEH_PE_STATE_UNAVAIL 5 587 #define RTAS_EEH_NOT_SUPPORT 0 588 #define RTAS_EEH_SUPPORT 1 589 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 590 #define RTAS_EEH_PE_RECOVER_INFO 0 591 592 /* ibm,set-slot-reset */ 593 #define RTAS_SLOT_RESET_DEACTIVATE 0 594 #define RTAS_SLOT_RESET_HOT 1 595 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 596 597 /* ibm,slot-error-detail */ 598 #define RTAS_SLOT_TEMP_ERR_LOG 1 599 #define RTAS_SLOT_PERM_ERR_LOG 2 600 601 /* RTAS return codes */ 602 #define RTAS_OUT_SUCCESS 0 603 #define RTAS_OUT_NO_ERRORS_FOUND 1 604 #define RTAS_OUT_HW_ERROR -1 605 #define RTAS_OUT_BUSY -2 606 #define RTAS_OUT_PARAM_ERROR -3 607 #define RTAS_OUT_NOT_SUPPORTED -3 608 #define RTAS_OUT_NO_SUCH_INDICATOR -3 609 #define RTAS_OUT_NOT_AUTHORIZED -9002 610 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 611 612 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 613 #define RTAS_DDW_PGSIZE_4K 0x01 614 #define RTAS_DDW_PGSIZE_64K 0x02 615 #define RTAS_DDW_PGSIZE_16M 0x04 616 #define RTAS_DDW_PGSIZE_32M 0x08 617 #define RTAS_DDW_PGSIZE_64M 0x10 618 #define RTAS_DDW_PGSIZE_128M 0x20 619 #define RTAS_DDW_PGSIZE_256M 0x40 620 #define RTAS_DDW_PGSIZE_16G 0x80 621 622 /* RTAS tokens */ 623 #define RTAS_TOKEN_BASE 0x2000 624 625 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 626 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 627 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 628 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 629 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 630 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 631 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 632 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 633 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 634 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 635 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 636 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 637 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 638 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 639 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 640 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 641 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 642 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 643 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 644 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 645 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 646 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 647 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 648 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 649 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 650 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 651 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 652 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 653 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 654 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 655 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 656 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 657 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 658 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 659 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 660 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 661 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 662 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 663 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 664 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 665 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 666 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 667 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 668 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 669 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 670 671 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 672 673 /* RTAS ibm,get-system-parameter token values */ 674 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 675 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 676 #define RTAS_SYSPARM_UUID 48 677 678 /* RTAS indicator/sensor types 679 * 680 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 681 * 682 * NOTE: currently only DR-related sensors are implemented here 683 */ 684 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 685 #define RTAS_SENSOR_TYPE_DR 9002 686 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 687 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 688 689 /* Possible values for the platform-processor-diagnostics-run-mode parameter 690 * of the RTAS ibm,get-system-parameter call. 691 */ 692 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 693 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 694 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 695 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 696 697 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 698 { 699 return addr & ~0xF000000000000000ULL; 700 } 701 702 static inline uint32_t rtas_ld(target_ulong phys, int n) 703 { 704 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 705 } 706 707 static inline uint64_t rtas_ldq(target_ulong phys, int n) 708 { 709 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 710 } 711 712 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 713 { 714 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 715 } 716 717 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 718 uint32_t token, 719 uint32_t nargs, target_ulong args, 720 uint32_t nret, target_ulong rets); 721 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 722 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 723 uint32_t token, uint32_t nargs, target_ulong args, 724 uint32_t nret, target_ulong rets); 725 void spapr_dt_rtas_tokens(void *fdt, int rtas); 726 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 727 728 #define SPAPR_TCE_PAGE_SHIFT 12 729 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 730 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 731 732 #define SPAPR_VIO_BASE_LIOBN 0x00000000 733 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 734 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 735 (0x80000000 | ((phb_index) << 8) | (window_num)) 736 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 737 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 738 739 #define RTAS_ERROR_LOG_MAX 2048 740 741 /* Offset from rtas-base where error log is placed */ 742 #define RTAS_ERROR_LOG_OFFSET 0x30 743 744 #define RTAS_EVENT_SCAN_RATE 1 745 746 /* This helper should be used to encode interrupt specifiers when the related 747 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 748 * VIO devices, RTAS event sources and PHBs). 749 */ 750 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 751 { 752 intspec[0] = cpu_to_be32(irq); 753 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 754 } 755 756 typedef struct SpaprTceTable SpaprTceTable; 757 758 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 759 #define SPAPR_TCE_TABLE(obj) \ 760 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 761 762 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 763 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 764 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 765 766 struct SpaprTceTable { 767 DeviceState parent; 768 uint32_t liobn; 769 uint32_t nb_table; 770 uint64_t bus_offset; 771 uint32_t page_shift; 772 uint64_t *table; 773 uint32_t mig_nb_table; 774 uint64_t *mig_table; 775 bool bypass; 776 bool need_vfio; 777 bool skipping_replay; 778 int fd; 779 MemoryRegion root; 780 IOMMUMemoryRegion iommu; 781 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 782 QLIST_ENTRY(SpaprTceTable) list; 783 }; 784 785 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 786 787 struct SpaprEventLogEntry { 788 uint32_t summary; 789 uint32_t extended_length; 790 void *extended_log; 791 QTAILQ_ENTRY(SpaprEventLogEntry) next; 792 }; 793 794 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 795 void spapr_events_init(SpaprMachineState *sm); 796 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 797 void close_htab_fd(SpaprMachineState *spapr); 798 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr); 799 void spapr_free_hpt(SpaprMachineState *spapr); 800 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 801 void spapr_tce_table_enable(SpaprTceTable *tcet, 802 uint32_t page_shift, uint64_t bus_offset, 803 uint32_t nb_table); 804 void spapr_tce_table_disable(SpaprTceTable *tcet); 805 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 806 807 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 808 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 809 uint32_t liobn, uint64_t window, uint32_t size); 810 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 811 SpaprTceTable *tcet); 812 void spapr_pci_switch_vga(bool big_endian); 813 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 814 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 815 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 816 uint32_t count); 817 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 818 uint32_t count); 819 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 820 uint32_t count, uint32_t index); 821 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 822 uint32_t count, uint32_t index); 823 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 824 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 825 Error **errp); 826 void spapr_clear_pending_events(SpaprMachineState *spapr); 827 int spapr_max_server_number(SpaprMachineState *spapr); 828 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 829 uint64_t pte0, uint64_t pte1); 830 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 831 832 /* DRC callbacks. */ 833 void spapr_core_release(DeviceState *dev); 834 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 835 void *fdt, int *fdt_start_offset, Error **errp); 836 void spapr_lmb_release(DeviceState *dev); 837 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 838 void *fdt, int *fdt_start_offset, Error **errp); 839 void spapr_phb_release(DeviceState *dev); 840 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 841 void *fdt, int *fdt_start_offset, Error **errp); 842 843 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 844 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 845 846 #define TYPE_SPAPR_RNG "spapr-rng" 847 848 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 849 850 /* 851 * This defines the maximum number of DIMM slots we can have for sPAPR 852 * guest. This is not defined by sPAPR but we are defining it to 32 slots 853 * based on default number of slots provided by PowerPC kernel. 854 */ 855 #define SPAPR_MAX_RAM_SLOTS 32 856 857 /* 1GB alignment for hotplug memory region */ 858 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 859 860 /* 861 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 862 * property under ibm,dynamic-reconfiguration-memory node. 863 */ 864 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 865 866 /* 867 * Defines for flag value in ibm,dynamic-memory property under 868 * ibm,dynamic-reconfiguration-memory node. 869 */ 870 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 871 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 872 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 873 874 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 875 876 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 877 878 int spapr_get_vcpu_id(PowerPCCPU *cpu); 879 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 880 PowerPCCPU *spapr_find_cpu(int vcpu_id); 881 882 int spapr_caps_pre_load(void *opaque); 883 int spapr_caps_pre_save(void *opaque); 884 885 /* 886 * Handling of optional capabilities 887 */ 888 extern const VMStateDescription vmstate_spapr_cap_htm; 889 extern const VMStateDescription vmstate_spapr_cap_vsx; 890 extern const VMStateDescription vmstate_spapr_cap_dfp; 891 extern const VMStateDescription vmstate_spapr_cap_cfpc; 892 extern const VMStateDescription vmstate_spapr_cap_sbbc; 893 extern const VMStateDescription vmstate_spapr_cap_ibs; 894 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 895 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 896 extern const VMStateDescription vmstate_spapr_cap_large_decr; 897 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 898 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 899 900 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 901 { 902 return spapr->eff.caps[cap]; 903 } 904 905 void spapr_caps_init(SpaprMachineState *spapr); 906 void spapr_caps_apply(SpaprMachineState *spapr); 907 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 908 void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp); 909 int spapr_caps_post_migration(SpaprMachineState *spapr); 910 911 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 912 Error **errp); 913 /* 914 * XIVE definitions 915 */ 916 #define SPAPR_OV5_XIVE_LEGACY 0x0 917 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 918 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 919 920 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 921 hwaddr spapr_get_rtas_addr(void); 922 #endif /* HW_SPAPR_H */ 923