1 #if !defined(__HW_SPAPR_H__) 2 #define __HW_SPAPR_H__ 3 4 #include "sysemu/dma.h" 5 #include "hw/ppc/xics.h" 6 7 struct VIOsPAPRBus; 8 struct sPAPRPHBState; 9 struct sPAPRNVRAM; 10 11 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 12 13 typedef struct sPAPREnvironment { 14 struct VIOsPAPRBus *vio_bus; 15 QLIST_HEAD(, sPAPRPHBState) phbs; 16 hwaddr msi_win_addr; 17 MemoryRegion msiwindow; 18 struct sPAPRNVRAM *nvram; 19 XICSState *icp; 20 21 hwaddr ram_limit; 22 void *htab; 23 uint32_t htab_shift; 24 hwaddr rma_size; 25 int vrma_adjust; 26 hwaddr fdt_addr, rtas_addr; 27 long rtas_size; 28 void *fdt_skel; 29 target_ulong entry_point; 30 uint32_t next_irq; 31 uint64_t rtc_offset; 32 char *cpu_model; 33 bool has_graphics; 34 35 uint32_t epow_irq; 36 Notifier epow_notifier; 37 38 /* Migration state */ 39 int htab_save_index; 40 bool htab_first_pass; 41 int htab_fd; 42 } sPAPREnvironment; 43 44 #define H_SUCCESS 0 45 #define H_BUSY 1 /* Hardware busy -- retry later */ 46 #define H_CLOSED 2 /* Resource closed */ 47 #define H_NOT_AVAILABLE 3 48 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 49 #define H_PARTIAL 5 50 #define H_IN_PROGRESS 14 /* Kind of like busy */ 51 #define H_PAGE_REGISTERED 15 52 #define H_PARTIAL_STORE 16 53 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 54 #define H_CONTINUE 18 /* Returned from H_Join on success */ 55 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 56 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 57 is a good time to retry */ 58 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 59 is a good time to retry */ 60 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 61 is a good time to retry */ 62 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 63 is a good time to retry */ 64 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 65 is a good time to retry */ 66 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 67 is a good time to retry */ 68 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 69 #define H_HARDWARE -1 /* Hardware error */ 70 #define H_FUNCTION -2 /* Function not supported */ 71 #define H_PRIVILEGE -3 /* Caller not privileged */ 72 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 73 #define H_BAD_MODE -5 /* Illegal msr value */ 74 #define H_PTEG_FULL -6 /* PTEG is full */ 75 #define H_NOT_FOUND -7 /* PTE was not found" */ 76 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 77 #define H_NO_MEM -9 78 #define H_AUTHORITY -10 79 #define H_PERMISSION -11 80 #define H_DROPPED -12 81 #define H_SOURCE_PARM -13 82 #define H_DEST_PARM -14 83 #define H_REMOTE_PARM -15 84 #define H_RESOURCE -16 85 #define H_ADAPTER_PARM -17 86 #define H_RH_PARM -18 87 #define H_RCQ_PARM -19 88 #define H_SCQ_PARM -20 89 #define H_EQ_PARM -21 90 #define H_RT_PARM -22 91 #define H_ST_PARM -23 92 #define H_SIGT_PARM -24 93 #define H_TOKEN_PARM -25 94 #define H_MLENGTH_PARM -27 95 #define H_MEM_PARM -28 96 #define H_MEM_ACCESS_PARM -29 97 #define H_ATTR_PARM -30 98 #define H_PORT_PARM -31 99 #define H_MCG_PARM -32 100 #define H_VL_PARM -33 101 #define H_TSIZE_PARM -34 102 #define H_TRACE_PARM -35 103 104 #define H_MASK_PARM -37 105 #define H_MCG_FULL -38 106 #define H_ALIAS_EXIST -39 107 #define H_P_COUNTER -40 108 #define H_TABLE_FULL -41 109 #define H_ALT_TABLE -42 110 #define H_MR_CONDITION -43 111 #define H_NOT_ENOUGH_RESOURCES -44 112 #define H_R_STATE -45 113 #define H_RESCINDEND -46 114 #define H_P2 -55 115 #define H_P3 -56 116 #define H_P4 -57 117 #define H_P5 -58 118 #define H_P6 -59 119 #define H_P7 -60 120 #define H_P8 -61 121 #define H_P9 -62 122 #define H_UNSUPPORTED_FLAG -256 123 #define H_MULTI_THREADS_ACTIVE -9005 124 125 126 /* Long Busy is a condition that can be returned by the firmware 127 * when a call cannot be completed now, but the identical call 128 * should be retried later. This prevents calls blocking in the 129 * firmware for long periods of time. Annoyingly the firmware can return 130 * a range of return codes, hinting at how long we should wait before 131 * retrying. If you don't care for the hint, the macro below is a good 132 * way to check for the long_busy return codes 133 */ 134 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 135 && (x <= H_LONG_BUSY_END_RANGE)) 136 137 /* Flags */ 138 #define H_LARGE_PAGE (1ULL<<(63-16)) 139 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 140 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 141 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 142 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 143 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 144 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 145 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 146 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 147 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 148 #define H_ANDCOND (1ULL<<(63-33)) 149 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 150 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 151 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 152 #define H_COPY_PAGE (1ULL<<(63-49)) 153 #define H_N (1ULL<<(63-61)) 154 #define H_PP1 (1ULL<<(63-62)) 155 #define H_PP2 (1ULL<<(63-63)) 156 157 /* H_SET_MODE flags */ 158 #define H_SET_MODE_ENDIAN 4 159 #define H_SET_MODE_ENDIAN_BIG 0 160 #define H_SET_MODE_ENDIAN_LITTLE 1 161 162 /* VASI States */ 163 #define H_VASI_INVALID 0 164 #define H_VASI_ENABLED 1 165 #define H_VASI_ABORTED 2 166 #define H_VASI_SUSPENDING 3 167 #define H_VASI_SUSPENDED 4 168 #define H_VASI_RESUMED 5 169 #define H_VASI_COMPLETED 6 170 171 /* DABRX flags */ 172 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 173 #define H_DABRX_KERNEL (1ULL<<(63-62)) 174 #define H_DABRX_USER (1ULL<<(63-63)) 175 176 /* Each control block has to be on a 4K boundary */ 177 #define H_CB_ALIGNMENT 4096 178 179 /* pSeries hypervisor opcodes */ 180 #define H_REMOVE 0x04 181 #define H_ENTER 0x08 182 #define H_READ 0x0c 183 #define H_CLEAR_MOD 0x10 184 #define H_CLEAR_REF 0x14 185 #define H_PROTECT 0x18 186 #define H_GET_TCE 0x1c 187 #define H_PUT_TCE 0x20 188 #define H_SET_SPRG0 0x24 189 #define H_SET_DABR 0x28 190 #define H_PAGE_INIT 0x2c 191 #define H_SET_ASR 0x30 192 #define H_ASR_ON 0x34 193 #define H_ASR_OFF 0x38 194 #define H_LOGICAL_CI_LOAD 0x3c 195 #define H_LOGICAL_CI_STORE 0x40 196 #define H_LOGICAL_CACHE_LOAD 0x44 197 #define H_LOGICAL_CACHE_STORE 0x48 198 #define H_LOGICAL_ICBI 0x4c 199 #define H_LOGICAL_DCBF 0x50 200 #define H_GET_TERM_CHAR 0x54 201 #define H_PUT_TERM_CHAR 0x58 202 #define H_REAL_TO_LOGICAL 0x5c 203 #define H_HYPERVISOR_DATA 0x60 204 #define H_EOI 0x64 205 #define H_CPPR 0x68 206 #define H_IPI 0x6c 207 #define H_IPOLL 0x70 208 #define H_XIRR 0x74 209 #define H_PERFMON 0x7c 210 #define H_MIGRATE_DMA 0x78 211 #define H_REGISTER_VPA 0xDC 212 #define H_CEDE 0xE0 213 #define H_CONFER 0xE4 214 #define H_PROD 0xE8 215 #define H_GET_PPP 0xEC 216 #define H_SET_PPP 0xF0 217 #define H_PURR 0xF4 218 #define H_PIC 0xF8 219 #define H_REG_CRQ 0xFC 220 #define H_FREE_CRQ 0x100 221 #define H_VIO_SIGNAL 0x104 222 #define H_SEND_CRQ 0x108 223 #define H_COPY_RDMA 0x110 224 #define H_REGISTER_LOGICAL_LAN 0x114 225 #define H_FREE_LOGICAL_LAN 0x118 226 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 227 #define H_SEND_LOGICAL_LAN 0x120 228 #define H_BULK_REMOVE 0x124 229 #define H_MULTICAST_CTRL 0x130 230 #define H_SET_XDABR 0x134 231 #define H_STUFF_TCE 0x138 232 #define H_PUT_TCE_INDIRECT 0x13C 233 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 234 #define H_VTERM_PARTNER_INFO 0x150 235 #define H_REGISTER_VTERM 0x154 236 #define H_FREE_VTERM 0x158 237 #define H_RESET_EVENTS 0x15C 238 #define H_ALLOC_RESOURCE 0x160 239 #define H_FREE_RESOURCE 0x164 240 #define H_MODIFY_QP 0x168 241 #define H_QUERY_QP 0x16C 242 #define H_REREGISTER_PMR 0x170 243 #define H_REGISTER_SMR 0x174 244 #define H_QUERY_MR 0x178 245 #define H_QUERY_MW 0x17C 246 #define H_QUERY_HCA 0x180 247 #define H_QUERY_PORT 0x184 248 #define H_MODIFY_PORT 0x188 249 #define H_DEFINE_AQP1 0x18C 250 #define H_GET_TRACE_BUFFER 0x190 251 #define H_DEFINE_AQP0 0x194 252 #define H_RESIZE_MR 0x198 253 #define H_ATTACH_MCQP 0x19C 254 #define H_DETACH_MCQP 0x1A0 255 #define H_CREATE_RPT 0x1A4 256 #define H_REMOVE_RPT 0x1A8 257 #define H_REGISTER_RPAGES 0x1AC 258 #define H_DISABLE_AND_GETC 0x1B0 259 #define H_ERROR_DATA 0x1B4 260 #define H_GET_HCA_INFO 0x1B8 261 #define H_GET_PERF_COUNT 0x1BC 262 #define H_MANAGE_TRACE 0x1C0 263 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 264 #define H_QUERY_INT_STATE 0x1E4 265 #define H_POLL_PENDING 0x1D8 266 #define H_ILLAN_ATTRIBUTES 0x244 267 #define H_MODIFY_HEA_QP 0x250 268 #define H_QUERY_HEA_QP 0x254 269 #define H_QUERY_HEA 0x258 270 #define H_QUERY_HEA_PORT 0x25C 271 #define H_MODIFY_HEA_PORT 0x260 272 #define H_REG_BCMC 0x264 273 #define H_DEREG_BCMC 0x268 274 #define H_REGISTER_HEA_RPAGES 0x26C 275 #define H_DISABLE_AND_GET_HEA 0x270 276 #define H_GET_HEA_INFO 0x274 277 #define H_ALLOC_HEA_RESOURCE 0x278 278 #define H_ADD_CONN 0x284 279 #define H_DEL_CONN 0x288 280 #define H_JOIN 0x298 281 #define H_VASI_STATE 0x2A4 282 #define H_ENABLE_CRQ 0x2B0 283 #define H_GET_EM_PARMS 0x2B8 284 #define H_SET_MPP 0x2D0 285 #define H_GET_MPP 0x2D4 286 #define H_SET_MODE 0x31C 287 #define MAX_HCALL_OPCODE H_SET_MODE 288 289 /* The hcalls above are standardized in PAPR and implemented by pHyp 290 * as well. 291 * 292 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 293 * So far we just need one for H_RTAS, but in future we'll need more 294 * for extensions like virtio. We put those into the 0xf000-0xfffc 295 * range which is reserved by PAPR for "platform-specific" hcalls. 296 */ 297 #define KVMPPC_HCALL_BASE 0xf000 298 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 299 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 300 #define KVMPPC_HCALL_MAX KVMPPC_H_LOGICAL_MEMOP 301 302 extern sPAPREnvironment *spapr; 303 304 /*#define DEBUG_SPAPR_HCALLS*/ 305 306 #ifdef DEBUG_SPAPR_HCALLS 307 #define hcall_dprintf(fmt, ...) \ 308 do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0) 309 #else 310 #define hcall_dprintf(fmt, ...) \ 311 do { } while (0) 312 #endif 313 314 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 315 target_ulong opcode, 316 target_ulong *args); 317 318 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 319 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 320 target_ulong *args); 321 322 int spapr_allocate_irq(int hint, bool lsi); 323 int spapr_allocate_irq_block(int num, bool lsi, bool msi); 324 325 static inline int spapr_allocate_msi(int hint) 326 { 327 return spapr_allocate_irq(hint, false); 328 } 329 330 static inline int spapr_allocate_lsi(int hint) 331 { 332 return spapr_allocate_irq(hint, true); 333 } 334 335 static inline uint32_t rtas_ld(target_ulong phys, int n) 336 { 337 return ldl_be_phys(phys + 4*n); 338 } 339 340 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 341 { 342 stl_be_phys(phys + 4*n, val); 343 } 344 345 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 346 uint32_t token, 347 uint32_t nargs, target_ulong args, 348 uint32_t nret, target_ulong rets); 349 int spapr_rtas_register(const char *name, spapr_rtas_fn fn); 350 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr, 351 uint32_t token, uint32_t nargs, target_ulong args, 352 uint32_t nret, target_ulong rets); 353 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 354 hwaddr rtas_size); 355 356 #define SPAPR_TCE_PAGE_SHIFT 12 357 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 358 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 359 360 #define SPAPR_VIO_BASE_LIOBN 0x00000000 361 #define SPAPR_PCI_BASE_LIOBN 0x80000000 362 363 #define RTAS_ERROR_LOG_MAX 2048 364 365 typedef struct sPAPRTCETable sPAPRTCETable; 366 367 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 368 #define SPAPR_TCE_TABLE(obj) \ 369 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 370 371 struct sPAPRTCETable { 372 DeviceState parent; 373 uint32_t liobn; 374 uint32_t window_size; 375 uint32_t nb_table; 376 uint64_t *table; 377 bool bypass; 378 int fd; 379 MemoryRegion iommu; 380 QLIST_ENTRY(sPAPRTCETable) list; 381 }; 382 383 void spapr_events_init(sPAPREnvironment *spapr); 384 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 385 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, 386 size_t window_size); 387 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 388 void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass); 389 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 390 uint32_t liobn, uint64_t window, uint32_t size); 391 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 392 sPAPRTCETable *tcet); 393 394 #endif /* !defined (__HW_SPAPR_H__) */ 395