1 #if !defined(__HW_SPAPR_H__) 2 #define __HW_SPAPR_H__ 3 4 #include "sysemu/dma.h" 5 #include "hw/ppc/xics.h" 6 7 struct VIOsPAPRBus; 8 struct sPAPRPHBState; 9 struct sPAPRNVRAM; 10 11 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 12 13 typedef struct sPAPREnvironment { 14 struct VIOsPAPRBus *vio_bus; 15 QLIST_HEAD(, sPAPRPHBState) phbs; 16 hwaddr msi_win_addr; 17 MemoryRegion msiwindow; 18 struct sPAPRNVRAM *nvram; 19 XICSState *icp; 20 21 hwaddr ram_limit; 22 void *htab; 23 uint32_t htab_shift; 24 hwaddr rma_size; 25 int vrma_adjust; 26 hwaddr fdt_addr, rtas_addr; 27 long rtas_size; 28 void *fdt_skel; 29 target_ulong entry_point; 30 uint32_t next_irq; 31 uint64_t rtc_offset; 32 bool has_graphics; 33 34 uint32_t epow_irq; 35 Notifier epow_notifier; 36 37 /* Migration state */ 38 int htab_save_index; 39 bool htab_first_pass; 40 int htab_fd; 41 } sPAPREnvironment; 42 43 #define H_SUCCESS 0 44 #define H_BUSY 1 /* Hardware busy -- retry later */ 45 #define H_CLOSED 2 /* Resource closed */ 46 #define H_NOT_AVAILABLE 3 47 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 48 #define H_PARTIAL 5 49 #define H_IN_PROGRESS 14 /* Kind of like busy */ 50 #define H_PAGE_REGISTERED 15 51 #define H_PARTIAL_STORE 16 52 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 53 #define H_CONTINUE 18 /* Returned from H_Join on success */ 54 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 55 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 56 is a good time to retry */ 57 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 58 is a good time to retry */ 59 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 60 is a good time to retry */ 61 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 62 is a good time to retry */ 63 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 64 is a good time to retry */ 65 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 66 is a good time to retry */ 67 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 68 #define H_HARDWARE -1 /* Hardware error */ 69 #define H_FUNCTION -2 /* Function not supported */ 70 #define H_PRIVILEGE -3 /* Caller not privileged */ 71 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 72 #define H_BAD_MODE -5 /* Illegal msr value */ 73 #define H_PTEG_FULL -6 /* PTEG is full */ 74 #define H_NOT_FOUND -7 /* PTE was not found" */ 75 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 76 #define H_NO_MEM -9 77 #define H_AUTHORITY -10 78 #define H_PERMISSION -11 79 #define H_DROPPED -12 80 #define H_SOURCE_PARM -13 81 #define H_DEST_PARM -14 82 #define H_REMOTE_PARM -15 83 #define H_RESOURCE -16 84 #define H_ADAPTER_PARM -17 85 #define H_RH_PARM -18 86 #define H_RCQ_PARM -19 87 #define H_SCQ_PARM -20 88 #define H_EQ_PARM -21 89 #define H_RT_PARM -22 90 #define H_ST_PARM -23 91 #define H_SIGT_PARM -24 92 #define H_TOKEN_PARM -25 93 #define H_MLENGTH_PARM -27 94 #define H_MEM_PARM -28 95 #define H_MEM_ACCESS_PARM -29 96 #define H_ATTR_PARM -30 97 #define H_PORT_PARM -31 98 #define H_MCG_PARM -32 99 #define H_VL_PARM -33 100 #define H_TSIZE_PARM -34 101 #define H_TRACE_PARM -35 102 103 #define H_MASK_PARM -37 104 #define H_MCG_FULL -38 105 #define H_ALIAS_EXIST -39 106 #define H_P_COUNTER -40 107 #define H_TABLE_FULL -41 108 #define H_ALT_TABLE -42 109 #define H_MR_CONDITION -43 110 #define H_NOT_ENOUGH_RESOURCES -44 111 #define H_R_STATE -45 112 #define H_RESCINDEND -46 113 #define H_P2 -55 114 #define H_P3 -56 115 #define H_P4 -57 116 #define H_P5 -58 117 #define H_P6 -59 118 #define H_P7 -60 119 #define H_P8 -61 120 #define H_P9 -62 121 #define H_UNSUPPORTED_FLAG -256 122 #define H_MULTI_THREADS_ACTIVE -9005 123 124 125 /* Long Busy is a condition that can be returned by the firmware 126 * when a call cannot be completed now, but the identical call 127 * should be retried later. This prevents calls blocking in the 128 * firmware for long periods of time. Annoyingly the firmware can return 129 * a range of return codes, hinting at how long we should wait before 130 * retrying. If you don't care for the hint, the macro below is a good 131 * way to check for the long_busy return codes 132 */ 133 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 134 && (x <= H_LONG_BUSY_END_RANGE)) 135 136 /* Flags */ 137 #define H_LARGE_PAGE (1ULL<<(63-16)) 138 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 139 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 140 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 141 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 142 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 143 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 144 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 145 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 146 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 147 #define H_ANDCOND (1ULL<<(63-33)) 148 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 149 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 150 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 151 #define H_COPY_PAGE (1ULL<<(63-49)) 152 #define H_N (1ULL<<(63-61)) 153 #define H_PP1 (1ULL<<(63-62)) 154 #define H_PP2 (1ULL<<(63-63)) 155 156 /* Values for 2nd argument to H_SET_MODE */ 157 #define H_SET_MODE_RESOURCE_SET_CIABR 1 158 #define H_SET_MODE_RESOURCE_SET_DAWR 2 159 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 160 #define H_SET_MODE_RESOURCE_LE 4 161 162 /* Flags for H_SET_MODE_RESOURCE_LE */ 163 #define H_SET_MODE_ENDIAN_BIG 0 164 #define H_SET_MODE_ENDIAN_LITTLE 1 165 166 /* VASI States */ 167 #define H_VASI_INVALID 0 168 #define H_VASI_ENABLED 1 169 #define H_VASI_ABORTED 2 170 #define H_VASI_SUSPENDING 3 171 #define H_VASI_SUSPENDED 4 172 #define H_VASI_RESUMED 5 173 #define H_VASI_COMPLETED 6 174 175 /* DABRX flags */ 176 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 177 #define H_DABRX_KERNEL (1ULL<<(63-62)) 178 #define H_DABRX_USER (1ULL<<(63-63)) 179 180 /* Each control block has to be on a 4K boundary */ 181 #define H_CB_ALIGNMENT 4096 182 183 /* pSeries hypervisor opcodes */ 184 #define H_REMOVE 0x04 185 #define H_ENTER 0x08 186 #define H_READ 0x0c 187 #define H_CLEAR_MOD 0x10 188 #define H_CLEAR_REF 0x14 189 #define H_PROTECT 0x18 190 #define H_GET_TCE 0x1c 191 #define H_PUT_TCE 0x20 192 #define H_SET_SPRG0 0x24 193 #define H_SET_DABR 0x28 194 #define H_PAGE_INIT 0x2c 195 #define H_SET_ASR 0x30 196 #define H_ASR_ON 0x34 197 #define H_ASR_OFF 0x38 198 #define H_LOGICAL_CI_LOAD 0x3c 199 #define H_LOGICAL_CI_STORE 0x40 200 #define H_LOGICAL_CACHE_LOAD 0x44 201 #define H_LOGICAL_CACHE_STORE 0x48 202 #define H_LOGICAL_ICBI 0x4c 203 #define H_LOGICAL_DCBF 0x50 204 #define H_GET_TERM_CHAR 0x54 205 #define H_PUT_TERM_CHAR 0x58 206 #define H_REAL_TO_LOGICAL 0x5c 207 #define H_HYPERVISOR_DATA 0x60 208 #define H_EOI 0x64 209 #define H_CPPR 0x68 210 #define H_IPI 0x6c 211 #define H_IPOLL 0x70 212 #define H_XIRR 0x74 213 #define H_PERFMON 0x7c 214 #define H_MIGRATE_DMA 0x78 215 #define H_REGISTER_VPA 0xDC 216 #define H_CEDE 0xE0 217 #define H_CONFER 0xE4 218 #define H_PROD 0xE8 219 #define H_GET_PPP 0xEC 220 #define H_SET_PPP 0xF0 221 #define H_PURR 0xF4 222 #define H_PIC 0xF8 223 #define H_REG_CRQ 0xFC 224 #define H_FREE_CRQ 0x100 225 #define H_VIO_SIGNAL 0x104 226 #define H_SEND_CRQ 0x108 227 #define H_COPY_RDMA 0x110 228 #define H_REGISTER_LOGICAL_LAN 0x114 229 #define H_FREE_LOGICAL_LAN 0x118 230 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 231 #define H_SEND_LOGICAL_LAN 0x120 232 #define H_BULK_REMOVE 0x124 233 #define H_MULTICAST_CTRL 0x130 234 #define H_SET_XDABR 0x134 235 #define H_STUFF_TCE 0x138 236 #define H_PUT_TCE_INDIRECT 0x13C 237 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 238 #define H_VTERM_PARTNER_INFO 0x150 239 #define H_REGISTER_VTERM 0x154 240 #define H_FREE_VTERM 0x158 241 #define H_RESET_EVENTS 0x15C 242 #define H_ALLOC_RESOURCE 0x160 243 #define H_FREE_RESOURCE 0x164 244 #define H_MODIFY_QP 0x168 245 #define H_QUERY_QP 0x16C 246 #define H_REREGISTER_PMR 0x170 247 #define H_REGISTER_SMR 0x174 248 #define H_QUERY_MR 0x178 249 #define H_QUERY_MW 0x17C 250 #define H_QUERY_HCA 0x180 251 #define H_QUERY_PORT 0x184 252 #define H_MODIFY_PORT 0x188 253 #define H_DEFINE_AQP1 0x18C 254 #define H_GET_TRACE_BUFFER 0x190 255 #define H_DEFINE_AQP0 0x194 256 #define H_RESIZE_MR 0x198 257 #define H_ATTACH_MCQP 0x19C 258 #define H_DETACH_MCQP 0x1A0 259 #define H_CREATE_RPT 0x1A4 260 #define H_REMOVE_RPT 0x1A8 261 #define H_REGISTER_RPAGES 0x1AC 262 #define H_DISABLE_AND_GETC 0x1B0 263 #define H_ERROR_DATA 0x1B4 264 #define H_GET_HCA_INFO 0x1B8 265 #define H_GET_PERF_COUNT 0x1BC 266 #define H_MANAGE_TRACE 0x1C0 267 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 268 #define H_QUERY_INT_STATE 0x1E4 269 #define H_POLL_PENDING 0x1D8 270 #define H_ILLAN_ATTRIBUTES 0x244 271 #define H_MODIFY_HEA_QP 0x250 272 #define H_QUERY_HEA_QP 0x254 273 #define H_QUERY_HEA 0x258 274 #define H_QUERY_HEA_PORT 0x25C 275 #define H_MODIFY_HEA_PORT 0x260 276 #define H_REG_BCMC 0x264 277 #define H_DEREG_BCMC 0x268 278 #define H_REGISTER_HEA_RPAGES 0x26C 279 #define H_DISABLE_AND_GET_HEA 0x270 280 #define H_GET_HEA_INFO 0x274 281 #define H_ALLOC_HEA_RESOURCE 0x278 282 #define H_ADD_CONN 0x284 283 #define H_DEL_CONN 0x288 284 #define H_JOIN 0x298 285 #define H_VASI_STATE 0x2A4 286 #define H_ENABLE_CRQ 0x2B0 287 #define H_GET_EM_PARMS 0x2B8 288 #define H_SET_MPP 0x2D0 289 #define H_GET_MPP 0x2D4 290 #define H_XIRR_X 0x2FC 291 #define H_SET_MODE 0x31C 292 #define MAX_HCALL_OPCODE H_SET_MODE 293 294 /* The hcalls above are standardized in PAPR and implemented by pHyp 295 * as well. 296 * 297 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 298 * So far we just need one for H_RTAS, but in future we'll need more 299 * for extensions like virtio. We put those into the 0xf000-0xfffc 300 * range which is reserved by PAPR for "platform-specific" hcalls. 301 */ 302 #define KVMPPC_HCALL_BASE 0xf000 303 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 304 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 305 #define KVMPPC_HCALL_MAX KVMPPC_H_LOGICAL_MEMOP 306 307 extern sPAPREnvironment *spapr; 308 309 /*#define DEBUG_SPAPR_HCALLS*/ 310 311 #ifdef DEBUG_SPAPR_HCALLS 312 #define hcall_dprintf(fmt, ...) \ 313 do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0) 314 #else 315 #define hcall_dprintf(fmt, ...) \ 316 do { } while (0) 317 #endif 318 319 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 320 target_ulong opcode, 321 target_ulong *args); 322 323 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 324 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 325 target_ulong *args); 326 327 int spapr_allocate_irq(int hint, bool lsi); 328 int spapr_allocate_irq_block(int num, bool lsi, bool msi); 329 330 static inline int spapr_allocate_msi(int hint) 331 { 332 return spapr_allocate_irq(hint, false); 333 } 334 335 static inline int spapr_allocate_lsi(int hint) 336 { 337 return spapr_allocate_irq(hint, true); 338 } 339 340 /* RTAS return codes */ 341 #define RTAS_OUT_SUCCESS 0 342 #define RTAS_OUT_NO_ERRORS_FOUND 1 343 #define RTAS_OUT_HW_ERROR -1 344 #define RTAS_OUT_BUSY -2 345 #define RTAS_OUT_PARAM_ERROR -3 346 #define RTAS_OUT_NOT_SUPPORTED -3 347 #define RTAS_OUT_NOT_AUTHORIZED -9002 348 349 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 350 { 351 return addr & ~0xF000000000000000ULL; 352 } 353 354 static inline uint32_t rtas_ld(target_ulong phys, int n) 355 { 356 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 357 } 358 359 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 360 { 361 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 362 } 363 364 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 365 uint32_t token, 366 uint32_t nargs, target_ulong args, 367 uint32_t nret, target_ulong rets); 368 int spapr_rtas_register(const char *name, spapr_rtas_fn fn); 369 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr, 370 uint32_t token, uint32_t nargs, target_ulong args, 371 uint32_t nret, target_ulong rets); 372 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 373 hwaddr rtas_size); 374 375 #define SPAPR_TCE_PAGE_SHIFT 12 376 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 377 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 378 379 #define SPAPR_VIO_BASE_LIOBN 0x00000000 380 #define SPAPR_PCI_BASE_LIOBN 0x80000000 381 382 #define RTAS_ERROR_LOG_MAX 2048 383 384 typedef struct sPAPRTCETable sPAPRTCETable; 385 386 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 387 #define SPAPR_TCE_TABLE(obj) \ 388 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 389 390 struct sPAPRTCETable { 391 DeviceState parent; 392 uint32_t liobn; 393 uint32_t window_size; 394 uint32_t nb_table; 395 uint64_t *table; 396 bool bypass; 397 int fd; 398 MemoryRegion iommu; 399 QLIST_ENTRY(sPAPRTCETable) list; 400 }; 401 402 void spapr_events_init(sPAPREnvironment *spapr); 403 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 404 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, 405 size_t window_size); 406 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 407 void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass); 408 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 409 uint32_t liobn, uint64_t window, uint32_t size); 410 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 411 sPAPRTCETable *tcet); 412 413 #endif /* !defined (__HW_SPAPR_H__) */ 414