1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 12 struct VIOsPAPRBus; 13 struct sPAPRPHBState; 14 struct sPAPRNVRAM; 15 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 16 typedef struct sPAPREventSource sPAPREventSource; 17 typedef struct sPAPRPendingHPT sPAPRPendingHPT; 18 typedef struct ICSState ICSState; 19 typedef struct sPAPRXive sPAPRXive; 20 21 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 22 #define SPAPR_ENTRY_POINT 0x100 23 24 #define SPAPR_TIMEBASE_FREQ 512000000ULL 25 26 #define TYPE_SPAPR_RTC "spapr-rtc" 27 28 #define SPAPR_RTC(obj) \ 29 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 30 31 typedef struct sPAPRRTCState sPAPRRTCState; 32 struct sPAPRRTCState { 33 /*< private >*/ 34 DeviceState parent_obj; 35 int64_t ns_offset; 36 }; 37 38 typedef struct sPAPRDIMMState sPAPRDIMMState; 39 typedef struct sPAPRMachineClass sPAPRMachineClass; 40 41 #define TYPE_SPAPR_MACHINE "spapr-machine" 42 #define SPAPR_MACHINE(obj) \ 43 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 44 #define SPAPR_MACHINE_GET_CLASS(obj) \ 45 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 46 #define SPAPR_MACHINE_CLASS(klass) \ 47 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 48 49 typedef enum { 50 SPAPR_RESIZE_HPT_DEFAULT = 0, 51 SPAPR_RESIZE_HPT_DISABLED, 52 SPAPR_RESIZE_HPT_ENABLED, 53 SPAPR_RESIZE_HPT_REQUIRED, 54 } sPAPRResizeHPT; 55 56 /** 57 * Capabilities 58 */ 59 60 /* Hardware Transactional Memory */ 61 #define SPAPR_CAP_HTM 0x00 62 /* Vector Scalar Extensions */ 63 #define SPAPR_CAP_VSX 0x01 64 /* Decimal Floating Point */ 65 #define SPAPR_CAP_DFP 0x02 66 /* Cache Flush on Privilege Change */ 67 #define SPAPR_CAP_CFPC 0x03 68 /* Speculation Barrier Bounds Checking */ 69 #define SPAPR_CAP_SBBC 0x04 70 /* Indirect Branch Serialisation */ 71 #define SPAPR_CAP_IBS 0x05 72 /* HPT Maximum Page Size (encoded as a shift) */ 73 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 74 /* Nested KVM-HV */ 75 #define SPAPR_CAP_NESTED_KVM_HV 0x07 76 /* Num Caps */ 77 #define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_KVM_HV + 1) 78 79 /* 80 * Capability Values 81 */ 82 /* Bool Caps */ 83 #define SPAPR_CAP_OFF 0x00 84 #define SPAPR_CAP_ON 0x01 85 /* Custom Caps */ 86 #define SPAPR_CAP_BROKEN 0x00 87 #define SPAPR_CAP_WORKAROUND 0x01 88 #define SPAPR_CAP_FIXED 0x02 89 #define SPAPR_CAP_FIXED_IBS 0x02 90 #define SPAPR_CAP_FIXED_CCD 0x03 91 92 typedef struct sPAPRCapabilities sPAPRCapabilities; 93 struct sPAPRCapabilities { 94 uint8_t caps[SPAPR_CAP_NUM]; 95 }; 96 97 /** 98 * sPAPRMachineClass: 99 */ 100 struct sPAPRMachineClass { 101 /*< private >*/ 102 MachineClass parent_class; 103 104 /*< public >*/ 105 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 106 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 107 bool pre_2_10_has_unused_icps; 108 bool legacy_irq_allocation; 109 110 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 111 uint64_t *buid, hwaddr *pio, 112 hwaddr *mmio32, hwaddr *mmio64, 113 unsigned n_dma, uint32_t *liobns, Error **errp); 114 sPAPRResizeHPT resize_hpt_default; 115 sPAPRCapabilities default_caps; 116 sPAPRIrq *irq; 117 }; 118 119 /** 120 * sPAPRMachineState: 121 */ 122 struct sPAPRMachineState { 123 /*< private >*/ 124 MachineState parent_obj; 125 126 struct VIOsPAPRBus *vio_bus; 127 QLIST_HEAD(, sPAPRPHBState) phbs; 128 struct sPAPRNVRAM *nvram; 129 ICSState *ics; 130 sPAPRRTCState rtc; 131 132 sPAPRResizeHPT resize_hpt; 133 void *htab; 134 uint32_t htab_shift; 135 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 136 sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 137 138 hwaddr rma_size; 139 int vrma_adjust; 140 ssize_t rtas_size; 141 void *rtas_blob; 142 long kernel_size; 143 bool kernel_le; 144 uint32_t initrd_base; 145 long initrd_size; 146 uint64_t rtc_offset; /* Now used only during incoming migration */ 147 struct PPCTimebase tb; 148 bool has_graphics; 149 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 150 151 Notifier epow_notifier; 152 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 153 bool use_hotplug_event_source; 154 sPAPREventSource *event_sources; 155 156 /* ibm,client-architecture-support option negotiation */ 157 bool cas_reboot; 158 bool cas_legacy_guest_workaround; 159 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 160 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 161 uint32_t max_compat_pvr; 162 163 /* Migration state */ 164 int htab_save_index; 165 bool htab_first_pass; 166 int htab_fd; 167 168 /* Pending DIMM unplug cache. It is populated when a LMB 169 * unplug starts. It can be regenerated if a migration 170 * occurs during the unplug process. */ 171 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 172 173 /*< public >*/ 174 char *kvm_type; 175 176 const char *icp_type; 177 int32_t irq_map_nr; 178 unsigned long *irq_map; 179 sPAPRXive *xive; 180 sPAPRIrq *irq; 181 182 bool cmd_line_caps[SPAPR_CAP_NUM]; 183 sPAPRCapabilities def, eff, mig; 184 }; 185 186 #define H_SUCCESS 0 187 #define H_BUSY 1 /* Hardware busy -- retry later */ 188 #define H_CLOSED 2 /* Resource closed */ 189 #define H_NOT_AVAILABLE 3 190 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 191 #define H_PARTIAL 5 192 #define H_IN_PROGRESS 14 /* Kind of like busy */ 193 #define H_PAGE_REGISTERED 15 194 #define H_PARTIAL_STORE 16 195 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 196 #define H_CONTINUE 18 /* Returned from H_Join on success */ 197 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 198 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 199 is a good time to retry */ 200 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 201 is a good time to retry */ 202 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 203 is a good time to retry */ 204 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 205 is a good time to retry */ 206 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 207 is a good time to retry */ 208 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 209 is a good time to retry */ 210 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 211 #define H_HARDWARE -1 /* Hardware error */ 212 #define H_FUNCTION -2 /* Function not supported */ 213 #define H_PRIVILEGE -3 /* Caller not privileged */ 214 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 215 #define H_BAD_MODE -5 /* Illegal msr value */ 216 #define H_PTEG_FULL -6 /* PTEG is full */ 217 #define H_NOT_FOUND -7 /* PTE was not found" */ 218 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 219 #define H_NO_MEM -9 220 #define H_AUTHORITY -10 221 #define H_PERMISSION -11 222 #define H_DROPPED -12 223 #define H_SOURCE_PARM -13 224 #define H_DEST_PARM -14 225 #define H_REMOTE_PARM -15 226 #define H_RESOURCE -16 227 #define H_ADAPTER_PARM -17 228 #define H_RH_PARM -18 229 #define H_RCQ_PARM -19 230 #define H_SCQ_PARM -20 231 #define H_EQ_PARM -21 232 #define H_RT_PARM -22 233 #define H_ST_PARM -23 234 #define H_SIGT_PARM -24 235 #define H_TOKEN_PARM -25 236 #define H_MLENGTH_PARM -27 237 #define H_MEM_PARM -28 238 #define H_MEM_ACCESS_PARM -29 239 #define H_ATTR_PARM -30 240 #define H_PORT_PARM -31 241 #define H_MCG_PARM -32 242 #define H_VL_PARM -33 243 #define H_TSIZE_PARM -34 244 #define H_TRACE_PARM -35 245 246 #define H_MASK_PARM -37 247 #define H_MCG_FULL -38 248 #define H_ALIAS_EXIST -39 249 #define H_P_COUNTER -40 250 #define H_TABLE_FULL -41 251 #define H_ALT_TABLE -42 252 #define H_MR_CONDITION -43 253 #define H_NOT_ENOUGH_RESOURCES -44 254 #define H_R_STATE -45 255 #define H_RESCINDEND -46 256 #define H_P2 -55 257 #define H_P3 -56 258 #define H_P4 -57 259 #define H_P5 -58 260 #define H_P6 -59 261 #define H_P7 -60 262 #define H_P8 -61 263 #define H_P9 -62 264 #define H_UNSUPPORTED_FLAG -256 265 #define H_MULTI_THREADS_ACTIVE -9005 266 267 268 /* Long Busy is a condition that can be returned by the firmware 269 * when a call cannot be completed now, but the identical call 270 * should be retried later. This prevents calls blocking in the 271 * firmware for long periods of time. Annoyingly the firmware can return 272 * a range of return codes, hinting at how long we should wait before 273 * retrying. If you don't care for the hint, the macro below is a good 274 * way to check for the long_busy return codes 275 */ 276 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 277 && (x <= H_LONG_BUSY_END_RANGE)) 278 279 /* Flags */ 280 #define H_LARGE_PAGE (1ULL<<(63-16)) 281 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 282 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 283 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 284 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 285 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 286 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 287 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 288 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 289 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 290 #define H_ANDCOND (1ULL<<(63-33)) 291 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 292 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 293 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 294 #define H_COPY_PAGE (1ULL<<(63-49)) 295 #define H_N (1ULL<<(63-61)) 296 #define H_PP1 (1ULL<<(63-62)) 297 #define H_PP2 (1ULL<<(63-63)) 298 299 /* Values for 2nd argument to H_SET_MODE */ 300 #define H_SET_MODE_RESOURCE_SET_CIABR 1 301 #define H_SET_MODE_RESOURCE_SET_DAWR 2 302 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 303 #define H_SET_MODE_RESOURCE_LE 4 304 305 /* Flags for H_SET_MODE_RESOURCE_LE */ 306 #define H_SET_MODE_ENDIAN_BIG 0 307 #define H_SET_MODE_ENDIAN_LITTLE 1 308 309 /* VASI States */ 310 #define H_VASI_INVALID 0 311 #define H_VASI_ENABLED 1 312 #define H_VASI_ABORTED 2 313 #define H_VASI_SUSPENDING 3 314 #define H_VASI_SUSPENDED 4 315 #define H_VASI_RESUMED 5 316 #define H_VASI_COMPLETED 6 317 318 /* DABRX flags */ 319 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 320 #define H_DABRX_KERNEL (1ULL<<(63-62)) 321 #define H_DABRX_USER (1ULL<<(63-63)) 322 323 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 324 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 325 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 326 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 327 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 328 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 329 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 330 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 331 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 332 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 333 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 334 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 335 336 /* Each control block has to be on a 4K boundary */ 337 #define H_CB_ALIGNMENT 4096 338 339 /* pSeries hypervisor opcodes */ 340 #define H_REMOVE 0x04 341 #define H_ENTER 0x08 342 #define H_READ 0x0c 343 #define H_CLEAR_MOD 0x10 344 #define H_CLEAR_REF 0x14 345 #define H_PROTECT 0x18 346 #define H_GET_TCE 0x1c 347 #define H_PUT_TCE 0x20 348 #define H_SET_SPRG0 0x24 349 #define H_SET_DABR 0x28 350 #define H_PAGE_INIT 0x2c 351 #define H_SET_ASR 0x30 352 #define H_ASR_ON 0x34 353 #define H_ASR_OFF 0x38 354 #define H_LOGICAL_CI_LOAD 0x3c 355 #define H_LOGICAL_CI_STORE 0x40 356 #define H_LOGICAL_CACHE_LOAD 0x44 357 #define H_LOGICAL_CACHE_STORE 0x48 358 #define H_LOGICAL_ICBI 0x4c 359 #define H_LOGICAL_DCBF 0x50 360 #define H_GET_TERM_CHAR 0x54 361 #define H_PUT_TERM_CHAR 0x58 362 #define H_REAL_TO_LOGICAL 0x5c 363 #define H_HYPERVISOR_DATA 0x60 364 #define H_EOI 0x64 365 #define H_CPPR 0x68 366 #define H_IPI 0x6c 367 #define H_IPOLL 0x70 368 #define H_XIRR 0x74 369 #define H_PERFMON 0x7c 370 #define H_MIGRATE_DMA 0x78 371 #define H_REGISTER_VPA 0xDC 372 #define H_CEDE 0xE0 373 #define H_CONFER 0xE4 374 #define H_PROD 0xE8 375 #define H_GET_PPP 0xEC 376 #define H_SET_PPP 0xF0 377 #define H_PURR 0xF4 378 #define H_PIC 0xF8 379 #define H_REG_CRQ 0xFC 380 #define H_FREE_CRQ 0x100 381 #define H_VIO_SIGNAL 0x104 382 #define H_SEND_CRQ 0x108 383 #define H_COPY_RDMA 0x110 384 #define H_REGISTER_LOGICAL_LAN 0x114 385 #define H_FREE_LOGICAL_LAN 0x118 386 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 387 #define H_SEND_LOGICAL_LAN 0x120 388 #define H_BULK_REMOVE 0x124 389 #define H_MULTICAST_CTRL 0x130 390 #define H_SET_XDABR 0x134 391 #define H_STUFF_TCE 0x138 392 #define H_PUT_TCE_INDIRECT 0x13C 393 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 394 #define H_VTERM_PARTNER_INFO 0x150 395 #define H_REGISTER_VTERM 0x154 396 #define H_FREE_VTERM 0x158 397 #define H_RESET_EVENTS 0x15C 398 #define H_ALLOC_RESOURCE 0x160 399 #define H_FREE_RESOURCE 0x164 400 #define H_MODIFY_QP 0x168 401 #define H_QUERY_QP 0x16C 402 #define H_REREGISTER_PMR 0x170 403 #define H_REGISTER_SMR 0x174 404 #define H_QUERY_MR 0x178 405 #define H_QUERY_MW 0x17C 406 #define H_QUERY_HCA 0x180 407 #define H_QUERY_PORT 0x184 408 #define H_MODIFY_PORT 0x188 409 #define H_DEFINE_AQP1 0x18C 410 #define H_GET_TRACE_BUFFER 0x190 411 #define H_DEFINE_AQP0 0x194 412 #define H_RESIZE_MR 0x198 413 #define H_ATTACH_MCQP 0x19C 414 #define H_DETACH_MCQP 0x1A0 415 #define H_CREATE_RPT 0x1A4 416 #define H_REMOVE_RPT 0x1A8 417 #define H_REGISTER_RPAGES 0x1AC 418 #define H_DISABLE_AND_GETC 0x1B0 419 #define H_ERROR_DATA 0x1B4 420 #define H_GET_HCA_INFO 0x1B8 421 #define H_GET_PERF_COUNT 0x1BC 422 #define H_MANAGE_TRACE 0x1C0 423 #define H_GET_CPU_CHARACTERISTICS 0x1C8 424 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 425 #define H_QUERY_INT_STATE 0x1E4 426 #define H_POLL_PENDING 0x1D8 427 #define H_ILLAN_ATTRIBUTES 0x244 428 #define H_MODIFY_HEA_QP 0x250 429 #define H_QUERY_HEA_QP 0x254 430 #define H_QUERY_HEA 0x258 431 #define H_QUERY_HEA_PORT 0x25C 432 #define H_MODIFY_HEA_PORT 0x260 433 #define H_REG_BCMC 0x264 434 #define H_DEREG_BCMC 0x268 435 #define H_REGISTER_HEA_RPAGES 0x26C 436 #define H_DISABLE_AND_GET_HEA 0x270 437 #define H_GET_HEA_INFO 0x274 438 #define H_ALLOC_HEA_RESOURCE 0x278 439 #define H_ADD_CONN 0x284 440 #define H_DEL_CONN 0x288 441 #define H_JOIN 0x298 442 #define H_VASI_STATE 0x2A4 443 #define H_ENABLE_CRQ 0x2B0 444 #define H_GET_EM_PARMS 0x2B8 445 #define H_SET_MPP 0x2D0 446 #define H_GET_MPP 0x2D4 447 #define H_XIRR_X 0x2FC 448 #define H_RANDOM 0x300 449 #define H_SET_MODE 0x31C 450 #define H_RESIZE_HPT_PREPARE 0x36C 451 #define H_RESIZE_HPT_COMMIT 0x370 452 #define H_CLEAN_SLB 0x374 453 #define H_INVALIDATE_PID 0x378 454 #define H_REGISTER_PROC_TBL 0x37C 455 #define H_SIGNAL_SYS_RESET 0x380 456 457 #define H_INT_GET_SOURCE_INFO 0x3A8 458 #define H_INT_SET_SOURCE_CONFIG 0x3AC 459 #define H_INT_GET_SOURCE_CONFIG 0x3B0 460 #define H_INT_GET_QUEUE_INFO 0x3B4 461 #define H_INT_SET_QUEUE_CONFIG 0x3B8 462 #define H_INT_GET_QUEUE_CONFIG 0x3BC 463 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 464 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 465 #define H_INT_ESB 0x3C8 466 #define H_INT_SYNC 0x3CC 467 #define H_INT_RESET 0x3D0 468 469 #define MAX_HCALL_OPCODE H_INT_RESET 470 471 /* The hcalls above are standardized in PAPR and implemented by pHyp 472 * as well. 473 * 474 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 475 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 476 * for "platform-specific" hcalls. 477 */ 478 #define KVMPPC_HCALL_BASE 0xf000 479 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 480 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 481 /* Client Architecture support */ 482 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 483 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 484 485 typedef struct sPAPRDeviceTreeUpdateHeader { 486 uint32_t version_id; 487 } sPAPRDeviceTreeUpdateHeader; 488 489 #define hcall_dprintf(fmt, ...) \ 490 do { \ 491 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 492 } while (0) 493 494 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 495 target_ulong opcode, 496 target_ulong *args); 497 498 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 499 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 500 target_ulong *args); 501 502 /* ibm,set-eeh-option */ 503 #define RTAS_EEH_DISABLE 0 504 #define RTAS_EEH_ENABLE 1 505 #define RTAS_EEH_THAW_IO 2 506 #define RTAS_EEH_THAW_DMA 3 507 508 /* ibm,get-config-addr-info2 */ 509 #define RTAS_GET_PE_ADDR 0 510 #define RTAS_GET_PE_MODE 1 511 #define RTAS_PE_MODE_NONE 0 512 #define RTAS_PE_MODE_NOT_SHARED 1 513 #define RTAS_PE_MODE_SHARED 2 514 515 /* ibm,read-slot-reset-state2 */ 516 #define RTAS_EEH_PE_STATE_NORMAL 0 517 #define RTAS_EEH_PE_STATE_RESET 1 518 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 519 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 520 #define RTAS_EEH_PE_STATE_UNAVAIL 5 521 #define RTAS_EEH_NOT_SUPPORT 0 522 #define RTAS_EEH_SUPPORT 1 523 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 524 #define RTAS_EEH_PE_RECOVER_INFO 0 525 526 /* ibm,set-slot-reset */ 527 #define RTAS_SLOT_RESET_DEACTIVATE 0 528 #define RTAS_SLOT_RESET_HOT 1 529 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 530 531 /* ibm,slot-error-detail */ 532 #define RTAS_SLOT_TEMP_ERR_LOG 1 533 #define RTAS_SLOT_PERM_ERR_LOG 2 534 535 /* RTAS return codes */ 536 #define RTAS_OUT_SUCCESS 0 537 #define RTAS_OUT_NO_ERRORS_FOUND 1 538 #define RTAS_OUT_HW_ERROR -1 539 #define RTAS_OUT_BUSY -2 540 #define RTAS_OUT_PARAM_ERROR -3 541 #define RTAS_OUT_NOT_SUPPORTED -3 542 #define RTAS_OUT_NO_SUCH_INDICATOR -3 543 #define RTAS_OUT_NOT_AUTHORIZED -9002 544 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 545 546 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 547 #define RTAS_DDW_PGSIZE_4K 0x01 548 #define RTAS_DDW_PGSIZE_64K 0x02 549 #define RTAS_DDW_PGSIZE_16M 0x04 550 #define RTAS_DDW_PGSIZE_32M 0x08 551 #define RTAS_DDW_PGSIZE_64M 0x10 552 #define RTAS_DDW_PGSIZE_128M 0x20 553 #define RTAS_DDW_PGSIZE_256M 0x40 554 #define RTAS_DDW_PGSIZE_16G 0x80 555 556 /* RTAS tokens */ 557 #define RTAS_TOKEN_BASE 0x2000 558 559 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 560 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 561 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 562 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 563 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 564 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 565 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 566 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 567 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 568 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 569 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 570 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 571 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 572 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 573 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 574 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 575 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 576 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 577 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 578 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 579 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 580 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 581 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 582 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 583 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 584 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 585 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 586 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 587 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 588 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 589 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 590 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 591 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 592 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 593 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 594 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 595 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 596 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 597 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 598 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 599 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 600 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 601 602 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 603 604 /* RTAS ibm,get-system-parameter token values */ 605 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 606 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 607 #define RTAS_SYSPARM_UUID 48 608 609 /* RTAS indicator/sensor types 610 * 611 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 612 * 613 * NOTE: currently only DR-related sensors are implemented here 614 */ 615 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 616 #define RTAS_SENSOR_TYPE_DR 9002 617 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 618 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 619 620 /* Possible values for the platform-processor-diagnostics-run-mode parameter 621 * of the RTAS ibm,get-system-parameter call. 622 */ 623 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 624 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 625 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 626 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 627 628 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 629 { 630 return addr & ~0xF000000000000000ULL; 631 } 632 633 static inline uint32_t rtas_ld(target_ulong phys, int n) 634 { 635 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 636 } 637 638 static inline uint64_t rtas_ldq(target_ulong phys, int n) 639 { 640 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 641 } 642 643 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 644 { 645 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 646 } 647 648 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 649 uint32_t token, 650 uint32_t nargs, target_ulong args, 651 uint32_t nret, target_ulong rets); 652 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 653 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 654 uint32_t token, uint32_t nargs, target_ulong args, 655 uint32_t nret, target_ulong rets); 656 void spapr_dt_rtas_tokens(void *fdt, int rtas); 657 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 658 659 #define SPAPR_TCE_PAGE_SHIFT 12 660 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 661 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 662 663 #define SPAPR_VIO_BASE_LIOBN 0x00000000 664 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 665 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 666 (0x80000000 | ((phb_index) << 8) | (window_num)) 667 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 668 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 669 670 #define RTAS_ERROR_LOG_MAX 2048 671 672 #define RTAS_EVENT_SCAN_RATE 1 673 674 /* This helper should be used to encode interrupt specifiers when the related 675 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 676 * VIO devices, RTAS event sources and PHBs). 677 */ 678 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi) 679 { 680 intspec[0] = cpu_to_be32(irq); 681 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 682 } 683 684 typedef struct sPAPRTCETable sPAPRTCETable; 685 686 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 687 #define SPAPR_TCE_TABLE(obj) \ 688 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 689 690 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 691 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 692 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 693 694 struct sPAPRTCETable { 695 DeviceState parent; 696 uint32_t liobn; 697 uint32_t nb_table; 698 uint64_t bus_offset; 699 uint32_t page_shift; 700 uint64_t *table; 701 uint32_t mig_nb_table; 702 uint64_t *mig_table; 703 bool bypass; 704 bool need_vfio; 705 int fd; 706 MemoryRegion root; 707 IOMMUMemoryRegion iommu; 708 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 709 QLIST_ENTRY(sPAPRTCETable) list; 710 }; 711 712 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 713 714 struct sPAPREventLogEntry { 715 uint32_t summary; 716 uint32_t extended_length; 717 void *extended_log; 718 QTAILQ_ENTRY(sPAPREventLogEntry) next; 719 }; 720 721 void spapr_events_init(sPAPRMachineState *sm); 722 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 723 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 724 target_ulong addr, target_ulong size, 725 sPAPROptionVector *ov5_updates); 726 void close_htab_fd(sPAPRMachineState *spapr); 727 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 728 void spapr_free_hpt(sPAPRMachineState *spapr); 729 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 730 void spapr_tce_table_enable(sPAPRTCETable *tcet, 731 uint32_t page_shift, uint64_t bus_offset, 732 uint32_t nb_table); 733 void spapr_tce_table_disable(sPAPRTCETable *tcet); 734 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 735 736 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 737 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 738 uint32_t liobn, uint64_t window, uint32_t size); 739 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 740 sPAPRTCETable *tcet); 741 void spapr_pci_switch_vga(bool big_endian); 742 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 743 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 744 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 745 uint32_t count); 746 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 747 uint32_t count); 748 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 749 uint32_t count, uint32_t index); 750 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 751 uint32_t count, uint32_t index); 752 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 753 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 754 Error **errp); 755 void spapr_clear_pending_events(sPAPRMachineState *spapr); 756 int spapr_max_server_number(sPAPRMachineState *spapr); 757 758 /* CPU and LMB DRC release callbacks. */ 759 void spapr_core_release(DeviceState *dev); 760 void spapr_lmb_release(DeviceState *dev); 761 762 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 763 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 764 765 #define TYPE_SPAPR_RNG "spapr-rng" 766 767 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 768 769 /* 770 * This defines the maximum number of DIMM slots we can have for sPAPR 771 * guest. This is not defined by sPAPR but we are defining it to 32 slots 772 * based on default number of slots provided by PowerPC kernel. 773 */ 774 #define SPAPR_MAX_RAM_SLOTS 32 775 776 /* 1GB alignment for hotplug memory region */ 777 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 778 779 /* 780 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 781 * property under ibm,dynamic-reconfiguration-memory node. 782 */ 783 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 784 785 /* 786 * Defines for flag value in ibm,dynamic-memory property under 787 * ibm,dynamic-reconfiguration-memory node. 788 */ 789 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 790 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 791 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 792 793 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 794 795 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 796 797 int spapr_get_vcpu_id(PowerPCCPU *cpu); 798 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 799 PowerPCCPU *spapr_find_cpu(int vcpu_id); 800 801 int spapr_caps_pre_load(void *opaque); 802 int spapr_caps_pre_save(void *opaque); 803 804 /* 805 * Handling of optional capabilities 806 */ 807 extern const VMStateDescription vmstate_spapr_cap_htm; 808 extern const VMStateDescription vmstate_spapr_cap_vsx; 809 extern const VMStateDescription vmstate_spapr_cap_dfp; 810 extern const VMStateDescription vmstate_spapr_cap_cfpc; 811 extern const VMStateDescription vmstate_spapr_cap_sbbc; 812 extern const VMStateDescription vmstate_spapr_cap_ibs; 813 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 814 815 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap) 816 { 817 return spapr->eff.caps[cap]; 818 } 819 820 void spapr_caps_init(sPAPRMachineState *spapr); 821 void spapr_caps_apply(sPAPRMachineState *spapr); 822 void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu); 823 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); 824 int spapr_caps_post_migration(sPAPRMachineState *spapr); 825 826 void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize, 827 Error **errp); 828 /* 829 * XIVE definitions 830 */ 831 #define SPAPR_OV5_XIVE_LEGACY 0x0 832 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 833 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 834 835 #endif /* HW_SPAPR_H */ 836