xref: /openbmc/qemu/include/hw/ppc/spapr.h (revision 438c78da)
1 #ifndef HW_SPAPR_H
2 #define HW_SPAPR_H
3 
4 #include "qemu/units.h"
5 #include "sysemu/dma.h"
6 #include "hw/boards.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
10 #include "hw/ppc/spapr_irq.h"
11 
12 struct VIOsPAPRBus;
13 struct sPAPRPHBState;
14 struct sPAPRNVRAM;
15 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
16 typedef struct sPAPREventSource sPAPREventSource;
17 typedef struct sPAPRPendingHPT sPAPRPendingHPT;
18 typedef struct ICSState ICSState;
19 
20 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
21 #define SPAPR_ENTRY_POINT       0x100
22 
23 #define SPAPR_TIMEBASE_FREQ     512000000ULL
24 
25 #define TYPE_SPAPR_RTC "spapr-rtc"
26 
27 #define SPAPR_RTC(obj)                                  \
28     OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
29 
30 typedef struct sPAPRRTCState sPAPRRTCState;
31 struct sPAPRRTCState {
32     /*< private >*/
33     DeviceState parent_obj;
34     int64_t ns_offset;
35 };
36 
37 typedef struct sPAPRDIMMState sPAPRDIMMState;
38 typedef struct sPAPRMachineClass sPAPRMachineClass;
39 
40 #define TYPE_SPAPR_MACHINE      "spapr-machine"
41 #define SPAPR_MACHINE(obj) \
42     OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
43 #define SPAPR_MACHINE_GET_CLASS(obj) \
44     OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
45 #define SPAPR_MACHINE_CLASS(klass) \
46     OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
47 
48 typedef enum {
49     SPAPR_RESIZE_HPT_DEFAULT = 0,
50     SPAPR_RESIZE_HPT_DISABLED,
51     SPAPR_RESIZE_HPT_ENABLED,
52     SPAPR_RESIZE_HPT_REQUIRED,
53 } sPAPRResizeHPT;
54 
55 /**
56  * Capabilities
57  */
58 
59 /* Hardware Transactional Memory */
60 #define SPAPR_CAP_HTM                   0x00
61 /* Vector Scalar Extensions */
62 #define SPAPR_CAP_VSX                   0x01
63 /* Decimal Floating Point */
64 #define SPAPR_CAP_DFP                   0x02
65 /* Cache Flush on Privilege Change */
66 #define SPAPR_CAP_CFPC                  0x03
67 /* Speculation Barrier Bounds Checking */
68 #define SPAPR_CAP_SBBC                  0x04
69 /* Indirect Branch Serialisation */
70 #define SPAPR_CAP_IBS                   0x05
71 /* HPT Maximum Page Size (encoded as a shift) */
72 #define SPAPR_CAP_HPT_MAXPAGESIZE       0x06
73 /* Num Caps */
74 #define SPAPR_CAP_NUM                   (SPAPR_CAP_HPT_MAXPAGESIZE + 1)
75 
76 /*
77  * Capability Values
78  */
79 /* Bool Caps */
80 #define SPAPR_CAP_OFF                   0x00
81 #define SPAPR_CAP_ON                    0x01
82 /* Custom Caps */
83 #define SPAPR_CAP_BROKEN                0x00
84 #define SPAPR_CAP_WORKAROUND            0x01
85 #define SPAPR_CAP_FIXED                 0x02
86 #define SPAPR_CAP_FIXED_IBS             0x02
87 #define SPAPR_CAP_FIXED_CCD             0x03
88 
89 typedef struct sPAPRCapabilities sPAPRCapabilities;
90 struct sPAPRCapabilities {
91     uint8_t caps[SPAPR_CAP_NUM];
92 };
93 
94 /**
95  * sPAPRMachineClass:
96  */
97 struct sPAPRMachineClass {
98     /*< private >*/
99     MachineClass parent_class;
100 
101     /*< public >*/
102     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
103     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
104     bool pre_2_10_has_unused_icps;
105     bool legacy_irq_allocation;
106 
107     void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
108                           uint64_t *buid, hwaddr *pio,
109                           hwaddr *mmio32, hwaddr *mmio64,
110                           unsigned n_dma, uint32_t *liobns, Error **errp);
111     sPAPRResizeHPT resize_hpt_default;
112     sPAPRCapabilities default_caps;
113     sPAPRIrq *irq;
114 };
115 
116 /**
117  * sPAPRMachineState:
118  */
119 struct sPAPRMachineState {
120     /*< private >*/
121     MachineState parent_obj;
122 
123     struct VIOsPAPRBus *vio_bus;
124     QLIST_HEAD(, sPAPRPHBState) phbs;
125     struct sPAPRNVRAM *nvram;
126     ICSState *ics;
127     sPAPRRTCState rtc;
128 
129     sPAPRResizeHPT resize_hpt;
130     void *htab;
131     uint32_t htab_shift;
132     uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
133     sPAPRPendingHPT *pending_hpt; /* in-progress resize */
134 
135     hwaddr rma_size;
136     int vrma_adjust;
137     ssize_t rtas_size;
138     void *rtas_blob;
139     long kernel_size;
140     bool kernel_le;
141     uint32_t initrd_base;
142     long initrd_size;
143     uint64_t rtc_offset; /* Now used only during incoming migration */
144     struct PPCTimebase tb;
145     bool has_graphics;
146     uint32_t vsmt;       /* Virtual SMT mode (KVM's "core stride") */
147 
148     Notifier epow_notifier;
149     QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
150     bool use_hotplug_event_source;
151     sPAPREventSource *event_sources;
152 
153     /* ibm,client-architecture-support option negotiation */
154     bool cas_reboot;
155     bool cas_legacy_guest_workaround;
156     sPAPROptionVector *ov5;         /* QEMU-supported option vectors */
157     sPAPROptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
158     uint32_t max_compat_pvr;
159 
160     /* Migration state */
161     int htab_save_index;
162     bool htab_first_pass;
163     int htab_fd;
164 
165     /* Pending DIMM unplug cache. It is populated when a LMB
166      * unplug starts. It can be regenerated if a migration
167      * occurs during the unplug process. */
168     QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs;
169 
170     /*< public >*/
171     char *kvm_type;
172 
173     const char *icp_type;
174     int32_t irq_map_nr;
175     unsigned long *irq_map;
176 
177     bool cmd_line_caps[SPAPR_CAP_NUM];
178     sPAPRCapabilities def, eff, mig;
179 };
180 
181 #define H_SUCCESS         0
182 #define H_BUSY            1        /* Hardware busy -- retry later */
183 #define H_CLOSED          2        /* Resource closed */
184 #define H_NOT_AVAILABLE   3
185 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
186 #define H_PARTIAL         5
187 #define H_IN_PROGRESS     14       /* Kind of like busy */
188 #define H_PAGE_REGISTERED 15
189 #define H_PARTIAL_STORE   16
190 #define H_PENDING         17       /* returned from H_POLL_PENDING */
191 #define H_CONTINUE        18       /* Returned from H_Join on success */
192 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
193 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
194                                                  is a good time to retry */
195 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
196                                                  is a good time to retry */
197 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
198                                                  is a good time to retry */
199 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
200                                                  is a good time to retry */
201 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
202                                                  is a good time to retry */
203 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
204                                                  is a good time to retry */
205 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
206 #define H_HARDWARE        -1       /* Hardware error */
207 #define H_FUNCTION        -2       /* Function not supported */
208 #define H_PRIVILEGE       -3       /* Caller not privileged */
209 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
210 #define H_BAD_MODE        -5       /* Illegal msr value */
211 #define H_PTEG_FULL       -6       /* PTEG is full */
212 #define H_NOT_FOUND       -7       /* PTE was not found" */
213 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
214 #define H_NO_MEM          -9
215 #define H_AUTHORITY       -10
216 #define H_PERMISSION      -11
217 #define H_DROPPED         -12
218 #define H_SOURCE_PARM     -13
219 #define H_DEST_PARM       -14
220 #define H_REMOTE_PARM     -15
221 #define H_RESOURCE        -16
222 #define H_ADAPTER_PARM    -17
223 #define H_RH_PARM         -18
224 #define H_RCQ_PARM        -19
225 #define H_SCQ_PARM        -20
226 #define H_EQ_PARM         -21
227 #define H_RT_PARM         -22
228 #define H_ST_PARM         -23
229 #define H_SIGT_PARM       -24
230 #define H_TOKEN_PARM      -25
231 #define H_MLENGTH_PARM    -27
232 #define H_MEM_PARM        -28
233 #define H_MEM_ACCESS_PARM -29
234 #define H_ATTR_PARM       -30
235 #define H_PORT_PARM       -31
236 #define H_MCG_PARM        -32
237 #define H_VL_PARM         -33
238 #define H_TSIZE_PARM      -34
239 #define H_TRACE_PARM      -35
240 
241 #define H_MASK_PARM       -37
242 #define H_MCG_FULL        -38
243 #define H_ALIAS_EXIST     -39
244 #define H_P_COUNTER       -40
245 #define H_TABLE_FULL      -41
246 #define H_ALT_TABLE       -42
247 #define H_MR_CONDITION    -43
248 #define H_NOT_ENOUGH_RESOURCES -44
249 #define H_R_STATE         -45
250 #define H_RESCINDEND      -46
251 #define H_P2              -55
252 #define H_P3              -56
253 #define H_P4              -57
254 #define H_P5              -58
255 #define H_P6              -59
256 #define H_P7              -60
257 #define H_P8              -61
258 #define H_P9              -62
259 #define H_UNSUPPORTED_FLAG -256
260 #define H_MULTI_THREADS_ACTIVE -9005
261 
262 
263 /* Long Busy is a condition that can be returned by the firmware
264  * when a call cannot be completed now, but the identical call
265  * should be retried later.  This prevents calls blocking in the
266  * firmware for long periods of time.  Annoyingly the firmware can return
267  * a range of return codes, hinting at how long we should wait before
268  * retrying.  If you don't care for the hint, the macro below is a good
269  * way to check for the long_busy return codes
270  */
271 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
272                             && (x <= H_LONG_BUSY_END_RANGE))
273 
274 /* Flags */
275 #define H_LARGE_PAGE      (1ULL<<(63-16))
276 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
277 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
278 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
279 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
280 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
281 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
282 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
283 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
284 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
285 #define H_ANDCOND         (1ULL<<(63-33))
286 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
287 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
288 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
289 #define H_COPY_PAGE       (1ULL<<(63-49))
290 #define H_N               (1ULL<<(63-61))
291 #define H_PP1             (1ULL<<(63-62))
292 #define H_PP2             (1ULL<<(63-63))
293 
294 /* Values for 2nd argument to H_SET_MODE */
295 #define H_SET_MODE_RESOURCE_SET_CIABR           1
296 #define H_SET_MODE_RESOURCE_SET_DAWR            2
297 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
298 #define H_SET_MODE_RESOURCE_LE                  4
299 
300 /* Flags for H_SET_MODE_RESOURCE_LE */
301 #define H_SET_MODE_ENDIAN_BIG    0
302 #define H_SET_MODE_ENDIAN_LITTLE 1
303 
304 /* VASI States */
305 #define H_VASI_INVALID    0
306 #define H_VASI_ENABLED    1
307 #define H_VASI_ABORTED    2
308 #define H_VASI_SUSPENDING 3
309 #define H_VASI_SUSPENDED  4
310 #define H_VASI_RESUMED    5
311 #define H_VASI_COMPLETED  6
312 
313 /* DABRX flags */
314 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
315 #define H_DABRX_KERNEL     (1ULL<<(63-62))
316 #define H_DABRX_USER       (1ULL<<(63-63))
317 
318 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
319 #define H_CPU_CHAR_SPEC_BAR_ORI31               PPC_BIT(0)
320 #define H_CPU_CHAR_BCCTRL_SERIALISED            PPC_BIT(1)
321 #define H_CPU_CHAR_L1D_FLUSH_ORI30              PPC_BIT(2)
322 #define H_CPU_CHAR_L1D_FLUSH_TRIG2              PPC_BIT(3)
323 #define H_CPU_CHAR_L1D_THREAD_PRIV              PPC_BIT(4)
324 #define H_CPU_CHAR_HON_BRANCH_HINTS             PPC_BIT(5)
325 #define H_CPU_CHAR_THR_RECONF_TRIG              PPC_BIT(6)
326 #define H_CPU_CHAR_CACHE_COUNT_DIS              PPC_BIT(7)
327 #define H_CPU_BEHAV_FAVOUR_SECURITY             PPC_BIT(0)
328 #define H_CPU_BEHAV_L1D_FLUSH_PR                PPC_BIT(1)
329 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR           PPC_BIT(2)
330 
331 /* Each control block has to be on a 4K boundary */
332 #define H_CB_ALIGNMENT     4096
333 
334 /* pSeries hypervisor opcodes */
335 #define H_REMOVE                0x04
336 #define H_ENTER                 0x08
337 #define H_READ                  0x0c
338 #define H_CLEAR_MOD             0x10
339 #define H_CLEAR_REF             0x14
340 #define H_PROTECT               0x18
341 #define H_GET_TCE               0x1c
342 #define H_PUT_TCE               0x20
343 #define H_SET_SPRG0             0x24
344 #define H_SET_DABR              0x28
345 #define H_PAGE_INIT             0x2c
346 #define H_SET_ASR               0x30
347 #define H_ASR_ON                0x34
348 #define H_ASR_OFF               0x38
349 #define H_LOGICAL_CI_LOAD       0x3c
350 #define H_LOGICAL_CI_STORE      0x40
351 #define H_LOGICAL_CACHE_LOAD    0x44
352 #define H_LOGICAL_CACHE_STORE   0x48
353 #define H_LOGICAL_ICBI          0x4c
354 #define H_LOGICAL_DCBF          0x50
355 #define H_GET_TERM_CHAR         0x54
356 #define H_PUT_TERM_CHAR         0x58
357 #define H_REAL_TO_LOGICAL       0x5c
358 #define H_HYPERVISOR_DATA       0x60
359 #define H_EOI                   0x64
360 #define H_CPPR                  0x68
361 #define H_IPI                   0x6c
362 #define H_IPOLL                 0x70
363 #define H_XIRR                  0x74
364 #define H_PERFMON               0x7c
365 #define H_MIGRATE_DMA           0x78
366 #define H_REGISTER_VPA          0xDC
367 #define H_CEDE                  0xE0
368 #define H_CONFER                0xE4
369 #define H_PROD                  0xE8
370 #define H_GET_PPP               0xEC
371 #define H_SET_PPP               0xF0
372 #define H_PURR                  0xF4
373 #define H_PIC                   0xF8
374 #define H_REG_CRQ               0xFC
375 #define H_FREE_CRQ              0x100
376 #define H_VIO_SIGNAL            0x104
377 #define H_SEND_CRQ              0x108
378 #define H_COPY_RDMA             0x110
379 #define H_REGISTER_LOGICAL_LAN  0x114
380 #define H_FREE_LOGICAL_LAN      0x118
381 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
382 #define H_SEND_LOGICAL_LAN      0x120
383 #define H_BULK_REMOVE           0x124
384 #define H_MULTICAST_CTRL        0x130
385 #define H_SET_XDABR             0x134
386 #define H_STUFF_TCE             0x138
387 #define H_PUT_TCE_INDIRECT      0x13C
388 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
389 #define H_VTERM_PARTNER_INFO    0x150
390 #define H_REGISTER_VTERM        0x154
391 #define H_FREE_VTERM            0x158
392 #define H_RESET_EVENTS          0x15C
393 #define H_ALLOC_RESOURCE        0x160
394 #define H_FREE_RESOURCE         0x164
395 #define H_MODIFY_QP             0x168
396 #define H_QUERY_QP              0x16C
397 #define H_REREGISTER_PMR        0x170
398 #define H_REGISTER_SMR          0x174
399 #define H_QUERY_MR              0x178
400 #define H_QUERY_MW              0x17C
401 #define H_QUERY_HCA             0x180
402 #define H_QUERY_PORT            0x184
403 #define H_MODIFY_PORT           0x188
404 #define H_DEFINE_AQP1           0x18C
405 #define H_GET_TRACE_BUFFER      0x190
406 #define H_DEFINE_AQP0           0x194
407 #define H_RESIZE_MR             0x198
408 #define H_ATTACH_MCQP           0x19C
409 #define H_DETACH_MCQP           0x1A0
410 #define H_CREATE_RPT            0x1A4
411 #define H_REMOVE_RPT            0x1A8
412 #define H_REGISTER_RPAGES       0x1AC
413 #define H_DISABLE_AND_GETC      0x1B0
414 #define H_ERROR_DATA            0x1B4
415 #define H_GET_HCA_INFO          0x1B8
416 #define H_GET_PERF_COUNT        0x1BC
417 #define H_MANAGE_TRACE          0x1C0
418 #define H_GET_CPU_CHARACTERISTICS 0x1C8
419 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
420 #define H_QUERY_INT_STATE       0x1E4
421 #define H_POLL_PENDING          0x1D8
422 #define H_ILLAN_ATTRIBUTES      0x244
423 #define H_MODIFY_HEA_QP         0x250
424 #define H_QUERY_HEA_QP          0x254
425 #define H_QUERY_HEA             0x258
426 #define H_QUERY_HEA_PORT        0x25C
427 #define H_MODIFY_HEA_PORT       0x260
428 #define H_REG_BCMC              0x264
429 #define H_DEREG_BCMC            0x268
430 #define H_REGISTER_HEA_RPAGES   0x26C
431 #define H_DISABLE_AND_GET_HEA   0x270
432 #define H_GET_HEA_INFO          0x274
433 #define H_ALLOC_HEA_RESOURCE    0x278
434 #define H_ADD_CONN              0x284
435 #define H_DEL_CONN              0x288
436 #define H_JOIN                  0x298
437 #define H_VASI_STATE            0x2A4
438 #define H_ENABLE_CRQ            0x2B0
439 #define H_GET_EM_PARMS          0x2B8
440 #define H_SET_MPP               0x2D0
441 #define H_GET_MPP               0x2D4
442 #define H_XIRR_X                0x2FC
443 #define H_RANDOM                0x300
444 #define H_SET_MODE              0x31C
445 #define H_RESIZE_HPT_PREPARE    0x36C
446 #define H_RESIZE_HPT_COMMIT     0x370
447 #define H_CLEAN_SLB             0x374
448 #define H_INVALIDATE_PID        0x378
449 #define H_REGISTER_PROC_TBL     0x37C
450 #define H_SIGNAL_SYS_RESET      0x380
451 #define MAX_HCALL_OPCODE        H_SIGNAL_SYS_RESET
452 
453 /* The hcalls above are standardized in PAPR and implemented by pHyp
454  * as well.
455  *
456  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
457  * We put those into the 0xf000-0xfffc range which is reserved by PAPR
458  * for "platform-specific" hcalls.
459  */
460 #define KVMPPC_HCALL_BASE       0xf000
461 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
462 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
463 /* Client Architecture support */
464 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
465 #define KVMPPC_HCALL_MAX        KVMPPC_H_CAS
466 
467 typedef struct sPAPRDeviceTreeUpdateHeader {
468     uint32_t version_id;
469 } sPAPRDeviceTreeUpdateHeader;
470 
471 #define hcall_dprintf(fmt, ...) \
472     do { \
473         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
474     } while (0)
475 
476 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
477                                        target_ulong opcode,
478                                        target_ulong *args);
479 
480 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
481 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
482                              target_ulong *args);
483 
484 /* ibm,set-eeh-option */
485 #define RTAS_EEH_DISABLE                 0
486 #define RTAS_EEH_ENABLE                  1
487 #define RTAS_EEH_THAW_IO                 2
488 #define RTAS_EEH_THAW_DMA                3
489 
490 /* ibm,get-config-addr-info2 */
491 #define RTAS_GET_PE_ADDR                 0
492 #define RTAS_GET_PE_MODE                 1
493 #define RTAS_PE_MODE_NONE                0
494 #define RTAS_PE_MODE_NOT_SHARED          1
495 #define RTAS_PE_MODE_SHARED              2
496 
497 /* ibm,read-slot-reset-state2 */
498 #define RTAS_EEH_PE_STATE_NORMAL         0
499 #define RTAS_EEH_PE_STATE_RESET          1
500 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
501 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
502 #define RTAS_EEH_PE_STATE_UNAVAIL        5
503 #define RTAS_EEH_NOT_SUPPORT             0
504 #define RTAS_EEH_SUPPORT                 1
505 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
506 #define RTAS_EEH_PE_RECOVER_INFO         0
507 
508 /* ibm,set-slot-reset */
509 #define RTAS_SLOT_RESET_DEACTIVATE       0
510 #define RTAS_SLOT_RESET_HOT              1
511 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
512 
513 /* ibm,slot-error-detail */
514 #define RTAS_SLOT_TEMP_ERR_LOG           1
515 #define RTAS_SLOT_PERM_ERR_LOG           2
516 
517 /* RTAS return codes */
518 #define RTAS_OUT_SUCCESS                        0
519 #define RTAS_OUT_NO_ERRORS_FOUND                1
520 #define RTAS_OUT_HW_ERROR                       -1
521 #define RTAS_OUT_BUSY                           -2
522 #define RTAS_OUT_PARAM_ERROR                    -3
523 #define RTAS_OUT_NOT_SUPPORTED                  -3
524 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
525 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
526 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
527 
528 /* DDW pagesize mask values from ibm,query-pe-dma-window */
529 #define RTAS_DDW_PGSIZE_4K       0x01
530 #define RTAS_DDW_PGSIZE_64K      0x02
531 #define RTAS_DDW_PGSIZE_16M      0x04
532 #define RTAS_DDW_PGSIZE_32M      0x08
533 #define RTAS_DDW_PGSIZE_64M      0x10
534 #define RTAS_DDW_PGSIZE_128M     0x20
535 #define RTAS_DDW_PGSIZE_256M     0x40
536 #define RTAS_DDW_PGSIZE_16G      0x80
537 
538 /* RTAS tokens */
539 #define RTAS_TOKEN_BASE      0x2000
540 
541 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
542 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
543 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
544 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
545 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
546 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
547 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
548 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
549 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
550 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
551 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
552 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
553 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
554 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
555 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
556 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
557 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
558 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
559 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
560 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
561 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
562 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
563 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
564 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
565 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
566 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
567 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
568 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
569 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
570 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
571 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
572 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
573 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
574 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
575 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
576 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
577 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
578 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
579 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
580 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
581 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
582 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
583 
584 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2A)
585 
586 /* RTAS ibm,get-system-parameter token values */
587 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
588 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
589 #define RTAS_SYSPARM_UUID                        48
590 
591 /* RTAS indicator/sensor types
592  *
593  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
594  *
595  * NOTE: currently only DR-related sensors are implemented here
596  */
597 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
598 #define RTAS_SENSOR_TYPE_DR                     9002
599 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
600 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
601 
602 /* Possible values for the platform-processor-diagnostics-run-mode parameter
603  * of the RTAS ibm,get-system-parameter call.
604  */
605 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
606 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
607 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
608 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
609 
610 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
611 {
612     return addr & ~0xF000000000000000ULL;
613 }
614 
615 static inline uint32_t rtas_ld(target_ulong phys, int n)
616 {
617     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
618 }
619 
620 static inline uint64_t rtas_ldq(target_ulong phys, int n)
621 {
622     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
623 }
624 
625 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
626 {
627     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
628 }
629 
630 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
631                               uint32_t token,
632                               uint32_t nargs, target_ulong args,
633                               uint32_t nret, target_ulong rets);
634 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
635 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
636                              uint32_t token, uint32_t nargs, target_ulong args,
637                              uint32_t nret, target_ulong rets);
638 void spapr_dt_rtas_tokens(void *fdt, int rtas);
639 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
640 
641 #define SPAPR_TCE_PAGE_SHIFT   12
642 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
643 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
644 
645 #define SPAPR_VIO_BASE_LIOBN    0x00000000
646 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
647 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
648     (0x80000000 | ((phb_index) << 8) | (window_num))
649 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
650 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
651 
652 #define RTAS_ERROR_LOG_MAX      2048
653 
654 #define RTAS_EVENT_SCAN_RATE    1
655 
656 /* This helper should be used to encode interrupt specifiers when the related
657  * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
658  * VIO devices, RTAS event sources and PHBs).
659  */
660 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi)
661 {
662     intspec[0] = cpu_to_be32(irq);
663     intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
664 }
665 
666 typedef struct sPAPRTCETable sPAPRTCETable;
667 
668 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
669 #define SPAPR_TCE_TABLE(obj) \
670     OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
671 
672 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
673 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
674         OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
675 
676 struct sPAPRTCETable {
677     DeviceState parent;
678     uint32_t liobn;
679     uint32_t nb_table;
680     uint64_t bus_offset;
681     uint32_t page_shift;
682     uint64_t *table;
683     uint32_t mig_nb_table;
684     uint64_t *mig_table;
685     bool bypass;
686     bool need_vfio;
687     int fd;
688     MemoryRegion root;
689     IOMMUMemoryRegion iommu;
690     struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
691     QLIST_ENTRY(sPAPRTCETable) list;
692 };
693 
694 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
695 
696 struct sPAPREventLogEntry {
697     uint32_t summary;
698     uint32_t extended_length;
699     void *extended_log;
700     QTAILQ_ENTRY(sPAPREventLogEntry) next;
701 };
702 
703 void spapr_events_init(sPAPRMachineState *sm);
704 void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
705 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
706                                  target_ulong addr, target_ulong size,
707                                  sPAPROptionVector *ov5_updates);
708 void close_htab_fd(sPAPRMachineState *spapr);
709 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr);
710 void spapr_free_hpt(sPAPRMachineState *spapr);
711 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
712 void spapr_tce_table_enable(sPAPRTCETable *tcet,
713                             uint32_t page_shift, uint64_t bus_offset,
714                             uint32_t nb_table);
715 void spapr_tce_table_disable(sPAPRTCETable *tcet);
716 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
717 
718 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
719 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
720                  uint32_t liobn, uint64_t window, uint32_t size);
721 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
722                       sPAPRTCETable *tcet);
723 void spapr_pci_switch_vga(bool big_endian);
724 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
725 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
726 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
727                                        uint32_t count);
728 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
729                                           uint32_t count);
730 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
731                                             uint32_t count, uint32_t index);
732 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
733                                                uint32_t count, uint32_t index);
734 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
735 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
736                           Error **errp);
737 void spapr_clear_pending_events(sPAPRMachineState *spapr);
738 
739 /* CPU and LMB DRC release callbacks. */
740 void spapr_core_release(DeviceState *dev);
741 void spapr_lmb_release(DeviceState *dev);
742 
743 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns);
744 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
745 
746 #define TYPE_SPAPR_RNG "spapr-rng"
747 
748 int spapr_rng_populate_dt(void *fdt);
749 
750 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
751 
752 /*
753  * This defines the maximum number of DIMM slots we can have for sPAPR
754  * guest. This is not defined by sPAPR but we are defining it to 32 slots
755  * based on default number of slots provided by PowerPC kernel.
756  */
757 #define SPAPR_MAX_RAM_SLOTS     32
758 
759 /* 1GB alignment for hotplug memory region */
760 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
761 
762 /*
763  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
764  * property under ibm,dynamic-reconfiguration-memory node.
765  */
766 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
767 
768 /*
769  * Defines for flag value in ibm,dynamic-memory property under
770  * ibm,dynamic-reconfiguration-memory node.
771  */
772 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
773 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
774 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
775 
776 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
777 
778 #define HTAB_SIZE(spapr)        (1ULL << ((spapr)->htab_shift))
779 
780 int spapr_get_vcpu_id(PowerPCCPU *cpu);
781 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
782 PowerPCCPU *spapr_find_cpu(int vcpu_id);
783 
784 int spapr_caps_pre_load(void *opaque);
785 int spapr_caps_pre_save(void *opaque);
786 
787 /*
788  * Handling of optional capabilities
789  */
790 extern const VMStateDescription vmstate_spapr_cap_htm;
791 extern const VMStateDescription vmstate_spapr_cap_vsx;
792 extern const VMStateDescription vmstate_spapr_cap_dfp;
793 extern const VMStateDescription vmstate_spapr_cap_cfpc;
794 extern const VMStateDescription vmstate_spapr_cap_sbbc;
795 extern const VMStateDescription vmstate_spapr_cap_ibs;
796 
797 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap)
798 {
799     return spapr->eff.caps[cap];
800 }
801 
802 void spapr_caps_init(sPAPRMachineState *spapr);
803 void spapr_caps_apply(sPAPRMachineState *spapr);
804 void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu);
805 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp);
806 int spapr_caps_post_migration(sPAPRMachineState *spapr);
807 
808 void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize,
809                           Error **errp);
810 
811 #endif /* HW_SPAPR_H */
812