1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "qom/object.h" 12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13 #include "hw/ppc/xics.h" /* For ICSState */ 14 #include "hw/ppc/spapr_tpm_proxy.h" 15 16 struct SpaprVioBus; 17 struct SpaprPhbState; 18 struct SpaprNvram; 19 20 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 21 typedef struct SpaprEventSource SpaprEventSource; 22 typedef struct SpaprPendingHpt SpaprPendingHpt; 23 24 typedef struct Vof Vof; 25 26 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 27 #define SPAPR_ENTRY_POINT 0x100 28 29 #define SPAPR_TIMEBASE_FREQ 512000000ULL 30 31 #define TYPE_SPAPR_RTC "spapr-rtc" 32 33 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 34 35 struct SpaprRtcState { 36 /*< private >*/ 37 DeviceState parent_obj; 38 int64_t ns_offset; 39 }; 40 41 typedef struct SpaprDimmState SpaprDimmState; 42 43 #define TYPE_SPAPR_MACHINE "spapr-machine" 44 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 45 46 typedef enum { 47 SPAPR_RESIZE_HPT_DEFAULT = 0, 48 SPAPR_RESIZE_HPT_DISABLED, 49 SPAPR_RESIZE_HPT_ENABLED, 50 SPAPR_RESIZE_HPT_REQUIRED, 51 } SpaprResizeHpt; 52 53 /** 54 * Capabilities 55 */ 56 57 /* Hardware Transactional Memory */ 58 #define SPAPR_CAP_HTM 0x00 59 /* Vector Scalar Extensions */ 60 #define SPAPR_CAP_VSX 0x01 61 /* Decimal Floating Point */ 62 #define SPAPR_CAP_DFP 0x02 63 /* Cache Flush on Privilege Change */ 64 #define SPAPR_CAP_CFPC 0x03 65 /* Speculation Barrier Bounds Checking */ 66 #define SPAPR_CAP_SBBC 0x04 67 /* Indirect Branch Serialisation */ 68 #define SPAPR_CAP_IBS 0x05 69 /* HPT Maximum Page Size (encoded as a shift) */ 70 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 71 /* Nested KVM-HV */ 72 #define SPAPR_CAP_NESTED_KVM_HV 0x07 73 /* Large Decrementer */ 74 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 75 /* Count Cache Flush Assist HW Instruction */ 76 #define SPAPR_CAP_CCF_ASSIST 0x09 77 /* Implements PAPR FWNMI option */ 78 #define SPAPR_CAP_FWNMI 0x0A 79 /* Support H_RPT_INVALIDATE */ 80 #define SPAPR_CAP_RPT_INVALIDATE 0x0B 81 /* Support for AIL modes */ 82 #define SPAPR_CAP_AIL_MODE_3 0x0C 83 /* Num Caps */ 84 #define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1) 85 86 /* 87 * Capability Values 88 */ 89 /* Bool Caps */ 90 #define SPAPR_CAP_OFF 0x00 91 #define SPAPR_CAP_ON 0x01 92 93 /* Custom Caps */ 94 95 /* Generic */ 96 #define SPAPR_CAP_BROKEN 0x00 97 #define SPAPR_CAP_WORKAROUND 0x01 98 #define SPAPR_CAP_FIXED 0x02 99 /* SPAPR_CAP_IBS (cap-ibs) */ 100 #define SPAPR_CAP_FIXED_IBS 0x02 101 #define SPAPR_CAP_FIXED_CCD 0x03 102 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 103 104 #define FDT_MAX_SIZE 0x200000 105 106 /* Max number of GPUs per system */ 107 #define NVGPU_MAX_NUM 6 108 109 /* Max number of NUMA nodes */ 110 #define NUMA_NODES_MAX_NUM (MAX_NODES + NVGPU_MAX_NUM) 111 112 /* 113 * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 114 * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 115 * kernel source. It represents the amount of associativity domains 116 * for non-CPU resources. 117 * 118 * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 119 * array for any non-CPU resource. 120 */ 121 #define FORM1_DIST_REF_POINTS 4 122 #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 123 124 /* 125 * FORM2 NUMA affinity has a single associativity domain, giving 126 * us a assoc size of 2. 127 */ 128 #define FORM2_DIST_REF_POINTS 1 129 #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 130 131 typedef struct SpaprCapabilities SpaprCapabilities; 132 struct SpaprCapabilities { 133 uint8_t caps[SPAPR_CAP_NUM]; 134 }; 135 136 /** 137 * SpaprMachineClass: 138 */ 139 struct SpaprMachineClass { 140 /*< private >*/ 141 MachineClass parent_class; 142 143 /*< public >*/ 144 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 145 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 146 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 147 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 148 bool pre_2_10_has_unused_icps; 149 bool legacy_irq_allocation; 150 uint32_t nr_xirqs; 151 bool broken_host_serial_model; /* present real host info to the guest */ 152 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 153 bool linux_pci_probe; 154 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 155 hwaddr rma_limit; /* clamp the RMA to this size */ 156 bool pre_5_1_assoc_refpoints; 157 bool pre_5_2_numa_associativity; 158 bool pre_6_2_numa_affinity; 159 160 bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 161 uint64_t *buid, hwaddr *pio, 162 hwaddr *mmio32, hwaddr *mmio64, 163 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 164 hwaddr *nv2atsd, Error **errp); 165 SpaprResizeHpt resize_hpt_default; 166 SpaprCapabilities default_caps; 167 SpaprIrq *irq; 168 }; 169 170 #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ 171 172 #define TYPE_SPAPR_WDT "spapr-wdt" 173 OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) 174 175 typedef struct SpaprWatchdog { 176 /*< private >*/ 177 DeviceState parent_obj; 178 /*< public >*/ 179 180 QEMUTimer timer; 181 uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ 182 uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ 183 } SpaprWatchdog; 184 185 /** 186 * SpaprMachineState: 187 */ 188 struct SpaprMachineState { 189 /*< private >*/ 190 MachineState parent_obj; 191 192 struct SpaprVioBus *vio_bus; 193 QLIST_HEAD(, SpaprPhbState) phbs; 194 struct SpaprNvram *nvram; 195 SpaprRtcState rtc; 196 197 SpaprResizeHpt resize_hpt; 198 void *htab; 199 uint32_t htab_shift; 200 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ 201 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 202 203 hwaddr rma_size; 204 uint32_t fdt_size; 205 uint32_t fdt_initial_size; 206 void *fdt_blob; 207 uint8_t fdt_rng_seed[32]; 208 long kernel_size; 209 bool kernel_le; 210 uint64_t kernel_addr; 211 uint32_t initrd_base; 212 long initrd_size; 213 Vof *vof; 214 uint64_t rtc_offset; /* Now used only during incoming migration */ 215 struct PPCTimebase tb; 216 bool want_stdout_path; 217 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 218 219 /* Nested HV support (TCG only) */ 220 uint64_t nested_ptcr; 221 222 Notifier epow_notifier; 223 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 224 bool use_hotplug_event_source; 225 SpaprEventSource *event_sources; 226 227 /* ibm,client-architecture-support option negotiation */ 228 bool cas_pre_isa3_guest; 229 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 230 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 231 uint32_t max_compat_pvr; 232 233 /* Migration state */ 234 int htab_save_index; 235 bool htab_first_pass; 236 int htab_fd; 237 238 /* Pending DIMM unplug cache. It is populated when a LMB 239 * unplug starts. It can be regenerated if a migration 240 * occurs during the unplug process. */ 241 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 242 243 /* State related to FWNMI option */ 244 245 /* System Reset and Machine Check Notification Routine addresses 246 * registered by "ibm,nmi-register" RTAS call. 247 */ 248 target_ulong fwnmi_system_reset_addr; 249 target_ulong fwnmi_machine_check_addr; 250 251 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 252 * set to -1 if a FWNMI machine check is not in progress, else is set to 253 * the CPU that was delivered the machine check, and is set back to -1 254 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 255 * to synchronize other CPUs. 256 */ 257 int fwnmi_machine_check_interlock; 258 QemuCond fwnmi_machine_check_interlock_cond; 259 260 /* Set by -boot */ 261 char *boot_device; 262 263 /*< public >*/ 264 char *kvm_type; 265 char *host_model; 266 char *host_serial; 267 268 int32_t irq_map_nr; 269 unsigned long *irq_map; 270 SpaprIrq *irq; 271 qemu_irq *qirqs; 272 SpaprInterruptController *active_intc; 273 ICSState *ics; 274 SpaprXive *xive; 275 276 bool cmd_line_caps[SPAPR_CAP_NUM]; 277 SpaprCapabilities def, eff, mig; 278 279 unsigned gpu_numa_id; 280 SpaprTpmProxy *tpm_proxy; 281 282 uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 283 uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 284 285 Error *fwnmi_migration_blocker; 286 287 SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; 288 }; 289 290 #define H_SUCCESS 0 291 #define H_BUSY 1 /* Hardware busy -- retry later */ 292 #define H_CLOSED 2 /* Resource closed */ 293 #define H_NOT_AVAILABLE 3 294 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 295 #define H_PARTIAL 5 296 #define H_IN_PROGRESS 14 /* Kind of like busy */ 297 #define H_PAGE_REGISTERED 15 298 #define H_PARTIAL_STORE 16 299 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 300 #define H_CONTINUE 18 /* Returned from H_Join on success */ 301 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 302 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 303 is a good time to retry */ 304 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 305 is a good time to retry */ 306 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 307 is a good time to retry */ 308 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 309 is a good time to retry */ 310 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 311 is a good time to retry */ 312 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 313 is a good time to retry */ 314 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 315 #define H_HARDWARE -1 /* Hardware error */ 316 #define H_FUNCTION -2 /* Function not supported */ 317 #define H_PRIVILEGE -3 /* Caller not privileged */ 318 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 319 #define H_BAD_MODE -5 /* Illegal msr value */ 320 #define H_PTEG_FULL -6 /* PTEG is full */ 321 #define H_NOT_FOUND -7 /* PTE was not found" */ 322 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 323 #define H_NO_MEM -9 324 #define H_AUTHORITY -10 325 #define H_PERMISSION -11 326 #define H_DROPPED -12 327 #define H_SOURCE_PARM -13 328 #define H_DEST_PARM -14 329 #define H_REMOTE_PARM -15 330 #define H_RESOURCE -16 331 #define H_ADAPTER_PARM -17 332 #define H_RH_PARM -18 333 #define H_RCQ_PARM -19 334 #define H_SCQ_PARM -20 335 #define H_EQ_PARM -21 336 #define H_RT_PARM -22 337 #define H_ST_PARM -23 338 #define H_SIGT_PARM -24 339 #define H_TOKEN_PARM -25 340 #define H_MLENGTH_PARM -27 341 #define H_MEM_PARM -28 342 #define H_MEM_ACCESS_PARM -29 343 #define H_ATTR_PARM -30 344 #define H_PORT_PARM -31 345 #define H_MCG_PARM -32 346 #define H_VL_PARM -33 347 #define H_TSIZE_PARM -34 348 #define H_TRACE_PARM -35 349 350 #define H_MASK_PARM -37 351 #define H_MCG_FULL -38 352 #define H_ALIAS_EXIST -39 353 #define H_P_COUNTER -40 354 #define H_TABLE_FULL -41 355 #define H_ALT_TABLE -42 356 #define H_MR_CONDITION -43 357 #define H_NOT_ENOUGH_RESOURCES -44 358 #define H_R_STATE -45 359 #define H_RESCINDEND -46 360 #define H_P2 -55 361 #define H_P3 -56 362 #define H_P4 -57 363 #define H_P5 -58 364 #define H_P6 -59 365 #define H_P7 -60 366 #define H_P8 -61 367 #define H_P9 -62 368 #define H_NOOP -63 369 #define H_UNSUPPORTED -67 370 #define H_OVERLAP -68 371 #define H_UNSUPPORTED_FLAG -256 372 #define H_MULTI_THREADS_ACTIVE -9005 373 374 375 /* Long Busy is a condition that can be returned by the firmware 376 * when a call cannot be completed now, but the identical call 377 * should be retried later. This prevents calls blocking in the 378 * firmware for long periods of time. Annoyingly the firmware can return 379 * a range of return codes, hinting at how long we should wait before 380 * retrying. If you don't care for the hint, the macro below is a good 381 * way to check for the long_busy return codes 382 */ 383 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 384 && (x <= H_LONG_BUSY_END_RANGE)) 385 386 /* Flags */ 387 #define H_LARGE_PAGE (1ULL<<(63-16)) 388 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 389 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 390 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 391 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 392 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 393 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 394 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 395 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 396 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 397 #define H_ANDCOND (1ULL<<(63-33)) 398 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 399 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 400 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 401 #define H_COPY_PAGE (1ULL<<(63-49)) 402 #define H_N (1ULL<<(63-61)) 403 #define H_PP1 (1ULL<<(63-62)) 404 #define H_PP2 (1ULL<<(63-63)) 405 406 /* Values for 2nd argument to H_SET_MODE */ 407 #define H_SET_MODE_RESOURCE_SET_CIABR 1 408 #define H_SET_MODE_RESOURCE_SET_DAWR0 2 409 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 410 #define H_SET_MODE_RESOURCE_LE 4 411 412 /* Flags for H_SET_MODE_RESOURCE_LE */ 413 #define H_SET_MODE_ENDIAN_BIG 0 414 #define H_SET_MODE_ENDIAN_LITTLE 1 415 416 /* VASI States */ 417 #define H_VASI_INVALID 0 418 #define H_VASI_ENABLED 1 419 #define H_VASI_ABORTED 2 420 #define H_VASI_SUSPENDING 3 421 #define H_VASI_SUSPENDED 4 422 #define H_VASI_RESUMED 5 423 #define H_VASI_COMPLETED 6 424 425 /* DABRX flags */ 426 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 427 #define H_DABRX_KERNEL (1ULL<<(63-62)) 428 #define H_DABRX_USER (1ULL<<(63-63)) 429 430 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 431 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 432 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 433 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 434 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 435 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 436 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 437 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 438 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 439 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 440 441 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 442 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 443 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 444 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 445 #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 446 #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 447 448 /* Each control block has to be on a 4K boundary */ 449 #define H_CB_ALIGNMENT 4096 450 451 /* pSeries hypervisor opcodes */ 452 #define H_REMOVE 0x04 453 #define H_ENTER 0x08 454 #define H_READ 0x0c 455 #define H_CLEAR_MOD 0x10 456 #define H_CLEAR_REF 0x14 457 #define H_PROTECT 0x18 458 #define H_GET_TCE 0x1c 459 #define H_PUT_TCE 0x20 460 #define H_SET_SPRG0 0x24 461 #define H_SET_DABR 0x28 462 #define H_PAGE_INIT 0x2c 463 #define H_SET_ASR 0x30 464 #define H_ASR_ON 0x34 465 #define H_ASR_OFF 0x38 466 #define H_LOGICAL_CI_LOAD 0x3c 467 #define H_LOGICAL_CI_STORE 0x40 468 #define H_LOGICAL_CACHE_LOAD 0x44 469 #define H_LOGICAL_CACHE_STORE 0x48 470 #define H_LOGICAL_ICBI 0x4c 471 #define H_LOGICAL_DCBF 0x50 472 #define H_GET_TERM_CHAR 0x54 473 #define H_PUT_TERM_CHAR 0x58 474 #define H_REAL_TO_LOGICAL 0x5c 475 #define H_HYPERVISOR_DATA 0x60 476 #define H_EOI 0x64 477 #define H_CPPR 0x68 478 #define H_IPI 0x6c 479 #define H_IPOLL 0x70 480 #define H_XIRR 0x74 481 #define H_PERFMON 0x7c 482 #define H_MIGRATE_DMA 0x78 483 #define H_REGISTER_VPA 0xDC 484 #define H_CEDE 0xE0 485 #define H_CONFER 0xE4 486 #define H_PROD 0xE8 487 #define H_GET_PPP 0xEC 488 #define H_SET_PPP 0xF0 489 #define H_PURR 0xF4 490 #define H_PIC 0xF8 491 #define H_REG_CRQ 0xFC 492 #define H_FREE_CRQ 0x100 493 #define H_VIO_SIGNAL 0x104 494 #define H_SEND_CRQ 0x108 495 #define H_COPY_RDMA 0x110 496 #define H_REGISTER_LOGICAL_LAN 0x114 497 #define H_FREE_LOGICAL_LAN 0x118 498 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 499 #define H_SEND_LOGICAL_LAN 0x120 500 #define H_BULK_REMOVE 0x124 501 #define H_MULTICAST_CTRL 0x130 502 #define H_SET_XDABR 0x134 503 #define H_STUFF_TCE 0x138 504 #define H_PUT_TCE_INDIRECT 0x13C 505 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 506 #define H_VTERM_PARTNER_INFO 0x150 507 #define H_REGISTER_VTERM 0x154 508 #define H_FREE_VTERM 0x158 509 #define H_RESET_EVENTS 0x15C 510 #define H_ALLOC_RESOURCE 0x160 511 #define H_FREE_RESOURCE 0x164 512 #define H_MODIFY_QP 0x168 513 #define H_QUERY_QP 0x16C 514 #define H_REREGISTER_PMR 0x170 515 #define H_REGISTER_SMR 0x174 516 #define H_QUERY_MR 0x178 517 #define H_QUERY_MW 0x17C 518 #define H_QUERY_HCA 0x180 519 #define H_QUERY_PORT 0x184 520 #define H_MODIFY_PORT 0x188 521 #define H_DEFINE_AQP1 0x18C 522 #define H_GET_TRACE_BUFFER 0x190 523 #define H_DEFINE_AQP0 0x194 524 #define H_RESIZE_MR 0x198 525 #define H_ATTACH_MCQP 0x19C 526 #define H_DETACH_MCQP 0x1A0 527 #define H_CREATE_RPT 0x1A4 528 #define H_REMOVE_RPT 0x1A8 529 #define H_REGISTER_RPAGES 0x1AC 530 #define H_DISABLE_AND_GETC 0x1B0 531 #define H_ERROR_DATA 0x1B4 532 #define H_GET_HCA_INFO 0x1B8 533 #define H_GET_PERF_COUNT 0x1BC 534 #define H_MANAGE_TRACE 0x1C0 535 #define H_GET_CPU_CHARACTERISTICS 0x1C8 536 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 537 #define H_QUERY_INT_STATE 0x1E4 538 #define H_POLL_PENDING 0x1D8 539 #define H_ILLAN_ATTRIBUTES 0x244 540 #define H_MODIFY_HEA_QP 0x250 541 #define H_QUERY_HEA_QP 0x254 542 #define H_QUERY_HEA 0x258 543 #define H_QUERY_HEA_PORT 0x25C 544 #define H_MODIFY_HEA_PORT 0x260 545 #define H_REG_BCMC 0x264 546 #define H_DEREG_BCMC 0x268 547 #define H_REGISTER_HEA_RPAGES 0x26C 548 #define H_DISABLE_AND_GET_HEA 0x270 549 #define H_GET_HEA_INFO 0x274 550 #define H_ALLOC_HEA_RESOURCE 0x278 551 #define H_ADD_CONN 0x284 552 #define H_DEL_CONN 0x288 553 #define H_JOIN 0x298 554 #define H_VASI_STATE 0x2A4 555 #define H_ENABLE_CRQ 0x2B0 556 #define H_GET_EM_PARMS 0x2B8 557 #define H_SET_MPP 0x2D0 558 #define H_GET_MPP 0x2D4 559 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 560 #define H_XIRR_X 0x2FC 561 #define H_RANDOM 0x300 562 #define H_SET_MODE 0x31C 563 #define H_RESIZE_HPT_PREPARE 0x36C 564 #define H_RESIZE_HPT_COMMIT 0x370 565 #define H_CLEAN_SLB 0x374 566 #define H_INVALIDATE_PID 0x378 567 #define H_REGISTER_PROC_TBL 0x37C 568 #define H_SIGNAL_SYS_RESET 0x380 569 570 #define H_INT_GET_SOURCE_INFO 0x3A8 571 #define H_INT_SET_SOURCE_CONFIG 0x3AC 572 #define H_INT_GET_SOURCE_CONFIG 0x3B0 573 #define H_INT_GET_QUEUE_INFO 0x3B4 574 #define H_INT_SET_QUEUE_CONFIG 0x3B8 575 #define H_INT_GET_QUEUE_CONFIG 0x3BC 576 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 577 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 578 #define H_INT_ESB 0x3C8 579 #define H_INT_SYNC 0x3CC 580 #define H_INT_RESET 0x3D0 581 #define H_SCM_READ_METADATA 0x3E4 582 #define H_SCM_WRITE_METADATA 0x3E8 583 #define H_SCM_BIND_MEM 0x3EC 584 #define H_SCM_UNBIND_MEM 0x3F0 585 #define H_SCM_UNBIND_ALL 0x3FC 586 #define H_SCM_HEALTH 0x400 587 #define H_RPT_INVALIDATE 0x448 588 #define H_SCM_FLUSH 0x44C 589 #define H_WATCHDOG 0x45C 590 591 #define MAX_HCALL_OPCODE H_WATCHDOG 592 593 /* The hcalls above are standardized in PAPR and implemented by pHyp 594 * as well. 595 * 596 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 597 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 598 * for "platform-specific" hcalls. 599 */ 600 #define KVMPPC_HCALL_BASE 0xf000 601 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 602 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 603 /* Client Architecture support */ 604 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 605 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 606 /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 607 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 608 609 /* Platform-specific hcalls used for nested HV KVM */ 610 #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) 611 #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) 612 #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) 613 #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) 614 615 #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST 616 617 /* 618 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 619 * Secure VM mode via an Ultravisor / Protected Execution Facility 620 */ 621 #define SVM_HCALL_BASE 0xEF00 622 #define SVM_H_TPM_COMM 0xEF10 623 #define SVM_HCALL_MAX SVM_H_TPM_COMM 624 625 typedef struct SpaprDeviceTreeUpdateHeader { 626 uint32_t version_id; 627 } SpaprDeviceTreeUpdateHeader; 628 629 #define hcall_dprintf(fmt, ...) \ 630 do { \ 631 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 632 } while (0) 633 634 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 635 target_ulong opcode, 636 target_ulong *args); 637 638 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 639 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 640 target_ulong *args); 641 642 target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, 643 target_ulong shift); 644 target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, 645 target_ulong flags, target_ulong shift); 646 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 647 void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 648 649 /* Virtual Processor Area structure constants */ 650 #define VPA_MIN_SIZE 640 651 #define VPA_SIZE_OFFSET 0x4 652 #define VPA_SHARED_PROC_OFFSET 0x9 653 #define VPA_SHARED_PROC_VAL 0x2 654 #define VPA_DISPATCH_COUNTER 0x100 655 656 /* ibm,set-eeh-option */ 657 #define RTAS_EEH_DISABLE 0 658 #define RTAS_EEH_ENABLE 1 659 #define RTAS_EEH_THAW_IO 2 660 #define RTAS_EEH_THAW_DMA 3 661 662 /* ibm,get-config-addr-info2 */ 663 #define RTAS_GET_PE_ADDR 0 664 #define RTAS_GET_PE_MODE 1 665 #define RTAS_PE_MODE_NONE 0 666 #define RTAS_PE_MODE_NOT_SHARED 1 667 #define RTAS_PE_MODE_SHARED 2 668 669 /* ibm,read-slot-reset-state2 */ 670 #define RTAS_EEH_PE_STATE_NORMAL 0 671 #define RTAS_EEH_PE_STATE_RESET 1 672 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 673 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 674 #define RTAS_EEH_PE_STATE_UNAVAIL 5 675 #define RTAS_EEH_NOT_SUPPORT 0 676 #define RTAS_EEH_SUPPORT 1 677 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 678 #define RTAS_EEH_PE_RECOVER_INFO 0 679 680 /* ibm,set-slot-reset */ 681 #define RTAS_SLOT_RESET_DEACTIVATE 0 682 #define RTAS_SLOT_RESET_HOT 1 683 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 684 685 /* ibm,slot-error-detail */ 686 #define RTAS_SLOT_TEMP_ERR_LOG 1 687 #define RTAS_SLOT_PERM_ERR_LOG 2 688 689 /* RTAS return codes */ 690 #define RTAS_OUT_SUCCESS 0 691 #define RTAS_OUT_NO_ERRORS_FOUND 1 692 #define RTAS_OUT_HW_ERROR -1 693 #define RTAS_OUT_BUSY -2 694 #define RTAS_OUT_PARAM_ERROR -3 695 #define RTAS_OUT_NOT_SUPPORTED -3 696 #define RTAS_OUT_NO_SUCH_INDICATOR -3 697 #define RTAS_OUT_NOT_AUTHORIZED -9002 698 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 699 700 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 701 #define RTAS_DDW_PGSIZE_4K 0x01 702 #define RTAS_DDW_PGSIZE_64K 0x02 703 #define RTAS_DDW_PGSIZE_16M 0x04 704 #define RTAS_DDW_PGSIZE_32M 0x08 705 #define RTAS_DDW_PGSIZE_64M 0x10 706 #define RTAS_DDW_PGSIZE_128M 0x20 707 #define RTAS_DDW_PGSIZE_256M 0x40 708 #define RTAS_DDW_PGSIZE_16G 0x80 709 #define RTAS_DDW_PGSIZE_2M 0x100 710 711 /* RTAS tokens */ 712 #define RTAS_TOKEN_BASE 0x2000 713 714 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 715 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 716 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 717 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 718 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 719 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 720 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 721 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 722 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 723 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 724 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 725 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 726 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 727 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 728 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 729 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 730 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 731 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 732 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 733 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 734 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 735 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 736 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 737 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 738 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 739 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 740 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 741 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 742 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 743 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 744 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 745 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 746 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 747 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 748 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 749 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 750 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 751 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 752 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 753 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 754 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 755 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 756 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 757 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 758 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 759 760 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 761 762 /* RTAS ibm,get-system-parameter token values */ 763 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 764 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 765 #define RTAS_SYSPARM_UUID 48 766 767 /* RTAS indicator/sensor types 768 * 769 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 770 * 771 * NOTE: currently only DR-related sensors are implemented here 772 */ 773 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 774 #define RTAS_SENSOR_TYPE_DR 9002 775 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 776 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 777 778 /* Possible values for the platform-processor-diagnostics-run-mode parameter 779 * of the RTAS ibm,get-system-parameter call. 780 */ 781 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 782 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 783 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 784 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 785 786 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 787 { 788 return addr & ~0xF000000000000000ULL; 789 } 790 791 static inline uint32_t rtas_ld(target_ulong phys, int n) 792 { 793 return ldl_be_phys(&address_space_memory, 794 ppc64_phys_to_real(phys + 4 * n)); 795 } 796 797 static inline uint64_t rtas_ldq(target_ulong phys, int n) 798 { 799 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 800 } 801 802 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 803 { 804 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val); 805 } 806 807 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 808 uint32_t token, 809 uint32_t nargs, target_ulong args, 810 uint32_t nret, target_ulong rets); 811 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 812 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 813 uint32_t token, uint32_t nargs, target_ulong args, 814 uint32_t nret, target_ulong rets); 815 void spapr_dt_rtas_tokens(void *fdt, int rtas); 816 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 817 818 #define SPAPR_TCE_PAGE_SHIFT 12 819 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 820 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 821 822 #define SPAPR_VIO_BASE_LIOBN 0x00000000 823 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 824 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 825 (0x80000000 | ((phb_index) << 8) | (window_num)) 826 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 827 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 828 829 #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 830 #define RTAS_ERROR_LOG_MAX 2048 831 832 /* Offset from rtas-base where error log is placed */ 833 #define RTAS_ERROR_LOG_OFFSET 0x30 834 835 #define RTAS_EVENT_SCAN_RATE 1 836 837 /* This helper should be used to encode interrupt specifiers when the related 838 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 839 * VIO devices, RTAS event sources and PHBs). 840 */ 841 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 842 { 843 intspec[0] = cpu_to_be32(irq); 844 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 845 } 846 847 848 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 849 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 850 851 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 852 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 853 TYPE_SPAPR_IOMMU_MEMORY_REGION) 854 855 struct SpaprTceTable { 856 DeviceState parent; 857 uint32_t liobn; 858 uint32_t nb_table; 859 uint64_t bus_offset; 860 uint32_t page_shift; 861 uint64_t *table; 862 uint32_t mig_nb_table; 863 uint64_t *mig_table; 864 bool bypass; 865 bool need_vfio; 866 bool skipping_replay; 867 bool def_win; 868 int fd; 869 MemoryRegion root; 870 IOMMUMemoryRegion iommu; 871 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 872 QLIST_ENTRY(SpaprTceTable) list; 873 }; 874 875 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 876 877 struct SpaprEventLogEntry { 878 uint32_t summary; 879 uint32_t extended_length; 880 void *extended_log; 881 QTAILQ_ENTRY(SpaprEventLogEntry) next; 882 }; 883 884 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 885 void spapr_events_init(SpaprMachineState *sm); 886 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 887 void close_htab_fd(SpaprMachineState *spapr); 888 void spapr_setup_hpt(SpaprMachineState *spapr); 889 void spapr_free_hpt(SpaprMachineState *spapr); 890 void spapr_check_mmu_mode(bool guest_radix); 891 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 892 void spapr_tce_table_enable(SpaprTceTable *tcet, 893 uint32_t page_shift, uint64_t bus_offset, 894 uint32_t nb_table); 895 void spapr_tce_table_disable(SpaprTceTable *tcet); 896 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 897 898 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 899 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 900 uint32_t liobn, uint64_t window, uint32_t size); 901 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 902 SpaprTceTable *tcet); 903 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 904 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 905 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 906 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 907 uint32_t count); 908 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 909 uint32_t count); 910 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 911 uint32_t count, uint32_t index); 912 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 913 uint32_t count, uint32_t index); 914 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 915 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 916 void spapr_clear_pending_events(SpaprMachineState *spapr); 917 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 918 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 919 int spapr_max_server_number(SpaprMachineState *spapr); 920 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 921 uint64_t pte0, uint64_t pte1); 922 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 923 924 /* DRC callbacks. */ 925 void spapr_core_release(DeviceState *dev); 926 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 927 void *fdt, int *fdt_start_offset, Error **errp); 928 void spapr_lmb_release(DeviceState *dev); 929 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 930 void *fdt, int *fdt_start_offset, Error **errp); 931 void spapr_phb_release(DeviceState *dev); 932 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 933 void *fdt, int *fdt_start_offset, Error **errp); 934 935 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 936 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 937 938 #define TYPE_SPAPR_RNG "spapr-rng" 939 940 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 941 942 /* 943 * This defines the maximum number of DIMM slots we can have for sPAPR 944 * guest. This is not defined by sPAPR but we are defining it to 32 slots 945 * based on default number of slots provided by PowerPC kernel. 946 */ 947 #define SPAPR_MAX_RAM_SLOTS 32 948 949 /* 1GB alignment for hotplug memory region */ 950 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 951 952 /* 953 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 954 * property under ibm,dynamic-reconfiguration-memory node. 955 */ 956 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 957 958 /* 959 * Defines for flag value in ibm,dynamic-memory property under 960 * ibm,dynamic-reconfiguration-memory node. 961 */ 962 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 963 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 964 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 965 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 966 967 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 968 969 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 970 971 int spapr_get_vcpu_id(PowerPCCPU *cpu); 972 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 973 PowerPCCPU *spapr_find_cpu(int vcpu_id); 974 975 int spapr_caps_pre_load(void *opaque); 976 int spapr_caps_pre_save(void *opaque); 977 978 /* 979 * Handling of optional capabilities 980 */ 981 extern const VMStateDescription vmstate_spapr_cap_htm; 982 extern const VMStateDescription vmstate_spapr_cap_vsx; 983 extern const VMStateDescription vmstate_spapr_cap_dfp; 984 extern const VMStateDescription vmstate_spapr_cap_cfpc; 985 extern const VMStateDescription vmstate_spapr_cap_sbbc; 986 extern const VMStateDescription vmstate_spapr_cap_ibs; 987 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 988 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 989 extern const VMStateDescription vmstate_spapr_cap_large_decr; 990 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 991 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 992 extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 993 extern const VMStateDescription vmstate_spapr_wdt; 994 995 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 996 { 997 return spapr->eff.caps[cap]; 998 } 999 1000 void spapr_caps_init(SpaprMachineState *spapr); 1001 void spapr_caps_apply(SpaprMachineState *spapr); 1002 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 1003 void spapr_caps_add_properties(SpaprMachineClass *smc); 1004 int spapr_caps_post_migration(SpaprMachineState *spapr); 1005 1006 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 1007 Error **errp); 1008 /* 1009 * XIVE definitions 1010 */ 1011 #define SPAPR_OV5_XIVE_LEGACY 0x0 1012 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 1013 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 1014 1015 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 1016 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask); 1017 hwaddr spapr_get_rtas_addr(void); 1018 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 1019 1020 void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 1021 void spapr_vof_quiesce(MachineState *ms); 1022 bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 1023 void *val, int vallen); 1024 target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 1025 target_ulong opcode, target_ulong *args); 1026 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1027 CPUState *cs, 1028 target_ulong ovec_addr); 1029 void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 1030 1031 /* H_WATCHDOG */ 1032 void spapr_watchdog_init(SpaprMachineState *spapr); 1033 1034 #endif /* HW_SPAPR_H */ 1035