1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "qom/object.h" 12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13 #include "hw/ppc/xics.h" /* For ICSState */ 14 #include "hw/ppc/spapr_tpm_proxy.h" 15 16 struct SpaprVioBus; 17 struct SpaprPhbState; 18 struct SpaprNvram; 19 20 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 21 typedef struct SpaprEventSource SpaprEventSource; 22 typedef struct SpaprPendingHpt SpaprPendingHpt; 23 24 typedef struct Vof Vof; 25 26 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 27 #define SPAPR_ENTRY_POINT 0x100 28 29 #define SPAPR_TIMEBASE_FREQ 512000000ULL 30 31 #define TYPE_SPAPR_RTC "spapr-rtc" 32 33 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 34 35 struct SpaprRtcState { 36 /*< private >*/ 37 DeviceState parent_obj; 38 int64_t ns_offset; 39 }; 40 41 typedef struct SpaprDimmState SpaprDimmState; 42 43 #define TYPE_SPAPR_MACHINE "spapr-machine" 44 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 45 46 typedef enum { 47 SPAPR_RESIZE_HPT_DEFAULT = 0, 48 SPAPR_RESIZE_HPT_DISABLED, 49 SPAPR_RESIZE_HPT_ENABLED, 50 SPAPR_RESIZE_HPT_REQUIRED, 51 } SpaprResizeHpt; 52 53 /** 54 * Capabilities 55 */ 56 57 /* Hardware Transactional Memory */ 58 #define SPAPR_CAP_HTM 0x00 59 /* Vector Scalar Extensions */ 60 #define SPAPR_CAP_VSX 0x01 61 /* Decimal Floating Point */ 62 #define SPAPR_CAP_DFP 0x02 63 /* Cache Flush on Privilege Change */ 64 #define SPAPR_CAP_CFPC 0x03 65 /* Speculation Barrier Bounds Checking */ 66 #define SPAPR_CAP_SBBC 0x04 67 /* Indirect Branch Serialisation */ 68 #define SPAPR_CAP_IBS 0x05 69 /* HPT Maximum Page Size (encoded as a shift) */ 70 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 71 /* Nested KVM-HV */ 72 #define SPAPR_CAP_NESTED_KVM_HV 0x07 73 /* Large Decrementer */ 74 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 75 /* Count Cache Flush Assist HW Instruction */ 76 #define SPAPR_CAP_CCF_ASSIST 0x09 77 /* Implements PAPR FWNMI option */ 78 #define SPAPR_CAP_FWNMI 0x0A 79 /* Support H_RPT_INVALIDATE */ 80 #define SPAPR_CAP_RPT_INVALIDATE 0x0B 81 /* Support for AIL modes */ 82 #define SPAPR_CAP_AIL_MODE_3 0x0C 83 /* Num Caps */ 84 #define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1) 85 86 /* 87 * Capability Values 88 */ 89 /* Bool Caps */ 90 #define SPAPR_CAP_OFF 0x00 91 #define SPAPR_CAP_ON 0x01 92 93 /* Custom Caps */ 94 95 /* Generic */ 96 #define SPAPR_CAP_BROKEN 0x00 97 #define SPAPR_CAP_WORKAROUND 0x01 98 #define SPAPR_CAP_FIXED 0x02 99 /* SPAPR_CAP_IBS (cap-ibs) */ 100 #define SPAPR_CAP_FIXED_IBS 0x02 101 #define SPAPR_CAP_FIXED_CCD 0x03 102 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 103 104 #define FDT_MAX_SIZE 0x200000 105 106 /* Max number of NUMA nodes */ 107 #define NUMA_NODES_MAX_NUM (MAX_NODES) 108 109 /* 110 * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 111 * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 112 * kernel source. It represents the amount of associativity domains 113 * for non-CPU resources. 114 * 115 * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 116 * array for any non-CPU resource. 117 */ 118 #define FORM1_DIST_REF_POINTS 4 119 #define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 120 121 /* 122 * FORM2 NUMA affinity has a single associativity domain, giving 123 * us a assoc size of 2. 124 */ 125 #define FORM2_DIST_REF_POINTS 1 126 #define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 127 128 typedef struct SpaprCapabilities SpaprCapabilities; 129 struct SpaprCapabilities { 130 uint8_t caps[SPAPR_CAP_NUM]; 131 }; 132 133 /** 134 * SpaprMachineClass: 135 */ 136 struct SpaprMachineClass { 137 /*< private >*/ 138 MachineClass parent_class; 139 140 /*< public >*/ 141 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 142 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 143 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 144 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 145 bool pre_2_10_has_unused_icps; 146 bool legacy_irq_allocation; 147 uint32_t nr_xirqs; 148 bool broken_host_serial_model; /* present real host info to the guest */ 149 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 150 bool linux_pci_probe; 151 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 152 hwaddr rma_limit; /* clamp the RMA to this size */ 153 bool pre_5_1_assoc_refpoints; 154 bool pre_5_2_numa_associativity; 155 bool pre_6_2_numa_affinity; 156 157 bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 158 uint64_t *buid, hwaddr *pio, 159 hwaddr *mmio32, hwaddr *mmio64, 160 unsigned n_dma, uint32_t *liobns, Error **errp); 161 SpaprResizeHpt resize_hpt_default; 162 SpaprCapabilities default_caps; 163 SpaprIrq *irq; 164 }; 165 166 #define WDT_MAX_WATCHDOGS 4 /* Maximum number of watchdog devices */ 167 168 #define TYPE_SPAPR_WDT "spapr-wdt" 169 OBJECT_DECLARE_SIMPLE_TYPE(SpaprWatchdog, SPAPR_WDT) 170 171 typedef struct SpaprWatchdog { 172 /*< private >*/ 173 DeviceState parent_obj; 174 /*< public >*/ 175 176 QEMUTimer timer; 177 uint8_t action; /* One of PSERIES_WDTF_ACTION_xxx */ 178 uint8_t leave_others; /* leaveOtherWatchdogsRunningOnTimeout */ 179 } SpaprWatchdog; 180 181 /** 182 * SpaprMachineState: 183 */ 184 struct SpaprMachineState { 185 /*< private >*/ 186 MachineState parent_obj; 187 188 struct SpaprVioBus *vio_bus; 189 QLIST_HEAD(, SpaprPhbState) phbs; 190 struct SpaprNvram *nvram; 191 SpaprRtcState rtc; 192 193 SpaprResizeHpt resize_hpt; 194 void *htab; 195 uint32_t htab_shift; 196 uint64_t patb_entry; /* Process tbl registered in H_REGISTER_PROC_TBL */ 197 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 198 199 hwaddr rma_size; 200 uint32_t fdt_size; 201 uint32_t fdt_initial_size; 202 void *fdt_blob; 203 uint8_t fdt_rng_seed[32]; 204 long kernel_size; 205 bool kernel_le; 206 uint64_t kernel_addr; 207 uint32_t initrd_base; 208 long initrd_size; 209 Vof *vof; 210 uint64_t rtc_offset; /* Now used only during incoming migration */ 211 struct PPCTimebase tb; 212 bool want_stdout_path; 213 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 214 215 /* Nested HV support (TCG only) */ 216 uint64_t nested_ptcr; 217 218 Notifier epow_notifier; 219 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 220 bool use_hotplug_event_source; 221 SpaprEventSource *event_sources; 222 223 /* ibm,client-architecture-support option negotiation */ 224 bool cas_pre_isa3_guest; 225 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 226 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 227 uint32_t max_compat_pvr; 228 229 /* Migration state */ 230 int htab_save_index; 231 bool htab_first_pass; 232 int htab_fd; 233 234 /* Pending DIMM unplug cache. It is populated when a LMB 235 * unplug starts. It can be regenerated if a migration 236 * occurs during the unplug process. */ 237 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 238 239 /* State related to FWNMI option */ 240 241 /* System Reset and Machine Check Notification Routine addresses 242 * registered by "ibm,nmi-register" RTAS call. 243 */ 244 target_ulong fwnmi_system_reset_addr; 245 target_ulong fwnmi_machine_check_addr; 246 247 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 248 * set to -1 if a FWNMI machine check is not in progress, else is set to 249 * the CPU that was delivered the machine check, and is set back to -1 250 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 251 * to synchronize other CPUs. 252 */ 253 int fwnmi_machine_check_interlock; 254 QemuCond fwnmi_machine_check_interlock_cond; 255 256 /* Set by -boot */ 257 char *boot_device; 258 259 /*< public >*/ 260 char *kvm_type; 261 char *host_model; 262 char *host_serial; 263 264 int32_t irq_map_nr; 265 unsigned long *irq_map; 266 SpaprIrq *irq; 267 qemu_irq *qirqs; 268 SpaprInterruptController *active_intc; 269 ICSState *ics; 270 SpaprXive *xive; 271 272 bool cmd_line_caps[SPAPR_CAP_NUM]; 273 SpaprCapabilities def, eff, mig; 274 275 SpaprTpmProxy *tpm_proxy; 276 277 uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 278 uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 279 280 Error *fwnmi_migration_blocker; 281 282 SpaprWatchdog wds[WDT_MAX_WATCHDOGS]; 283 }; 284 285 #define H_SUCCESS 0 286 #define H_BUSY 1 /* Hardware busy -- retry later */ 287 #define H_CLOSED 2 /* Resource closed */ 288 #define H_NOT_AVAILABLE 3 289 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 290 #define H_PARTIAL 5 291 #define H_IN_PROGRESS 14 /* Kind of like busy */ 292 #define H_PAGE_REGISTERED 15 293 #define H_PARTIAL_STORE 16 294 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 295 #define H_CONTINUE 18 /* Returned from H_Join on success */ 296 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 297 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 298 is a good time to retry */ 299 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 300 is a good time to retry */ 301 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 302 is a good time to retry */ 303 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 304 is a good time to retry */ 305 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 306 is a good time to retry */ 307 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 308 is a good time to retry */ 309 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 310 #define H_HARDWARE -1 /* Hardware error */ 311 #define H_FUNCTION -2 /* Function not supported */ 312 #define H_PRIVILEGE -3 /* Caller not privileged */ 313 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 314 #define H_BAD_MODE -5 /* Illegal msr value */ 315 #define H_PTEG_FULL -6 /* PTEG is full */ 316 #define H_NOT_FOUND -7 /* PTE was not found" */ 317 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 318 #define H_NO_MEM -9 319 #define H_AUTHORITY -10 320 #define H_PERMISSION -11 321 #define H_DROPPED -12 322 #define H_SOURCE_PARM -13 323 #define H_DEST_PARM -14 324 #define H_REMOTE_PARM -15 325 #define H_RESOURCE -16 326 #define H_ADAPTER_PARM -17 327 #define H_RH_PARM -18 328 #define H_RCQ_PARM -19 329 #define H_SCQ_PARM -20 330 #define H_EQ_PARM -21 331 #define H_RT_PARM -22 332 #define H_ST_PARM -23 333 #define H_SIGT_PARM -24 334 #define H_TOKEN_PARM -25 335 #define H_MLENGTH_PARM -27 336 #define H_MEM_PARM -28 337 #define H_MEM_ACCESS_PARM -29 338 #define H_ATTR_PARM -30 339 #define H_PORT_PARM -31 340 #define H_MCG_PARM -32 341 #define H_VL_PARM -33 342 #define H_TSIZE_PARM -34 343 #define H_TRACE_PARM -35 344 345 #define H_MASK_PARM -37 346 #define H_MCG_FULL -38 347 #define H_ALIAS_EXIST -39 348 #define H_P_COUNTER -40 349 #define H_TABLE_FULL -41 350 #define H_ALT_TABLE -42 351 #define H_MR_CONDITION -43 352 #define H_NOT_ENOUGH_RESOURCES -44 353 #define H_R_STATE -45 354 #define H_RESCINDEND -46 355 #define H_P2 -55 356 #define H_P3 -56 357 #define H_P4 -57 358 #define H_P5 -58 359 #define H_P6 -59 360 #define H_P7 -60 361 #define H_P8 -61 362 #define H_P9 -62 363 #define H_NOOP -63 364 #define H_UNSUPPORTED -67 365 #define H_OVERLAP -68 366 #define H_UNSUPPORTED_FLAG -256 367 #define H_MULTI_THREADS_ACTIVE -9005 368 369 370 /* Long Busy is a condition that can be returned by the firmware 371 * when a call cannot be completed now, but the identical call 372 * should be retried later. This prevents calls blocking in the 373 * firmware for long periods of time. Annoyingly the firmware can return 374 * a range of return codes, hinting at how long we should wait before 375 * retrying. If you don't care for the hint, the macro below is a good 376 * way to check for the long_busy return codes 377 */ 378 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 379 && (x <= H_LONG_BUSY_END_RANGE)) 380 381 /* Flags */ 382 #define H_LARGE_PAGE (1ULL<<(63-16)) 383 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 384 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 385 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 386 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 387 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 388 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 389 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 390 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 391 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 392 #define H_ANDCOND (1ULL<<(63-33)) 393 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 394 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 395 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 396 #define H_COPY_PAGE (1ULL<<(63-49)) 397 #define H_N (1ULL<<(63-61)) 398 #define H_PP1 (1ULL<<(63-62)) 399 #define H_PP2 (1ULL<<(63-63)) 400 401 /* Values for 2nd argument to H_SET_MODE */ 402 #define H_SET_MODE_RESOURCE_SET_CIABR 1 403 #define H_SET_MODE_RESOURCE_SET_DAWR0 2 404 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 405 #define H_SET_MODE_RESOURCE_LE 4 406 407 /* Flags for H_SET_MODE_RESOURCE_LE */ 408 #define H_SET_MODE_ENDIAN_BIG 0 409 #define H_SET_MODE_ENDIAN_LITTLE 1 410 411 /* VASI States */ 412 #define H_VASI_INVALID 0 413 #define H_VASI_ENABLED 1 414 #define H_VASI_ABORTED 2 415 #define H_VASI_SUSPENDING 3 416 #define H_VASI_SUSPENDED 4 417 #define H_VASI_RESUMED 5 418 #define H_VASI_COMPLETED 6 419 420 /* DABRX flags */ 421 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 422 #define H_DABRX_KERNEL (1ULL<<(63-62)) 423 #define H_DABRX_USER (1ULL<<(63-63)) 424 425 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 426 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 427 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 428 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 429 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 430 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 431 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 432 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 433 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 434 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 435 436 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 437 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 438 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 439 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 440 #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 441 #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 442 443 /* Each control block has to be on a 4K boundary */ 444 #define H_CB_ALIGNMENT 4096 445 446 /* pSeries hypervisor opcodes */ 447 #define H_REMOVE 0x04 448 #define H_ENTER 0x08 449 #define H_READ 0x0c 450 #define H_CLEAR_MOD 0x10 451 #define H_CLEAR_REF 0x14 452 #define H_PROTECT 0x18 453 #define H_GET_TCE 0x1c 454 #define H_PUT_TCE 0x20 455 #define H_SET_SPRG0 0x24 456 #define H_SET_DABR 0x28 457 #define H_PAGE_INIT 0x2c 458 #define H_SET_ASR 0x30 459 #define H_ASR_ON 0x34 460 #define H_ASR_OFF 0x38 461 #define H_LOGICAL_CI_LOAD 0x3c 462 #define H_LOGICAL_CI_STORE 0x40 463 #define H_LOGICAL_CACHE_LOAD 0x44 464 #define H_LOGICAL_CACHE_STORE 0x48 465 #define H_LOGICAL_ICBI 0x4c 466 #define H_LOGICAL_DCBF 0x50 467 #define H_GET_TERM_CHAR 0x54 468 #define H_PUT_TERM_CHAR 0x58 469 #define H_REAL_TO_LOGICAL 0x5c 470 #define H_HYPERVISOR_DATA 0x60 471 #define H_EOI 0x64 472 #define H_CPPR 0x68 473 #define H_IPI 0x6c 474 #define H_IPOLL 0x70 475 #define H_XIRR 0x74 476 #define H_PERFMON 0x7c 477 #define H_MIGRATE_DMA 0x78 478 #define H_REGISTER_VPA 0xDC 479 #define H_CEDE 0xE0 480 #define H_CONFER 0xE4 481 #define H_PROD 0xE8 482 #define H_GET_PPP 0xEC 483 #define H_SET_PPP 0xF0 484 #define H_PURR 0xF4 485 #define H_PIC 0xF8 486 #define H_REG_CRQ 0xFC 487 #define H_FREE_CRQ 0x100 488 #define H_VIO_SIGNAL 0x104 489 #define H_SEND_CRQ 0x108 490 #define H_COPY_RDMA 0x110 491 #define H_REGISTER_LOGICAL_LAN 0x114 492 #define H_FREE_LOGICAL_LAN 0x118 493 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 494 #define H_SEND_LOGICAL_LAN 0x120 495 #define H_BULK_REMOVE 0x124 496 #define H_MULTICAST_CTRL 0x130 497 #define H_SET_XDABR 0x134 498 #define H_STUFF_TCE 0x138 499 #define H_PUT_TCE_INDIRECT 0x13C 500 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 501 #define H_VTERM_PARTNER_INFO 0x150 502 #define H_REGISTER_VTERM 0x154 503 #define H_FREE_VTERM 0x158 504 #define H_RESET_EVENTS 0x15C 505 #define H_ALLOC_RESOURCE 0x160 506 #define H_FREE_RESOURCE 0x164 507 #define H_MODIFY_QP 0x168 508 #define H_QUERY_QP 0x16C 509 #define H_REREGISTER_PMR 0x170 510 #define H_REGISTER_SMR 0x174 511 #define H_QUERY_MR 0x178 512 #define H_QUERY_MW 0x17C 513 #define H_QUERY_HCA 0x180 514 #define H_QUERY_PORT 0x184 515 #define H_MODIFY_PORT 0x188 516 #define H_DEFINE_AQP1 0x18C 517 #define H_GET_TRACE_BUFFER 0x190 518 #define H_DEFINE_AQP0 0x194 519 #define H_RESIZE_MR 0x198 520 #define H_ATTACH_MCQP 0x19C 521 #define H_DETACH_MCQP 0x1A0 522 #define H_CREATE_RPT 0x1A4 523 #define H_REMOVE_RPT 0x1A8 524 #define H_REGISTER_RPAGES 0x1AC 525 #define H_DISABLE_AND_GETC 0x1B0 526 #define H_ERROR_DATA 0x1B4 527 #define H_GET_HCA_INFO 0x1B8 528 #define H_GET_PERF_COUNT 0x1BC 529 #define H_MANAGE_TRACE 0x1C0 530 #define H_GET_CPU_CHARACTERISTICS 0x1C8 531 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 532 #define H_QUERY_INT_STATE 0x1E4 533 #define H_POLL_PENDING 0x1D8 534 #define H_ILLAN_ATTRIBUTES 0x244 535 #define H_MODIFY_HEA_QP 0x250 536 #define H_QUERY_HEA_QP 0x254 537 #define H_QUERY_HEA 0x258 538 #define H_QUERY_HEA_PORT 0x25C 539 #define H_MODIFY_HEA_PORT 0x260 540 #define H_REG_BCMC 0x264 541 #define H_DEREG_BCMC 0x268 542 #define H_REGISTER_HEA_RPAGES 0x26C 543 #define H_DISABLE_AND_GET_HEA 0x270 544 #define H_GET_HEA_INFO 0x274 545 #define H_ALLOC_HEA_RESOURCE 0x278 546 #define H_ADD_CONN 0x284 547 #define H_DEL_CONN 0x288 548 #define H_JOIN 0x298 549 #define H_VASI_STATE 0x2A4 550 #define H_ENABLE_CRQ 0x2B0 551 #define H_GET_EM_PARMS 0x2B8 552 #define H_SET_MPP 0x2D0 553 #define H_GET_MPP 0x2D4 554 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 555 #define H_XIRR_X 0x2FC 556 #define H_RANDOM 0x300 557 #define H_SET_MODE 0x31C 558 #define H_RESIZE_HPT_PREPARE 0x36C 559 #define H_RESIZE_HPT_COMMIT 0x370 560 #define H_CLEAN_SLB 0x374 561 #define H_INVALIDATE_PID 0x378 562 #define H_REGISTER_PROC_TBL 0x37C 563 #define H_SIGNAL_SYS_RESET 0x380 564 565 #define H_INT_GET_SOURCE_INFO 0x3A8 566 #define H_INT_SET_SOURCE_CONFIG 0x3AC 567 #define H_INT_GET_SOURCE_CONFIG 0x3B0 568 #define H_INT_GET_QUEUE_INFO 0x3B4 569 #define H_INT_SET_QUEUE_CONFIG 0x3B8 570 #define H_INT_GET_QUEUE_CONFIG 0x3BC 571 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 572 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 573 #define H_INT_ESB 0x3C8 574 #define H_INT_SYNC 0x3CC 575 #define H_INT_RESET 0x3D0 576 #define H_SCM_READ_METADATA 0x3E4 577 #define H_SCM_WRITE_METADATA 0x3E8 578 #define H_SCM_BIND_MEM 0x3EC 579 #define H_SCM_UNBIND_MEM 0x3F0 580 #define H_SCM_UNBIND_ALL 0x3FC 581 #define H_SCM_HEALTH 0x400 582 #define H_RPT_INVALIDATE 0x448 583 #define H_SCM_FLUSH 0x44C 584 #define H_WATCHDOG 0x45C 585 586 #define MAX_HCALL_OPCODE H_WATCHDOG 587 588 /* The hcalls above are standardized in PAPR and implemented by pHyp 589 * as well. 590 * 591 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 592 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 593 * for "platform-specific" hcalls. 594 */ 595 #define KVMPPC_HCALL_BASE 0xf000 596 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 597 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 598 /* Client Architecture support */ 599 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 600 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 601 /* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 602 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 603 604 /* Platform-specific hcalls used for nested HV KVM */ 605 #define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800) 606 #define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804) 607 #define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808) 608 #define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C) 609 610 #define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST 611 612 /* 613 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 614 * Secure VM mode via an Ultravisor / Protected Execution Facility 615 */ 616 #define SVM_HCALL_BASE 0xEF00 617 #define SVM_H_TPM_COMM 0xEF10 618 #define SVM_HCALL_MAX SVM_H_TPM_COMM 619 620 typedef struct SpaprDeviceTreeUpdateHeader { 621 uint32_t version_id; 622 } SpaprDeviceTreeUpdateHeader; 623 624 #define hcall_dprintf(fmt, ...) \ 625 do { \ 626 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 627 } while (0) 628 629 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 630 target_ulong opcode, 631 target_ulong *args); 632 633 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 634 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 635 target_ulong *args); 636 637 target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, 638 target_ulong shift); 639 target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, 640 target_ulong flags, target_ulong shift); 641 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 642 void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 643 644 /* Virtual Processor Area structure constants */ 645 #define VPA_MIN_SIZE 640 646 #define VPA_SIZE_OFFSET 0x4 647 #define VPA_SHARED_PROC_OFFSET 0x9 648 #define VPA_SHARED_PROC_VAL 0x2 649 #define VPA_DISPATCH_COUNTER 0x100 650 651 /* ibm,set-eeh-option */ 652 #define RTAS_EEH_DISABLE 0 653 #define RTAS_EEH_ENABLE 1 654 #define RTAS_EEH_THAW_IO 2 655 #define RTAS_EEH_THAW_DMA 3 656 657 /* ibm,get-config-addr-info2 */ 658 #define RTAS_GET_PE_ADDR 0 659 #define RTAS_GET_PE_MODE 1 660 #define RTAS_PE_MODE_NONE 0 661 #define RTAS_PE_MODE_NOT_SHARED 1 662 #define RTAS_PE_MODE_SHARED 2 663 664 /* ibm,read-slot-reset-state2 */ 665 #define RTAS_EEH_PE_STATE_NORMAL 0 666 #define RTAS_EEH_PE_STATE_RESET 1 667 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 668 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 669 #define RTAS_EEH_PE_STATE_UNAVAIL 5 670 #define RTAS_EEH_NOT_SUPPORT 0 671 #define RTAS_EEH_SUPPORT 1 672 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 673 #define RTAS_EEH_PE_RECOVER_INFO 0 674 675 /* ibm,set-slot-reset */ 676 #define RTAS_SLOT_RESET_DEACTIVATE 0 677 #define RTAS_SLOT_RESET_HOT 1 678 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 679 680 /* ibm,slot-error-detail */ 681 #define RTAS_SLOT_TEMP_ERR_LOG 1 682 #define RTAS_SLOT_PERM_ERR_LOG 2 683 684 /* RTAS return codes */ 685 #define RTAS_OUT_SUCCESS 0 686 #define RTAS_OUT_NO_ERRORS_FOUND 1 687 #define RTAS_OUT_HW_ERROR -1 688 #define RTAS_OUT_BUSY -2 689 #define RTAS_OUT_PARAM_ERROR -3 690 #define RTAS_OUT_NOT_SUPPORTED -3 691 #define RTAS_OUT_NO_SUCH_INDICATOR -3 692 #define RTAS_OUT_NOT_AUTHORIZED -9002 693 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 694 695 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 696 #define RTAS_DDW_PGSIZE_4K 0x01 697 #define RTAS_DDW_PGSIZE_64K 0x02 698 #define RTAS_DDW_PGSIZE_16M 0x04 699 #define RTAS_DDW_PGSIZE_32M 0x08 700 #define RTAS_DDW_PGSIZE_64M 0x10 701 #define RTAS_DDW_PGSIZE_128M 0x20 702 #define RTAS_DDW_PGSIZE_256M 0x40 703 #define RTAS_DDW_PGSIZE_16G 0x80 704 #define RTAS_DDW_PGSIZE_2M 0x100 705 706 /* RTAS tokens */ 707 #define RTAS_TOKEN_BASE 0x2000 708 709 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 710 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 711 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 712 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 713 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 714 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 715 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 716 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 717 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 718 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 719 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 720 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 721 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 722 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 723 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 724 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 725 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 726 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 727 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 728 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 729 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 730 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 731 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 732 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 733 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 734 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 735 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 736 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 737 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 738 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 739 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 740 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 741 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 742 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 743 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 744 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 745 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 746 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 747 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 748 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 749 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 750 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 751 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 752 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 753 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 754 755 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 756 757 /* RTAS ibm,get-system-parameter token values */ 758 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 759 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 760 #define RTAS_SYSPARM_UUID 48 761 762 /* RTAS indicator/sensor types 763 * 764 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 765 * 766 * NOTE: currently only DR-related sensors are implemented here 767 */ 768 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 769 #define RTAS_SENSOR_TYPE_DR 9002 770 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 771 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 772 773 /* Possible values for the platform-processor-diagnostics-run-mode parameter 774 * of the RTAS ibm,get-system-parameter call. 775 */ 776 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 777 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 778 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 779 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 780 781 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 782 { 783 return addr & ~0xF000000000000000ULL; 784 } 785 786 static inline uint32_t rtas_ld(target_ulong phys, int n) 787 { 788 return ldl_be_phys(&address_space_memory, 789 ppc64_phys_to_real(phys + 4 * n)); 790 } 791 792 static inline uint64_t rtas_ldq(target_ulong phys, int n) 793 { 794 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 795 } 796 797 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 798 { 799 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4 * n), val); 800 } 801 802 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 803 uint32_t token, 804 uint32_t nargs, target_ulong args, 805 uint32_t nret, target_ulong rets); 806 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 807 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 808 uint32_t token, uint32_t nargs, target_ulong args, 809 uint32_t nret, target_ulong rets); 810 void spapr_dt_rtas_tokens(void *fdt, int rtas); 811 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 812 813 #define SPAPR_TCE_PAGE_SHIFT 12 814 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 815 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 816 817 #define SPAPR_VIO_BASE_LIOBN 0x00000000 818 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 819 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 820 (0x80000000 | ((phb_index) << 8) | (window_num)) 821 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 822 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 823 824 #define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 825 #define RTAS_ERROR_LOG_MAX 2048 826 827 /* Offset from rtas-base where error log is placed */ 828 #define RTAS_ERROR_LOG_OFFSET 0x30 829 830 #define RTAS_EVENT_SCAN_RATE 1 831 832 /* This helper should be used to encode interrupt specifiers when the related 833 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 834 * VIO devices, RTAS event sources and PHBs). 835 */ 836 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 837 { 838 intspec[0] = cpu_to_be32(irq); 839 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 840 } 841 842 843 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 844 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 845 846 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 847 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 848 TYPE_SPAPR_IOMMU_MEMORY_REGION) 849 850 struct SpaprTceTable { 851 DeviceState parent; 852 uint32_t liobn; 853 uint32_t nb_table; 854 uint64_t bus_offset; 855 uint32_t page_shift; 856 uint64_t *table; 857 uint32_t mig_nb_table; 858 uint64_t *mig_table; 859 bool bypass; 860 bool need_vfio; 861 bool skipping_replay; 862 bool def_win; 863 int fd; 864 MemoryRegion root; 865 IOMMUMemoryRegion iommu; 866 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 867 QLIST_ENTRY(SpaprTceTable) list; 868 }; 869 870 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 871 872 struct SpaprEventLogEntry { 873 uint32_t summary; 874 uint32_t extended_length; 875 void *extended_log; 876 QTAILQ_ENTRY(SpaprEventLogEntry) next; 877 }; 878 879 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 880 void spapr_events_init(SpaprMachineState *sm); 881 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 882 void close_htab_fd(SpaprMachineState *spapr); 883 void spapr_setup_hpt(SpaprMachineState *spapr); 884 void spapr_free_hpt(SpaprMachineState *spapr); 885 void spapr_check_mmu_mode(bool guest_radix); 886 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 887 void spapr_tce_table_enable(SpaprTceTable *tcet, 888 uint32_t page_shift, uint64_t bus_offset, 889 uint32_t nb_table); 890 void spapr_tce_table_disable(SpaprTceTable *tcet); 891 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 892 893 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 894 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 895 uint32_t liobn, uint64_t window, uint32_t size); 896 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 897 SpaprTceTable *tcet); 898 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 899 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 900 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 901 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 902 uint32_t count); 903 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 904 uint32_t count); 905 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 906 uint32_t count, uint32_t index); 907 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 908 uint32_t count, uint32_t index); 909 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 910 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 911 void spapr_clear_pending_events(SpaprMachineState *spapr); 912 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 913 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 914 int spapr_max_server_number(SpaprMachineState *spapr); 915 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 916 uint64_t pte0, uint64_t pte1); 917 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 918 919 /* DRC callbacks. */ 920 void spapr_core_release(DeviceState *dev); 921 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 922 void *fdt, int *fdt_start_offset, Error **errp); 923 void spapr_lmb_release(DeviceState *dev); 924 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 925 void *fdt, int *fdt_start_offset, Error **errp); 926 void spapr_phb_release(DeviceState *dev); 927 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 928 void *fdt, int *fdt_start_offset, Error **errp); 929 930 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 931 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 932 933 #define TYPE_SPAPR_RNG "spapr-rng" 934 935 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 936 937 /* 938 * This defines the maximum number of DIMM slots we can have for sPAPR 939 * guest. This is not defined by sPAPR but we are defining it to 32 slots 940 * based on default number of slots provided by PowerPC kernel. 941 */ 942 #define SPAPR_MAX_RAM_SLOTS 32 943 944 /* 1GB alignment for hotplug memory region */ 945 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 946 947 /* 948 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 949 * property under ibm,dynamic-reconfiguration-memory node. 950 */ 951 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 952 953 /* 954 * Defines for flag value in ibm,dynamic-memory property under 955 * ibm,dynamic-reconfiguration-memory node. 956 */ 957 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 958 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 959 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 960 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 961 962 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 963 964 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 965 966 int spapr_get_vcpu_id(PowerPCCPU *cpu); 967 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 968 PowerPCCPU *spapr_find_cpu(int vcpu_id); 969 970 int spapr_caps_pre_load(void *opaque); 971 int spapr_caps_pre_save(void *opaque); 972 973 /* 974 * Handling of optional capabilities 975 */ 976 extern const VMStateDescription vmstate_spapr_cap_htm; 977 extern const VMStateDescription vmstate_spapr_cap_vsx; 978 extern const VMStateDescription vmstate_spapr_cap_dfp; 979 extern const VMStateDescription vmstate_spapr_cap_cfpc; 980 extern const VMStateDescription vmstate_spapr_cap_sbbc; 981 extern const VMStateDescription vmstate_spapr_cap_ibs; 982 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 983 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 984 extern const VMStateDescription vmstate_spapr_cap_large_decr; 985 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 986 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 987 extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 988 extern const VMStateDescription vmstate_spapr_wdt; 989 990 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 991 { 992 return spapr->eff.caps[cap]; 993 } 994 995 void spapr_caps_init(SpaprMachineState *spapr); 996 void spapr_caps_apply(SpaprMachineState *spapr); 997 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 998 void spapr_caps_add_properties(SpaprMachineClass *smc); 999 int spapr_caps_post_migration(SpaprMachineState *spapr); 1000 1001 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 1002 Error **errp); 1003 /* 1004 * XIVE definitions 1005 */ 1006 #define SPAPR_OV5_XIVE_LEGACY 0x0 1007 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 1008 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 1009 1010 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 1011 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask); 1012 hwaddr spapr_get_rtas_addr(void); 1013 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 1014 1015 void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 1016 void spapr_vof_quiesce(MachineState *ms); 1017 bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 1018 void *val, int vallen); 1019 target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 1020 target_ulong opcode, target_ulong *args); 1021 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1022 CPUState *cs, 1023 target_ulong ovec_addr); 1024 void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 1025 1026 /* H_WATCHDOG */ 1027 void spapr_watchdog_init(SpaprMachineState *spapr); 1028 1029 #endif /* HW_SPAPR_H */ 1030