1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 12 struct VIOsPAPRBus; 13 struct sPAPRPHBState; 14 struct sPAPRNVRAM; 15 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 16 typedef struct sPAPREventSource sPAPREventSource; 17 typedef struct sPAPRPendingHPT sPAPRPendingHPT; 18 typedef struct ICSState ICSState; 19 typedef struct sPAPRXive sPAPRXive; 20 21 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 22 #define SPAPR_ENTRY_POINT 0x100 23 24 #define SPAPR_TIMEBASE_FREQ 512000000ULL 25 26 #define TYPE_SPAPR_RTC "spapr-rtc" 27 28 #define SPAPR_RTC(obj) \ 29 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 30 31 typedef struct sPAPRRTCState sPAPRRTCState; 32 struct sPAPRRTCState { 33 /*< private >*/ 34 DeviceState parent_obj; 35 int64_t ns_offset; 36 }; 37 38 typedef struct sPAPRDIMMState sPAPRDIMMState; 39 typedef struct sPAPRMachineClass sPAPRMachineClass; 40 41 #define TYPE_SPAPR_MACHINE "spapr-machine" 42 #define SPAPR_MACHINE(obj) \ 43 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 44 #define SPAPR_MACHINE_GET_CLASS(obj) \ 45 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 46 #define SPAPR_MACHINE_CLASS(klass) \ 47 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 48 49 typedef enum { 50 SPAPR_RESIZE_HPT_DEFAULT = 0, 51 SPAPR_RESIZE_HPT_DISABLED, 52 SPAPR_RESIZE_HPT_ENABLED, 53 SPAPR_RESIZE_HPT_REQUIRED, 54 } sPAPRResizeHPT; 55 56 /** 57 * Capabilities 58 */ 59 60 /* Hardware Transactional Memory */ 61 #define SPAPR_CAP_HTM 0x00 62 /* Vector Scalar Extensions */ 63 #define SPAPR_CAP_VSX 0x01 64 /* Decimal Floating Point */ 65 #define SPAPR_CAP_DFP 0x02 66 /* Cache Flush on Privilege Change */ 67 #define SPAPR_CAP_CFPC 0x03 68 /* Speculation Barrier Bounds Checking */ 69 #define SPAPR_CAP_SBBC 0x04 70 /* Indirect Branch Serialisation */ 71 #define SPAPR_CAP_IBS 0x05 72 /* HPT Maximum Page Size (encoded as a shift) */ 73 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 74 /* Nested KVM-HV */ 75 #define SPAPR_CAP_NESTED_KVM_HV 0x07 76 /* Num Caps */ 77 #define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_KVM_HV + 1) 78 79 /* 80 * Capability Values 81 */ 82 /* Bool Caps */ 83 #define SPAPR_CAP_OFF 0x00 84 #define SPAPR_CAP_ON 0x01 85 /* Custom Caps */ 86 #define SPAPR_CAP_BROKEN 0x00 87 #define SPAPR_CAP_WORKAROUND 0x01 88 #define SPAPR_CAP_FIXED 0x02 89 #define SPAPR_CAP_FIXED_IBS 0x02 90 #define SPAPR_CAP_FIXED_CCD 0x03 91 92 typedef struct sPAPRCapabilities sPAPRCapabilities; 93 struct sPAPRCapabilities { 94 uint8_t caps[SPAPR_CAP_NUM]; 95 }; 96 97 /** 98 * sPAPRMachineClass: 99 */ 100 struct sPAPRMachineClass { 101 /*< private >*/ 102 MachineClass parent_class; 103 104 /*< public >*/ 105 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 106 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 107 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 108 bool pre_2_10_has_unused_icps; 109 bool legacy_irq_allocation; 110 111 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 112 uint64_t *buid, hwaddr *pio, 113 hwaddr *mmio32, hwaddr *mmio64, 114 unsigned n_dma, uint32_t *liobns, Error **errp); 115 sPAPRResizeHPT resize_hpt_default; 116 sPAPRCapabilities default_caps; 117 sPAPRIrq *irq; 118 }; 119 120 /** 121 * sPAPRMachineState: 122 */ 123 struct sPAPRMachineState { 124 /*< private >*/ 125 MachineState parent_obj; 126 127 struct VIOsPAPRBus *vio_bus; 128 QLIST_HEAD(, sPAPRPHBState) phbs; 129 struct sPAPRNVRAM *nvram; 130 ICSState *ics; 131 sPAPRRTCState rtc; 132 133 sPAPRResizeHPT resize_hpt; 134 void *htab; 135 uint32_t htab_shift; 136 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 137 sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 138 139 hwaddr rma_size; 140 int vrma_adjust; 141 ssize_t rtas_size; 142 void *rtas_blob; 143 uint32_t fdt_size; 144 uint32_t fdt_initial_size; 145 void *fdt_blob; 146 long kernel_size; 147 bool kernel_le; 148 uint32_t initrd_base; 149 long initrd_size; 150 uint64_t rtc_offset; /* Now used only during incoming migration */ 151 struct PPCTimebase tb; 152 bool has_graphics; 153 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 154 155 Notifier epow_notifier; 156 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 157 bool use_hotplug_event_source; 158 sPAPREventSource *event_sources; 159 160 /* ibm,client-architecture-support option negotiation */ 161 bool cas_reboot; 162 bool cas_legacy_guest_workaround; 163 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 164 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 165 uint32_t max_compat_pvr; 166 167 /* Migration state */ 168 int htab_save_index; 169 bool htab_first_pass; 170 int htab_fd; 171 172 /* Pending DIMM unplug cache. It is populated when a LMB 173 * unplug starts. It can be regenerated if a migration 174 * occurs during the unplug process. */ 175 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 176 177 /*< public >*/ 178 char *kvm_type; 179 180 const char *icp_type; 181 int32_t irq_map_nr; 182 unsigned long *irq_map; 183 sPAPRXive *xive; 184 sPAPRIrq *irq; 185 qemu_irq *qirqs; 186 187 bool cmd_line_caps[SPAPR_CAP_NUM]; 188 sPAPRCapabilities def, eff, mig; 189 }; 190 191 #define H_SUCCESS 0 192 #define H_BUSY 1 /* Hardware busy -- retry later */ 193 #define H_CLOSED 2 /* Resource closed */ 194 #define H_NOT_AVAILABLE 3 195 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 196 #define H_PARTIAL 5 197 #define H_IN_PROGRESS 14 /* Kind of like busy */ 198 #define H_PAGE_REGISTERED 15 199 #define H_PARTIAL_STORE 16 200 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 201 #define H_CONTINUE 18 /* Returned from H_Join on success */ 202 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 203 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 204 is a good time to retry */ 205 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 206 is a good time to retry */ 207 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 208 is a good time to retry */ 209 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 210 is a good time to retry */ 211 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 212 is a good time to retry */ 213 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 214 is a good time to retry */ 215 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 216 #define H_HARDWARE -1 /* Hardware error */ 217 #define H_FUNCTION -2 /* Function not supported */ 218 #define H_PRIVILEGE -3 /* Caller not privileged */ 219 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 220 #define H_BAD_MODE -5 /* Illegal msr value */ 221 #define H_PTEG_FULL -6 /* PTEG is full */ 222 #define H_NOT_FOUND -7 /* PTE was not found" */ 223 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 224 #define H_NO_MEM -9 225 #define H_AUTHORITY -10 226 #define H_PERMISSION -11 227 #define H_DROPPED -12 228 #define H_SOURCE_PARM -13 229 #define H_DEST_PARM -14 230 #define H_REMOTE_PARM -15 231 #define H_RESOURCE -16 232 #define H_ADAPTER_PARM -17 233 #define H_RH_PARM -18 234 #define H_RCQ_PARM -19 235 #define H_SCQ_PARM -20 236 #define H_EQ_PARM -21 237 #define H_RT_PARM -22 238 #define H_ST_PARM -23 239 #define H_SIGT_PARM -24 240 #define H_TOKEN_PARM -25 241 #define H_MLENGTH_PARM -27 242 #define H_MEM_PARM -28 243 #define H_MEM_ACCESS_PARM -29 244 #define H_ATTR_PARM -30 245 #define H_PORT_PARM -31 246 #define H_MCG_PARM -32 247 #define H_VL_PARM -33 248 #define H_TSIZE_PARM -34 249 #define H_TRACE_PARM -35 250 251 #define H_MASK_PARM -37 252 #define H_MCG_FULL -38 253 #define H_ALIAS_EXIST -39 254 #define H_P_COUNTER -40 255 #define H_TABLE_FULL -41 256 #define H_ALT_TABLE -42 257 #define H_MR_CONDITION -43 258 #define H_NOT_ENOUGH_RESOURCES -44 259 #define H_R_STATE -45 260 #define H_RESCINDEND -46 261 #define H_P2 -55 262 #define H_P3 -56 263 #define H_P4 -57 264 #define H_P5 -58 265 #define H_P6 -59 266 #define H_P7 -60 267 #define H_P8 -61 268 #define H_P9 -62 269 #define H_UNSUPPORTED_FLAG -256 270 #define H_MULTI_THREADS_ACTIVE -9005 271 272 273 /* Long Busy is a condition that can be returned by the firmware 274 * when a call cannot be completed now, but the identical call 275 * should be retried later. This prevents calls blocking in the 276 * firmware for long periods of time. Annoyingly the firmware can return 277 * a range of return codes, hinting at how long we should wait before 278 * retrying. If you don't care for the hint, the macro below is a good 279 * way to check for the long_busy return codes 280 */ 281 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 282 && (x <= H_LONG_BUSY_END_RANGE)) 283 284 /* Flags */ 285 #define H_LARGE_PAGE (1ULL<<(63-16)) 286 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 287 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 288 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 289 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 290 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 291 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 292 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 293 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 294 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 295 #define H_ANDCOND (1ULL<<(63-33)) 296 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 297 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 298 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 299 #define H_COPY_PAGE (1ULL<<(63-49)) 300 #define H_N (1ULL<<(63-61)) 301 #define H_PP1 (1ULL<<(63-62)) 302 #define H_PP2 (1ULL<<(63-63)) 303 304 /* Values for 2nd argument to H_SET_MODE */ 305 #define H_SET_MODE_RESOURCE_SET_CIABR 1 306 #define H_SET_MODE_RESOURCE_SET_DAWR 2 307 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 308 #define H_SET_MODE_RESOURCE_LE 4 309 310 /* Flags for H_SET_MODE_RESOURCE_LE */ 311 #define H_SET_MODE_ENDIAN_BIG 0 312 #define H_SET_MODE_ENDIAN_LITTLE 1 313 314 /* VASI States */ 315 #define H_VASI_INVALID 0 316 #define H_VASI_ENABLED 1 317 #define H_VASI_ABORTED 2 318 #define H_VASI_SUSPENDING 3 319 #define H_VASI_SUSPENDED 4 320 #define H_VASI_RESUMED 5 321 #define H_VASI_COMPLETED 6 322 323 /* DABRX flags */ 324 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 325 #define H_DABRX_KERNEL (1ULL<<(63-62)) 326 #define H_DABRX_USER (1ULL<<(63-63)) 327 328 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 329 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 330 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 331 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 332 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 333 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 334 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 335 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 336 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 337 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 338 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 339 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 340 341 /* Each control block has to be on a 4K boundary */ 342 #define H_CB_ALIGNMENT 4096 343 344 /* pSeries hypervisor opcodes */ 345 #define H_REMOVE 0x04 346 #define H_ENTER 0x08 347 #define H_READ 0x0c 348 #define H_CLEAR_MOD 0x10 349 #define H_CLEAR_REF 0x14 350 #define H_PROTECT 0x18 351 #define H_GET_TCE 0x1c 352 #define H_PUT_TCE 0x20 353 #define H_SET_SPRG0 0x24 354 #define H_SET_DABR 0x28 355 #define H_PAGE_INIT 0x2c 356 #define H_SET_ASR 0x30 357 #define H_ASR_ON 0x34 358 #define H_ASR_OFF 0x38 359 #define H_LOGICAL_CI_LOAD 0x3c 360 #define H_LOGICAL_CI_STORE 0x40 361 #define H_LOGICAL_CACHE_LOAD 0x44 362 #define H_LOGICAL_CACHE_STORE 0x48 363 #define H_LOGICAL_ICBI 0x4c 364 #define H_LOGICAL_DCBF 0x50 365 #define H_GET_TERM_CHAR 0x54 366 #define H_PUT_TERM_CHAR 0x58 367 #define H_REAL_TO_LOGICAL 0x5c 368 #define H_HYPERVISOR_DATA 0x60 369 #define H_EOI 0x64 370 #define H_CPPR 0x68 371 #define H_IPI 0x6c 372 #define H_IPOLL 0x70 373 #define H_XIRR 0x74 374 #define H_PERFMON 0x7c 375 #define H_MIGRATE_DMA 0x78 376 #define H_REGISTER_VPA 0xDC 377 #define H_CEDE 0xE0 378 #define H_CONFER 0xE4 379 #define H_PROD 0xE8 380 #define H_GET_PPP 0xEC 381 #define H_SET_PPP 0xF0 382 #define H_PURR 0xF4 383 #define H_PIC 0xF8 384 #define H_REG_CRQ 0xFC 385 #define H_FREE_CRQ 0x100 386 #define H_VIO_SIGNAL 0x104 387 #define H_SEND_CRQ 0x108 388 #define H_COPY_RDMA 0x110 389 #define H_REGISTER_LOGICAL_LAN 0x114 390 #define H_FREE_LOGICAL_LAN 0x118 391 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 392 #define H_SEND_LOGICAL_LAN 0x120 393 #define H_BULK_REMOVE 0x124 394 #define H_MULTICAST_CTRL 0x130 395 #define H_SET_XDABR 0x134 396 #define H_STUFF_TCE 0x138 397 #define H_PUT_TCE_INDIRECT 0x13C 398 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 399 #define H_VTERM_PARTNER_INFO 0x150 400 #define H_REGISTER_VTERM 0x154 401 #define H_FREE_VTERM 0x158 402 #define H_RESET_EVENTS 0x15C 403 #define H_ALLOC_RESOURCE 0x160 404 #define H_FREE_RESOURCE 0x164 405 #define H_MODIFY_QP 0x168 406 #define H_QUERY_QP 0x16C 407 #define H_REREGISTER_PMR 0x170 408 #define H_REGISTER_SMR 0x174 409 #define H_QUERY_MR 0x178 410 #define H_QUERY_MW 0x17C 411 #define H_QUERY_HCA 0x180 412 #define H_QUERY_PORT 0x184 413 #define H_MODIFY_PORT 0x188 414 #define H_DEFINE_AQP1 0x18C 415 #define H_GET_TRACE_BUFFER 0x190 416 #define H_DEFINE_AQP0 0x194 417 #define H_RESIZE_MR 0x198 418 #define H_ATTACH_MCQP 0x19C 419 #define H_DETACH_MCQP 0x1A0 420 #define H_CREATE_RPT 0x1A4 421 #define H_REMOVE_RPT 0x1A8 422 #define H_REGISTER_RPAGES 0x1AC 423 #define H_DISABLE_AND_GETC 0x1B0 424 #define H_ERROR_DATA 0x1B4 425 #define H_GET_HCA_INFO 0x1B8 426 #define H_GET_PERF_COUNT 0x1BC 427 #define H_MANAGE_TRACE 0x1C0 428 #define H_GET_CPU_CHARACTERISTICS 0x1C8 429 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 430 #define H_QUERY_INT_STATE 0x1E4 431 #define H_POLL_PENDING 0x1D8 432 #define H_ILLAN_ATTRIBUTES 0x244 433 #define H_MODIFY_HEA_QP 0x250 434 #define H_QUERY_HEA_QP 0x254 435 #define H_QUERY_HEA 0x258 436 #define H_QUERY_HEA_PORT 0x25C 437 #define H_MODIFY_HEA_PORT 0x260 438 #define H_REG_BCMC 0x264 439 #define H_DEREG_BCMC 0x268 440 #define H_REGISTER_HEA_RPAGES 0x26C 441 #define H_DISABLE_AND_GET_HEA 0x270 442 #define H_GET_HEA_INFO 0x274 443 #define H_ALLOC_HEA_RESOURCE 0x278 444 #define H_ADD_CONN 0x284 445 #define H_DEL_CONN 0x288 446 #define H_JOIN 0x298 447 #define H_VASI_STATE 0x2A4 448 #define H_ENABLE_CRQ 0x2B0 449 #define H_GET_EM_PARMS 0x2B8 450 #define H_SET_MPP 0x2D0 451 #define H_GET_MPP 0x2D4 452 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 453 #define H_XIRR_X 0x2FC 454 #define H_RANDOM 0x300 455 #define H_SET_MODE 0x31C 456 #define H_RESIZE_HPT_PREPARE 0x36C 457 #define H_RESIZE_HPT_COMMIT 0x370 458 #define H_CLEAN_SLB 0x374 459 #define H_INVALIDATE_PID 0x378 460 #define H_REGISTER_PROC_TBL 0x37C 461 #define H_SIGNAL_SYS_RESET 0x380 462 463 #define H_INT_GET_SOURCE_INFO 0x3A8 464 #define H_INT_SET_SOURCE_CONFIG 0x3AC 465 #define H_INT_GET_SOURCE_CONFIG 0x3B0 466 #define H_INT_GET_QUEUE_INFO 0x3B4 467 #define H_INT_SET_QUEUE_CONFIG 0x3B8 468 #define H_INT_GET_QUEUE_CONFIG 0x3BC 469 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 470 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 471 #define H_INT_ESB 0x3C8 472 #define H_INT_SYNC 0x3CC 473 #define H_INT_RESET 0x3D0 474 475 #define MAX_HCALL_OPCODE H_INT_RESET 476 477 /* The hcalls above are standardized in PAPR and implemented by pHyp 478 * as well. 479 * 480 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 481 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 482 * for "platform-specific" hcalls. 483 */ 484 #define KVMPPC_HCALL_BASE 0xf000 485 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 486 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 487 /* Client Architecture support */ 488 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 489 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 490 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 491 492 typedef struct sPAPRDeviceTreeUpdateHeader { 493 uint32_t version_id; 494 } sPAPRDeviceTreeUpdateHeader; 495 496 #define hcall_dprintf(fmt, ...) \ 497 do { \ 498 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 499 } while (0) 500 501 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 502 target_ulong opcode, 503 target_ulong *args); 504 505 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 506 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 507 target_ulong *args); 508 509 /* ibm,set-eeh-option */ 510 #define RTAS_EEH_DISABLE 0 511 #define RTAS_EEH_ENABLE 1 512 #define RTAS_EEH_THAW_IO 2 513 #define RTAS_EEH_THAW_DMA 3 514 515 /* ibm,get-config-addr-info2 */ 516 #define RTAS_GET_PE_ADDR 0 517 #define RTAS_GET_PE_MODE 1 518 #define RTAS_PE_MODE_NONE 0 519 #define RTAS_PE_MODE_NOT_SHARED 1 520 #define RTAS_PE_MODE_SHARED 2 521 522 /* ibm,read-slot-reset-state2 */ 523 #define RTAS_EEH_PE_STATE_NORMAL 0 524 #define RTAS_EEH_PE_STATE_RESET 1 525 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 526 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 527 #define RTAS_EEH_PE_STATE_UNAVAIL 5 528 #define RTAS_EEH_NOT_SUPPORT 0 529 #define RTAS_EEH_SUPPORT 1 530 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 531 #define RTAS_EEH_PE_RECOVER_INFO 0 532 533 /* ibm,set-slot-reset */ 534 #define RTAS_SLOT_RESET_DEACTIVATE 0 535 #define RTAS_SLOT_RESET_HOT 1 536 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 537 538 /* ibm,slot-error-detail */ 539 #define RTAS_SLOT_TEMP_ERR_LOG 1 540 #define RTAS_SLOT_PERM_ERR_LOG 2 541 542 /* RTAS return codes */ 543 #define RTAS_OUT_SUCCESS 0 544 #define RTAS_OUT_NO_ERRORS_FOUND 1 545 #define RTAS_OUT_HW_ERROR -1 546 #define RTAS_OUT_BUSY -2 547 #define RTAS_OUT_PARAM_ERROR -3 548 #define RTAS_OUT_NOT_SUPPORTED -3 549 #define RTAS_OUT_NO_SUCH_INDICATOR -3 550 #define RTAS_OUT_NOT_AUTHORIZED -9002 551 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 552 553 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 554 #define RTAS_DDW_PGSIZE_4K 0x01 555 #define RTAS_DDW_PGSIZE_64K 0x02 556 #define RTAS_DDW_PGSIZE_16M 0x04 557 #define RTAS_DDW_PGSIZE_32M 0x08 558 #define RTAS_DDW_PGSIZE_64M 0x10 559 #define RTAS_DDW_PGSIZE_128M 0x20 560 #define RTAS_DDW_PGSIZE_256M 0x40 561 #define RTAS_DDW_PGSIZE_16G 0x80 562 563 /* RTAS tokens */ 564 #define RTAS_TOKEN_BASE 0x2000 565 566 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 567 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 568 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 569 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 570 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 571 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 572 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 573 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 574 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 575 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 576 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 577 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 578 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 579 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 580 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 581 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 582 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 583 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 584 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 585 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 586 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 587 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 588 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 589 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 590 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 591 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 592 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 593 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 594 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 595 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 596 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 597 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 598 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 599 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 600 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 601 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 602 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 603 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 604 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 605 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 606 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 607 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 608 609 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 610 611 /* RTAS ibm,get-system-parameter token values */ 612 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 613 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 614 #define RTAS_SYSPARM_UUID 48 615 616 /* RTAS indicator/sensor types 617 * 618 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 619 * 620 * NOTE: currently only DR-related sensors are implemented here 621 */ 622 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 623 #define RTAS_SENSOR_TYPE_DR 9002 624 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 625 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 626 627 /* Possible values for the platform-processor-diagnostics-run-mode parameter 628 * of the RTAS ibm,get-system-parameter call. 629 */ 630 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 631 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 632 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 633 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 634 635 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 636 { 637 return addr & ~0xF000000000000000ULL; 638 } 639 640 static inline uint32_t rtas_ld(target_ulong phys, int n) 641 { 642 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 643 } 644 645 static inline uint64_t rtas_ldq(target_ulong phys, int n) 646 { 647 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 648 } 649 650 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 651 { 652 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 653 } 654 655 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 656 uint32_t token, 657 uint32_t nargs, target_ulong args, 658 uint32_t nret, target_ulong rets); 659 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 660 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 661 uint32_t token, uint32_t nargs, target_ulong args, 662 uint32_t nret, target_ulong rets); 663 void spapr_dt_rtas_tokens(void *fdt, int rtas); 664 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 665 666 #define SPAPR_TCE_PAGE_SHIFT 12 667 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 668 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 669 670 #define SPAPR_VIO_BASE_LIOBN 0x00000000 671 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 672 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 673 (0x80000000 | ((phb_index) << 8) | (window_num)) 674 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 675 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 676 677 #define RTAS_ERROR_LOG_MAX 2048 678 679 #define RTAS_EVENT_SCAN_RATE 1 680 681 /* This helper should be used to encode interrupt specifiers when the related 682 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 683 * VIO devices, RTAS event sources and PHBs). 684 */ 685 static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi) 686 { 687 intspec[0] = cpu_to_be32(irq); 688 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 689 } 690 691 typedef struct sPAPRTCETable sPAPRTCETable; 692 693 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 694 #define SPAPR_TCE_TABLE(obj) \ 695 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 696 697 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 698 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 699 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 700 701 struct sPAPRTCETable { 702 DeviceState parent; 703 uint32_t liobn; 704 uint32_t nb_table; 705 uint64_t bus_offset; 706 uint32_t page_shift; 707 uint64_t *table; 708 uint32_t mig_nb_table; 709 uint64_t *mig_table; 710 bool bypass; 711 bool need_vfio; 712 int fd; 713 MemoryRegion root; 714 IOMMUMemoryRegion iommu; 715 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 716 QLIST_ENTRY(sPAPRTCETable) list; 717 }; 718 719 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 720 721 struct sPAPREventLogEntry { 722 uint32_t summary; 723 uint32_t extended_length; 724 void *extended_log; 725 QTAILQ_ENTRY(sPAPREventLogEntry) next; 726 }; 727 728 void spapr_events_init(sPAPRMachineState *sm); 729 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 730 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 731 target_ulong addr, target_ulong size, 732 sPAPROptionVector *ov5_updates); 733 void close_htab_fd(sPAPRMachineState *spapr); 734 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 735 void spapr_free_hpt(sPAPRMachineState *spapr); 736 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 737 void spapr_tce_table_enable(sPAPRTCETable *tcet, 738 uint32_t page_shift, uint64_t bus_offset, 739 uint32_t nb_table); 740 void spapr_tce_table_disable(sPAPRTCETable *tcet); 741 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 742 743 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 744 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 745 uint32_t liobn, uint64_t window, uint32_t size); 746 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 747 sPAPRTCETable *tcet); 748 void spapr_pci_switch_vga(bool big_endian); 749 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 750 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 751 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 752 uint32_t count); 753 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 754 uint32_t count); 755 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 756 uint32_t count, uint32_t index); 757 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 758 uint32_t count, uint32_t index); 759 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 760 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 761 Error **errp); 762 void spapr_clear_pending_events(sPAPRMachineState *spapr); 763 int spapr_max_server_number(sPAPRMachineState *spapr); 764 765 /* CPU and LMB DRC release callbacks. */ 766 void spapr_core_release(DeviceState *dev); 767 void spapr_lmb_release(DeviceState *dev); 768 769 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 770 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 771 772 #define TYPE_SPAPR_RNG "spapr-rng" 773 774 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 775 776 /* 777 * This defines the maximum number of DIMM slots we can have for sPAPR 778 * guest. This is not defined by sPAPR but we are defining it to 32 slots 779 * based on default number of slots provided by PowerPC kernel. 780 */ 781 #define SPAPR_MAX_RAM_SLOTS 32 782 783 /* 1GB alignment for hotplug memory region */ 784 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 785 786 /* 787 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 788 * property under ibm,dynamic-reconfiguration-memory node. 789 */ 790 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 791 792 /* 793 * Defines for flag value in ibm,dynamic-memory property under 794 * ibm,dynamic-reconfiguration-memory node. 795 */ 796 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 797 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 798 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 799 800 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 801 802 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 803 804 int spapr_get_vcpu_id(PowerPCCPU *cpu); 805 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 806 PowerPCCPU *spapr_find_cpu(int vcpu_id); 807 808 int spapr_caps_pre_load(void *opaque); 809 int spapr_caps_pre_save(void *opaque); 810 811 /* 812 * Handling of optional capabilities 813 */ 814 extern const VMStateDescription vmstate_spapr_cap_htm; 815 extern const VMStateDescription vmstate_spapr_cap_vsx; 816 extern const VMStateDescription vmstate_spapr_cap_dfp; 817 extern const VMStateDescription vmstate_spapr_cap_cfpc; 818 extern const VMStateDescription vmstate_spapr_cap_sbbc; 819 extern const VMStateDescription vmstate_spapr_cap_ibs; 820 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 821 822 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap) 823 { 824 return spapr->eff.caps[cap]; 825 } 826 827 void spapr_caps_init(sPAPRMachineState *spapr); 828 void spapr_caps_apply(sPAPRMachineState *spapr); 829 void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu); 830 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); 831 int spapr_caps_post_migration(sPAPRMachineState *spapr); 832 833 void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize, 834 Error **errp); 835 /* 836 * XIVE definitions 837 */ 838 #define SPAPR_OV5_XIVE_LEGACY 0x0 839 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 840 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 841 842 #endif /* HW_SPAPR_H */ 843