1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "sysemu/dma.h" 5 #include "hw/boards.h" 6 #include "hw/ppc/xics.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 10 struct VIOsPAPRBus; 11 struct sPAPRPHBState; 12 struct sPAPRNVRAM; 13 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState; 14 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 15 16 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 17 #define SPAPR_ENTRY_POINT 0x100 18 19 #define SPAPR_TIMEBASE_FREQ 512000000ULL 20 21 typedef struct sPAPRMachineClass sPAPRMachineClass; 22 typedef struct sPAPRMachineState sPAPRMachineState; 23 24 #define TYPE_SPAPR_MACHINE "spapr-machine" 25 #define SPAPR_MACHINE(obj) \ 26 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 27 #define SPAPR_MACHINE_GET_CLASS(obj) \ 28 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 29 #define SPAPR_MACHINE_CLASS(klass) \ 30 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 31 32 /** 33 * sPAPRMachineClass: 34 */ 35 struct sPAPRMachineClass { 36 /*< private >*/ 37 MachineClass parent_class; 38 39 /*< public >*/ 40 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 41 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 42 const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */ 43 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 44 uint64_t *buid, hwaddr *pio, 45 hwaddr *mmio32, hwaddr *mmio64, 46 unsigned n_dma, uint32_t *liobns, Error **errp); 47 }; 48 49 /** 50 * sPAPRMachineState: 51 */ 52 struct sPAPRMachineState { 53 /*< private >*/ 54 MachineState parent_obj; 55 56 struct VIOsPAPRBus *vio_bus; 57 QLIST_HEAD(, sPAPRPHBState) phbs; 58 struct sPAPRNVRAM *nvram; 59 XICSState *xics; 60 DeviceState *rtc; 61 62 void *htab; 63 uint32_t htab_shift; 64 hwaddr rma_size; 65 int vrma_adjust; 66 hwaddr fdt_addr, rtas_addr; 67 ssize_t rtas_size; 68 void *rtas_blob; 69 void *fdt_skel; 70 uint64_t rtc_offset; /* Now used only during incoming migration */ 71 struct PPCTimebase tb; 72 bool has_graphics; 73 74 uint32_t check_exception_irq; 75 Notifier epow_notifier; 76 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 77 78 /* Migration state */ 79 int htab_save_index; 80 bool htab_first_pass; 81 int htab_fd; 82 83 /* RTAS state */ 84 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list; 85 86 /*< public >*/ 87 char *kvm_type; 88 MemoryHotplugState hotplug_memory; 89 Object **cores; 90 }; 91 92 #define H_SUCCESS 0 93 #define H_BUSY 1 /* Hardware busy -- retry later */ 94 #define H_CLOSED 2 /* Resource closed */ 95 #define H_NOT_AVAILABLE 3 96 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 97 #define H_PARTIAL 5 98 #define H_IN_PROGRESS 14 /* Kind of like busy */ 99 #define H_PAGE_REGISTERED 15 100 #define H_PARTIAL_STORE 16 101 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 102 #define H_CONTINUE 18 /* Returned from H_Join on success */ 103 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 104 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 105 is a good time to retry */ 106 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 107 is a good time to retry */ 108 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 109 is a good time to retry */ 110 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 111 is a good time to retry */ 112 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 113 is a good time to retry */ 114 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 115 is a good time to retry */ 116 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 117 #define H_HARDWARE -1 /* Hardware error */ 118 #define H_FUNCTION -2 /* Function not supported */ 119 #define H_PRIVILEGE -3 /* Caller not privileged */ 120 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 121 #define H_BAD_MODE -5 /* Illegal msr value */ 122 #define H_PTEG_FULL -6 /* PTEG is full */ 123 #define H_NOT_FOUND -7 /* PTE was not found" */ 124 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 125 #define H_NO_MEM -9 126 #define H_AUTHORITY -10 127 #define H_PERMISSION -11 128 #define H_DROPPED -12 129 #define H_SOURCE_PARM -13 130 #define H_DEST_PARM -14 131 #define H_REMOTE_PARM -15 132 #define H_RESOURCE -16 133 #define H_ADAPTER_PARM -17 134 #define H_RH_PARM -18 135 #define H_RCQ_PARM -19 136 #define H_SCQ_PARM -20 137 #define H_EQ_PARM -21 138 #define H_RT_PARM -22 139 #define H_ST_PARM -23 140 #define H_SIGT_PARM -24 141 #define H_TOKEN_PARM -25 142 #define H_MLENGTH_PARM -27 143 #define H_MEM_PARM -28 144 #define H_MEM_ACCESS_PARM -29 145 #define H_ATTR_PARM -30 146 #define H_PORT_PARM -31 147 #define H_MCG_PARM -32 148 #define H_VL_PARM -33 149 #define H_TSIZE_PARM -34 150 #define H_TRACE_PARM -35 151 152 #define H_MASK_PARM -37 153 #define H_MCG_FULL -38 154 #define H_ALIAS_EXIST -39 155 #define H_P_COUNTER -40 156 #define H_TABLE_FULL -41 157 #define H_ALT_TABLE -42 158 #define H_MR_CONDITION -43 159 #define H_NOT_ENOUGH_RESOURCES -44 160 #define H_R_STATE -45 161 #define H_RESCINDEND -46 162 #define H_P2 -55 163 #define H_P3 -56 164 #define H_P4 -57 165 #define H_P5 -58 166 #define H_P6 -59 167 #define H_P7 -60 168 #define H_P8 -61 169 #define H_P9 -62 170 #define H_UNSUPPORTED_FLAG -256 171 #define H_MULTI_THREADS_ACTIVE -9005 172 173 174 /* Long Busy is a condition that can be returned by the firmware 175 * when a call cannot be completed now, but the identical call 176 * should be retried later. This prevents calls blocking in the 177 * firmware for long periods of time. Annoyingly the firmware can return 178 * a range of return codes, hinting at how long we should wait before 179 * retrying. If you don't care for the hint, the macro below is a good 180 * way to check for the long_busy return codes 181 */ 182 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 183 && (x <= H_LONG_BUSY_END_RANGE)) 184 185 /* Flags */ 186 #define H_LARGE_PAGE (1ULL<<(63-16)) 187 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 188 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 189 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 190 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 191 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 192 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 193 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 194 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 195 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 196 #define H_ANDCOND (1ULL<<(63-33)) 197 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 198 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 199 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 200 #define H_COPY_PAGE (1ULL<<(63-49)) 201 #define H_N (1ULL<<(63-61)) 202 #define H_PP1 (1ULL<<(63-62)) 203 #define H_PP2 (1ULL<<(63-63)) 204 205 /* Values for 2nd argument to H_SET_MODE */ 206 #define H_SET_MODE_RESOURCE_SET_CIABR 1 207 #define H_SET_MODE_RESOURCE_SET_DAWR 2 208 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 209 #define H_SET_MODE_RESOURCE_LE 4 210 211 /* Flags for H_SET_MODE_RESOURCE_LE */ 212 #define H_SET_MODE_ENDIAN_BIG 0 213 #define H_SET_MODE_ENDIAN_LITTLE 1 214 215 /* VASI States */ 216 #define H_VASI_INVALID 0 217 #define H_VASI_ENABLED 1 218 #define H_VASI_ABORTED 2 219 #define H_VASI_SUSPENDING 3 220 #define H_VASI_SUSPENDED 4 221 #define H_VASI_RESUMED 5 222 #define H_VASI_COMPLETED 6 223 224 /* DABRX flags */ 225 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 226 #define H_DABRX_KERNEL (1ULL<<(63-62)) 227 #define H_DABRX_USER (1ULL<<(63-63)) 228 229 /* Each control block has to be on a 4K boundary */ 230 #define H_CB_ALIGNMENT 4096 231 232 /* pSeries hypervisor opcodes */ 233 #define H_REMOVE 0x04 234 #define H_ENTER 0x08 235 #define H_READ 0x0c 236 #define H_CLEAR_MOD 0x10 237 #define H_CLEAR_REF 0x14 238 #define H_PROTECT 0x18 239 #define H_GET_TCE 0x1c 240 #define H_PUT_TCE 0x20 241 #define H_SET_SPRG0 0x24 242 #define H_SET_DABR 0x28 243 #define H_PAGE_INIT 0x2c 244 #define H_SET_ASR 0x30 245 #define H_ASR_ON 0x34 246 #define H_ASR_OFF 0x38 247 #define H_LOGICAL_CI_LOAD 0x3c 248 #define H_LOGICAL_CI_STORE 0x40 249 #define H_LOGICAL_CACHE_LOAD 0x44 250 #define H_LOGICAL_CACHE_STORE 0x48 251 #define H_LOGICAL_ICBI 0x4c 252 #define H_LOGICAL_DCBF 0x50 253 #define H_GET_TERM_CHAR 0x54 254 #define H_PUT_TERM_CHAR 0x58 255 #define H_REAL_TO_LOGICAL 0x5c 256 #define H_HYPERVISOR_DATA 0x60 257 #define H_EOI 0x64 258 #define H_CPPR 0x68 259 #define H_IPI 0x6c 260 #define H_IPOLL 0x70 261 #define H_XIRR 0x74 262 #define H_PERFMON 0x7c 263 #define H_MIGRATE_DMA 0x78 264 #define H_REGISTER_VPA 0xDC 265 #define H_CEDE 0xE0 266 #define H_CONFER 0xE4 267 #define H_PROD 0xE8 268 #define H_GET_PPP 0xEC 269 #define H_SET_PPP 0xF0 270 #define H_PURR 0xF4 271 #define H_PIC 0xF8 272 #define H_REG_CRQ 0xFC 273 #define H_FREE_CRQ 0x100 274 #define H_VIO_SIGNAL 0x104 275 #define H_SEND_CRQ 0x108 276 #define H_COPY_RDMA 0x110 277 #define H_REGISTER_LOGICAL_LAN 0x114 278 #define H_FREE_LOGICAL_LAN 0x118 279 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 280 #define H_SEND_LOGICAL_LAN 0x120 281 #define H_BULK_REMOVE 0x124 282 #define H_MULTICAST_CTRL 0x130 283 #define H_SET_XDABR 0x134 284 #define H_STUFF_TCE 0x138 285 #define H_PUT_TCE_INDIRECT 0x13C 286 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 287 #define H_VTERM_PARTNER_INFO 0x150 288 #define H_REGISTER_VTERM 0x154 289 #define H_FREE_VTERM 0x158 290 #define H_RESET_EVENTS 0x15C 291 #define H_ALLOC_RESOURCE 0x160 292 #define H_FREE_RESOURCE 0x164 293 #define H_MODIFY_QP 0x168 294 #define H_QUERY_QP 0x16C 295 #define H_REREGISTER_PMR 0x170 296 #define H_REGISTER_SMR 0x174 297 #define H_QUERY_MR 0x178 298 #define H_QUERY_MW 0x17C 299 #define H_QUERY_HCA 0x180 300 #define H_QUERY_PORT 0x184 301 #define H_MODIFY_PORT 0x188 302 #define H_DEFINE_AQP1 0x18C 303 #define H_GET_TRACE_BUFFER 0x190 304 #define H_DEFINE_AQP0 0x194 305 #define H_RESIZE_MR 0x198 306 #define H_ATTACH_MCQP 0x19C 307 #define H_DETACH_MCQP 0x1A0 308 #define H_CREATE_RPT 0x1A4 309 #define H_REMOVE_RPT 0x1A8 310 #define H_REGISTER_RPAGES 0x1AC 311 #define H_DISABLE_AND_GETC 0x1B0 312 #define H_ERROR_DATA 0x1B4 313 #define H_GET_HCA_INFO 0x1B8 314 #define H_GET_PERF_COUNT 0x1BC 315 #define H_MANAGE_TRACE 0x1C0 316 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 317 #define H_QUERY_INT_STATE 0x1E4 318 #define H_POLL_PENDING 0x1D8 319 #define H_ILLAN_ATTRIBUTES 0x244 320 #define H_MODIFY_HEA_QP 0x250 321 #define H_QUERY_HEA_QP 0x254 322 #define H_QUERY_HEA 0x258 323 #define H_QUERY_HEA_PORT 0x25C 324 #define H_MODIFY_HEA_PORT 0x260 325 #define H_REG_BCMC 0x264 326 #define H_DEREG_BCMC 0x268 327 #define H_REGISTER_HEA_RPAGES 0x26C 328 #define H_DISABLE_AND_GET_HEA 0x270 329 #define H_GET_HEA_INFO 0x274 330 #define H_ALLOC_HEA_RESOURCE 0x278 331 #define H_ADD_CONN 0x284 332 #define H_DEL_CONN 0x288 333 #define H_JOIN 0x298 334 #define H_VASI_STATE 0x2A4 335 #define H_ENABLE_CRQ 0x2B0 336 #define H_GET_EM_PARMS 0x2B8 337 #define H_SET_MPP 0x2D0 338 #define H_GET_MPP 0x2D4 339 #define H_XIRR_X 0x2FC 340 #define H_RANDOM 0x300 341 #define H_SET_MODE 0x31C 342 #define MAX_HCALL_OPCODE H_SET_MODE 343 344 /* The hcalls above are standardized in PAPR and implemented by pHyp 345 * as well. 346 * 347 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 348 * So far we just need one for H_RTAS, but in future we'll need more 349 * for extensions like virtio. We put those into the 0xf000-0xfffc 350 * range which is reserved by PAPR for "platform-specific" hcalls. 351 */ 352 #define KVMPPC_HCALL_BASE 0xf000 353 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 354 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 355 /* Client Architecture support */ 356 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 357 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 358 359 typedef struct sPAPRDeviceTreeUpdateHeader { 360 uint32_t version_id; 361 } sPAPRDeviceTreeUpdateHeader; 362 363 #define hcall_dprintf(fmt, ...) \ 364 do { \ 365 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 366 } while (0) 367 368 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 369 target_ulong opcode, 370 target_ulong *args); 371 372 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 373 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 374 target_ulong *args); 375 376 /* ibm,set-eeh-option */ 377 #define RTAS_EEH_DISABLE 0 378 #define RTAS_EEH_ENABLE 1 379 #define RTAS_EEH_THAW_IO 2 380 #define RTAS_EEH_THAW_DMA 3 381 382 /* ibm,get-config-addr-info2 */ 383 #define RTAS_GET_PE_ADDR 0 384 #define RTAS_GET_PE_MODE 1 385 #define RTAS_PE_MODE_NONE 0 386 #define RTAS_PE_MODE_NOT_SHARED 1 387 #define RTAS_PE_MODE_SHARED 2 388 389 /* ibm,read-slot-reset-state2 */ 390 #define RTAS_EEH_PE_STATE_NORMAL 0 391 #define RTAS_EEH_PE_STATE_RESET 1 392 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 393 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 394 #define RTAS_EEH_PE_STATE_UNAVAIL 5 395 #define RTAS_EEH_NOT_SUPPORT 0 396 #define RTAS_EEH_SUPPORT 1 397 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 398 #define RTAS_EEH_PE_RECOVER_INFO 0 399 400 /* ibm,set-slot-reset */ 401 #define RTAS_SLOT_RESET_DEACTIVATE 0 402 #define RTAS_SLOT_RESET_HOT 1 403 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 404 405 /* ibm,slot-error-detail */ 406 #define RTAS_SLOT_TEMP_ERR_LOG 1 407 #define RTAS_SLOT_PERM_ERR_LOG 2 408 409 /* RTAS return codes */ 410 #define RTAS_OUT_SUCCESS 0 411 #define RTAS_OUT_NO_ERRORS_FOUND 1 412 #define RTAS_OUT_HW_ERROR -1 413 #define RTAS_OUT_BUSY -2 414 #define RTAS_OUT_PARAM_ERROR -3 415 #define RTAS_OUT_NOT_SUPPORTED -3 416 #define RTAS_OUT_NO_SUCH_INDICATOR -3 417 #define RTAS_OUT_NOT_AUTHORIZED -9002 418 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 419 420 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 421 #define RTAS_DDW_PGSIZE_4K 0x01 422 #define RTAS_DDW_PGSIZE_64K 0x02 423 #define RTAS_DDW_PGSIZE_16M 0x04 424 #define RTAS_DDW_PGSIZE_32M 0x08 425 #define RTAS_DDW_PGSIZE_64M 0x10 426 #define RTAS_DDW_PGSIZE_128M 0x20 427 #define RTAS_DDW_PGSIZE_256M 0x40 428 #define RTAS_DDW_PGSIZE_16G 0x80 429 430 /* RTAS tokens */ 431 #define RTAS_TOKEN_BASE 0x2000 432 433 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 434 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 435 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 436 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 437 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 438 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 439 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 440 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 441 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 442 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 443 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 444 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 445 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 446 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 447 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 448 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 449 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 450 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 451 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 452 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 453 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 454 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 455 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 456 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 457 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 458 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 459 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 460 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 461 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 462 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 463 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 464 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 465 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 466 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 467 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 468 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 469 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 470 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 471 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 472 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 473 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 474 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 475 476 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 477 478 /* RTAS ibm,get-system-parameter token values */ 479 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 480 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 481 #define RTAS_SYSPARM_UUID 48 482 483 /* RTAS indicator/sensor types 484 * 485 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 486 * 487 * NOTE: currently only DR-related sensors are implemented here 488 */ 489 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 490 #define RTAS_SENSOR_TYPE_DR 9002 491 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 492 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 493 494 /* Possible values for the platform-processor-diagnostics-run-mode parameter 495 * of the RTAS ibm,get-system-parameter call. 496 */ 497 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 498 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 499 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 500 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 501 502 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 503 { 504 return addr & ~0xF000000000000000ULL; 505 } 506 507 static inline uint32_t rtas_ld(target_ulong phys, int n) 508 { 509 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 510 } 511 512 static inline uint64_t rtas_ldq(target_ulong phys, int n) 513 { 514 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 515 } 516 517 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 518 { 519 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 520 } 521 522 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 523 uint32_t token, 524 uint32_t nargs, target_ulong args, 525 uint32_t nret, target_ulong rets); 526 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 527 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 528 uint32_t token, uint32_t nargs, target_ulong args, 529 uint32_t nret, target_ulong rets); 530 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 531 hwaddr rtas_size); 532 533 #define SPAPR_TCE_PAGE_SHIFT 12 534 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 535 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 536 537 #define SPAPR_VIO_BASE_LIOBN 0x00000000 538 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 539 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 540 (0x80000000 | ((phb_index) << 8) | (window_num)) 541 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 542 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 543 544 #define RTAS_ERROR_LOG_MAX 2048 545 546 #define RTAS_EVENT_SCAN_RATE 1 547 548 typedef struct sPAPRTCETable sPAPRTCETable; 549 550 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 551 #define SPAPR_TCE_TABLE(obj) \ 552 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 553 554 struct sPAPRTCETable { 555 DeviceState parent; 556 uint32_t liobn; 557 uint32_t nb_table; 558 uint64_t bus_offset; 559 uint32_t page_shift; 560 uint64_t *table; 561 uint32_t mig_nb_table; 562 uint64_t *mig_table; 563 bool bypass; 564 bool need_vfio; 565 int fd; 566 MemoryRegion root, iommu; 567 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 568 QLIST_ENTRY(sPAPRTCETable) list; 569 }; 570 571 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 572 573 struct sPAPREventLogEntry { 574 int log_type; 575 bool exception; 576 void *data; 577 QTAILQ_ENTRY(sPAPREventLogEntry) next; 578 }; 579 580 void spapr_events_init(sPAPRMachineState *sm); 581 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 582 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 583 target_ulong addr, target_ulong size, 584 bool cpu_update, bool memory_update); 585 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 586 void spapr_tce_table_enable(sPAPRTCETable *tcet, 587 uint32_t page_shift, uint64_t bus_offset, 588 uint32_t nb_table); 589 void spapr_tce_table_disable(sPAPRTCETable *tcet); 590 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 591 592 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 593 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 594 uint32_t liobn, uint64_t window, uint32_t size); 595 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 596 sPAPRTCETable *tcet); 597 void spapr_pci_switch_vga(bool big_endian); 598 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 599 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 600 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 601 uint32_t count); 602 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 603 uint32_t count); 604 void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp); 605 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 606 sPAPRMachineState *spapr); 607 608 /* rtas-configure-connector state */ 609 struct sPAPRConfigureConnectorState { 610 uint32_t drc_index; 611 int fdt_offset; 612 int fdt_depth; 613 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next; 614 }; 615 616 void spapr_ccs_reset_hook(void *opaque); 617 618 #define TYPE_SPAPR_RTC "spapr-rtc" 619 #define TYPE_SPAPR_RNG "spapr-rng" 620 621 void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); 622 int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); 623 624 int spapr_rng_populate_dt(void *fdt); 625 626 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 627 628 /* 629 * This defines the maximum number of DIMM slots we can have for sPAPR 630 * guest. This is not defined by sPAPR but we are defining it to 32 slots 631 * based on default number of slots provided by PowerPC kernel. 632 */ 633 #define SPAPR_MAX_RAM_SLOTS 32 634 635 /* 1GB alignment for hotplug memory region */ 636 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) 637 638 /* 639 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 640 * property under ibm,dynamic-reconfiguration-memory node. 641 */ 642 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 643 644 /* 645 * Defines for flag value in ibm,dynamic-memory property under 646 * ibm,dynamic-reconfiguration-memory node. 647 */ 648 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 649 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 650 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 651 652 #endif /* HW_SPAPR_H */ 653